o procps 3.2.0 # ps --version
o oprofile 0.9 # oprofiled --version
o udev 081 # udevinfo -V
+o grub 0.93 # grub --version
Kernel compilation
==================
Prefix: 'adm1030'
Addresses scanned: I2C 0x2c to 0x2e
Datasheet: Publicly available at the Analog Devices website
- http://products.analog.com/products/info.asp?product=ADM1030
+ http://www.analog.com/en/prod/0%2C2877%2CADM1030%2C00.html
* Analog Devices ADM1031
Prefix: 'adm1031'
Addresses scanned: I2C 0x2c to 0x2e
Datasheet: Publicly available at the Analog Devices website
- http://products.analog.com/products/info.asp?product=ADM1031
+ http://www.analog.com/en/prod/0%2C2877%2CADM1031%2C00.html
Authors:
Alexandre d'Alton <alex@alexdalton.org>
--- /dev/null
+Kernel driver thmc50
+=====================
+
+Supported chips:
+ * Analog Devices ADM1022
+ Prefix: 'adm1022'
+ Addresses scanned: I2C 0x2c - 0x2e
+ Datasheet: http://www.analog.com/en/prod/0,2877,ADM1022,00.html
+ * Texas Instruments THMC50
+ Prefix: 'thmc50'
+ Addresses scanned: I2C 0x2c - 0x2e
+ Datasheet: http://focus.ti.com/docs/prod/folders/print/thmc50.html
+
+Author: Krzysztof Helt <krzysztof.h1@wp.pl>
+
+This driver was derived from the 2.4 kernel thmc50.c source file.
+
+Credits:
+ thmc50.c (2.4 kernel):
+ Frodo Looijaard <frodol@dds.nl>
+ Philip Edelbrock <phil@netroedge.com>
+
+Module Parameters
+-----------------
+
+* adm1022_temp3: short array
+ List of adapter,address pairs to force chips into ADM1022 mode with
+ second remote temperature. This does not work for original THMC50 chips.
+
+Description
+-----------
+
+The THMC50 implements: an internal temperature sensor, support for an
+external diode-type temperature sensor (compatible w/ the diode sensor inside
+many processors), and a controllable fan/analog_out DAC. For the temperature
+sensors, limits can be set through the appropriate Overtemperature Shutdown
+register and Hysteresis register. Each value can be set and read to half-degree
+accuracy. An alarm is issued (usually to a connected LM78) when the
+temperature gets higher then the Overtemperature Shutdown value; it stays on
+until the temperature falls below the Hysteresis value. All temperatures are in
+degrees Celsius, and are guaranteed within a range of -55 to +125 degrees.
+
+The THMC50 only updates its values each 1.5 seconds; reading it more often
+will do no harm, but will return 'old' values.
+
+The THMC50 is usually used in combination with LM78-like chips, to measure
+the temperature of the processor(s).
+
+The ADM1022 works the same as THMC50 but it is faster (5 Hz instead of
+1 Hz for THMC50). It can be also put in a new mode to handle additional
+remote temperature sensor. The driver use the mode set by BIOS by default.
+
+In case the BIOS is broken and the mode is set incorrectly, you can force
+the mode with additional remote temperature with adm1022_temp3 parameter.
+A typical symptom of wrong setting is a fan forced to full speed.
+
+Driver Features
+---------------
+
+The driver provides up to three temperatures:
+
+temp1 -- internal
+temp2 -- remote
+temp3 -- 2nd remote only for ADM1022
+
+pwm1 -- fan speed (0 = stop, 255 = full)
+pwm1_mode -- always 0 (DC mode)
+
+The value of 0 for pwm1 also forces FAN_OFF signal from the chip,
+so it stops fans even if the value 0 into the ANALOG_OUT register does not.
+
+The driver was tested on Compaq AP550 with two ADM1022 chips (one works
+in the temp3 mode), five temperature readings and two fans.
+
W: http://blackfin.uclinux.org
S: Supported
+BLACKFIN WATCHDOG DRIVER
+P: Mike Frysinger
+M: michael.frysinger@analog.com
+M: vapier.adi@gmail.com
+L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only)
+W: http://blackfin.uclinux.org
+S: Supported
+
BAYCOM/HDLCDRV DRIVERS FOR AX.25
P: Thomas Sailer
M: t.sailer@alumni.ethz.ch
W: http://www.linux-usb.org/gadget
S: Maintained
-USB HID/HIDBP DRIVERS
+USB HID/HIDBP DRIVERS (USB KEYBOARDS, MICE, REMOTE CONTROLS, ...)
P: Jiri Kosina
M: jkosina@suse.cz
L: linux-usb-devel@lists.sourceforge.net
__reg_MB86943_pci_sl_mem_base = __region_CS2 + 0x08000000;
mb();
- *(volatile unsigned long *)(__region_CS2+0x01300014) == 1;
+ /* enable PCI arbitration */
+ __reg_MB86943_pci_arbiter = MB86943_PCIARB_EN;
ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff;
ax = 0x4800;
dx = devno;
asm("pushfl; int $0x13; popfl"
- : "+a" (ax), "+d" (dx)
+ : "+a" (ax), "+d" (dx), "=m" (ei->params)
: "S" (&ei->params)
: "ebx", "ecx", "edi");
dx = 0; /* EDID block number */
di =(size_t) &boot_params.edid_info; /* (ES:)Pointer to block */
asm(INT10
- : "+a" (ax), "+b" (bx), "+d" (dx)
+ : "+a" (ax), "+b" (bx), "+d" (dx), "=m" (boot_params.edid_info)
: "c" (cx), "D" (di)
: "esi");
#endif /* CONFIG_FIRMWARE_EDID */
#include <linux/uio.h>
#include <linux/nfs_fs.h>
#include <linux/quota.h>
-#include <linux/syscalls.h>
#include <linux/sunrpc/svc.h>
#include <linux/nfsd/nfsd.h>
#include <linux/nfsd/cache.h>
static struct iosapic_intr_info {
struct list_head rtes; /* RTEs using this vector (empty =>
* not an IOSAPIC interrupt) */
- int count; /* # of RTEs that shares this vector */
+ int count; /* # of registered RTEs */
u32 low32; /* current value of low word of
* Redirection table entry */
unsigned int dest; /* destination CPU physical ID */
int rte_index;
struct iosapic_rte_info *rte;
- if (list_empty(&iosapic_intr_info[irq].rtes))
+ if (!iosapic_intr_info[irq].count)
return; /* not an IOSAPIC interrupt! */
/* set only the mask bit */
int rte_index;
struct iosapic_rte_info *rte;
- if (list_empty(&iosapic_intr_info[irq].rtes))
+ if (!iosapic_intr_info[irq].count)
return; /* not an IOSAPIC interrupt! */
low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK;
dest = cpu_physical_id(first_cpu(mask));
- if (list_empty(&iosapic_intr_info[irq].rtes))
+ if (!iosapic_intr_info[irq].count)
return; /* not an IOSAPIC interrupt */
set_irq_affinity_info(irq, dest, redir);
{
int new_irq;
- if (!list_empty(&iosapic_intr_info[irq].rtes)) {
+ if (iosapic_intr_info[irq].count) {
new_irq = create_irq();
if (new_irq < 0)
panic("%s: out of interrupt vectors!\n", __FUNCTION__);
}
}
-static struct iosapic_rte_info *iosapic_alloc_rte (void)
+static struct iosapic_rte_info * __init_refok iosapic_alloc_rte (void)
{
int i;
struct iosapic_rte_info *rte;
* In case of vector shared by multiple RTEs, all RTEs that
* share the vector need to use the same destination CPU.
*/
- if (!list_empty(&iosapic_intr_info[irq].rtes))
+ if (iosapic_intr_info[irq].count)
return iosapic_intr_info[irq].dest;
/*
err = register_intr(gsi, irq, IOSAPIC_LOWEST_PRIORITY,
polarity, trigger);
if (err < 0) {
+ spin_unlock(&irq_desc[irq].lock);
irq = err;
- goto unlock_all;
+ goto unlock_iosapic_lock;
}
/*
gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
(polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
cpu_logical_id(dest), dest, irq_to_vector(irq));
- unlock_all:
+
spin_unlock(&irq_desc[irq].lock);
unlock_iosapic_lock:
spin_unlock_irqrestore(&iosapic_lock, flags);
return -1;
}
-static void reserve_irq(unsigned int irq)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&vector_lock, flags);
- irq_status[irq] = IRQ_RSVD;
- spin_unlock_irqrestore(&vector_lock, flags);
-}
-
static inline int find_unassigned_irq(void)
{
int irq;
void destroy_and_reserve_irq(unsigned int irq)
{
+ unsigned long flags;
+
dynamic_irq_cleanup(irq);
- clear_irq_vector(irq);
- reserve_irq(irq);
+ spin_lock_irqsave(&vector_lock, flags);
+ __clear_irq_vector(irq);
+ irq_status[irq] = IRQ_RSVD;
+ spin_unlock_irqrestore(&vector_lock, flags);
}
static int __reassign_irq_vector(int irq, int cpu)
strncpy(p->comm, type, sizeof(p->comm)-1);
}
-/* Do per-CPU MCA-related initialization. */
+/* Caller prevents this from being called after init */
+static void * __init_refok mca_bootmem(void)
+{
+ void *p;
+ p = alloc_bootmem(sizeof(struct ia64_mca_cpu) * NR_CPUS +
+ KERNEL_STACK_SIZE);
+ return (void *)ALIGN((unsigned long)p, KERNEL_STACK_SIZE);
+}
+
+/* Do per-CPU MCA-related initialization. */
void __cpuinit
ia64_mca_cpu_init(void *cpu_data)
{
int cpu;
first_time = 0;
- mca_data = alloc_bootmem(sizeof(struct ia64_mca_cpu)
- * NR_CPUS + KERNEL_STACK_SIZE);
- mca_data = (void *)(((unsigned long)mca_data +
- KERNEL_STACK_SIZE - 1) &
- (-KERNEL_STACK_SIZE));
+ mca_data = mca_bootmem();
for (cpu = 0; cpu < NR_CPUS; cpu++) {
format_mca_init_stack(mca_data,
offsetof(struct ia64_mca_cpu, mca_stack),
#include <asm/smp.h>
#include <asm/system.h>
#include <asm/unistd.h>
-#include <asm/system.h>
#if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
# error "struct cpuinfo_ia64 too big!"
}
/*
- * Run a function on another CPU
+ * Run a function on a specific CPU
* <func> The function to run. This must be fast and non-blocking.
* <info> An arbitrary pointer to pass to the function.
* <nonatomic> Currently unused.
int me = get_cpu(); /* prevent preemption and reschedule on another processor */
if (cpuid == me) {
- printk(KERN_INFO "%s: trying to call self\n", __FUNCTION__);
+ local_irq_disable();
+ func(info);
+ local_irq_enable();
put_cpu();
- return -EBUSY;
+ return 0;
}
data.func = func;
if (!nojitter)
itc_jitter_data.itc_jitter = 1;
#endif
- }
+ } else
+ /*
+ * ITC is drifty and we have not synchronized the ITCs in smpboot.c.
+ * ITC values may fluctuate significantly between processors.
+ * Clock should not be used for hrtimers. Mark itc as only
+ * useful for boot and testing.
+ *
+ * Note that jitter compensation is off! There is no point of
+ * synchronizing ITCs since they may be large differentials
+ * that change over time.
+ *
+ * The only way to fix this would be to repeatedly sync the
+ * ITCs. Until that time we have to avoid ITC.
+ */
+ clocksource_itc.rating = 50;
/* Setup the CPU local timer tick */
ia64_cpu_local_tick();
* hubdev_init_node() - Creates the HUB data structure and link them to it's
* own NODE specific data area.
*/
-void hubdev_init_node(nodepda_t * npda, cnodeid_t node)
+void __init hubdev_init_node(nodepda_t * npda, cnodeid_t node)
{
struct hubdev_info *hubdev_info;
int size;
#include <linux/interrupt.h>
#include <linux/acpi.h>
#include <linux/compiler.h>
-#include <linux/sched.h>
#include <linux/root_dev.h>
#include <linux/nodemask.h>
#include <linux/pm.h>
extern unsigned long sn_rtc_cycles_per_second;
-static void __iomem *sn2_mc;
-
static cycle_t read_sn2(void)
{
- return (cycle_t)readq(sn2_mc);
+ return (cycle_t)readq(RTC_COUNTER_ADDR);
}
static struct clocksource clocksource_sn2 = {
.name = "sn2_rtc",
- .rating = 300,
+ .rating = 450,
.read = read_sn2,
.mask = (1LL << 55) - 1,
.mult = 0,
void __init sn_timer_init(void)
{
- sn2_mc = RTC_COUNTER_ADDR;
clocksource_sn2.fsys_mmio = RTC_COUNTER_ADDR;
clocksource_sn2.mult = clocksource_hz2mult(sn_rtc_cycles_per_second,
clocksource_sn2.shift);
prompt "System type"
default SGI_IP22
-config LEMOTE_FULONG
- bool "Lemote Fulong mini-PC"
- select ARCH_SPARSEMEM_ENABLE
- select SYS_HAS_CPU_LOONGSON2
- select DMA_NONCOHERENT
- select BOOT_ELF32
- select BOARD_SCACHE
- select HAVE_STD_PC_SERIAL_PORT
- select HW_HAS_PCI
- select I8259
- select ISA
- select IRQ_CPU
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select SYS_SUPPORTS_HIGHMEM
- select SYS_HAS_EARLY_PRINTK
- select GENERIC_HARDIRQS_NO__DO_IRQ
- select CPU_HAS_WB
- help
- Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and
- an FPGA northbridge
-
config MACH_ALCHEMY
bool "Alchemy processor based machines"
Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
Olivetti M700-10 workstations.
+config LEMOTE_FULONG
+ bool "Lemote Fulong mini-PC"
+ select ARCH_SPARSEMEM_ENABLE
+ select SYS_HAS_CPU_LOONGSON2
+ select DMA_NONCOHERENT
+ select BOOT_ELF32
+ select BOARD_SCACHE
+ select HAVE_STD_PC_SERIAL_PORT
+ select HW_HAS_PCI
+ select I8259
+ select ISA
+ select IRQ_CPU
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_HAS_EARLY_PRINTK
+ select GENERIC_HARDIRQS_NO__DO_IRQ
+ select CPU_HAS_WB
+ help
+ Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and
+ an FPGA northbridge
+
config MIPS_ATLAS
bool "MIPS Atlas board"
select BOOT_ELF32
This enables support for the MIPS Technologies SEAD evaluation
board.
-config WR_PPMC
- bool "Wind River PPMC board"
- select IRQ_CPU
- select BOOT_ELF32
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select PCI_GT64XXX_PCI0
- select SWAP_IO_SPACE
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_HAS_CPU_MIPS32_R2
- select SYS_HAS_CPU_MIPS64_R1
- select SYS_HAS_CPU_NEVADA
- select SYS_HAS_CPU_RM7000
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_LITTLE_ENDIAN
- help
- This enables support for the Wind River MIPS32 4KC PPMC evaluation
- board, which is based on GT64120 bridge chip.
-
config MIPS_SIM
bool 'MIPS simulator (MIPSsim)'
select DMA_NONCOHERENT
This option enables support for MIPS Technologies MIPSsim software
emulator.
-config MOMENCO_OCELOT
- bool "Momentum Ocelot board"
+config MARKEINS
+ bool "NEC EMMA2RH Mark-eins"
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
- select IRQ_CPU_RM7K
- select PCI_GT64XXX_PCI0
- select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
- select SYS_HAS_CPU_RM7000
select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_KGDB
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_HAS_CPU_R5000
help
- The Ocelot is a MIPS-based Single Board Computer (SBC) made by
- Momentum Computer <http://www.momenco.com/>.
+ This enables support for the R5432-based NEC Mark-eins
+ boards with R5500 CPU.
+
+config MACH_VR41XX
+ bool "NEC VR4100 series based machines"
+ select SYS_HAS_CPU_VR41XX
+ select GENERIC_HARDIRQS_NO__DO_IRQ
config PNX8550_JBS
bool "Philips PNX8550 based JBS board"
select PNX8550
select SYS_SUPPORTS_LITTLE_ENDIAN
-config DDB5477
- bool "NEC DDB Vrc-5477"
- select DDB5XXX_COMMON
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select I8259
- select IRQ_CPU
- select SYS_HAS_CPU_R5432
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
- select SYS_SUPPORTS_KGDB
- select SYS_SUPPORTS_KGDB
- select SYS_SUPPORTS_LITTLE_ENDIAN
- help
- This enables support for the R5432-based NEC DDB Vrc-5477,
- or Rockhopper/SolutionGear boards with R5432/R5500 CPUs.
-
- Features : kernel debugging, serial terminal, NFS root fs, on-board
- ether port USB, AC97, PCI, etc.
-
-config MACH_VR41XX
- bool "NEC VR4100 series based machines"
- select SYS_HAS_CPU_VR41XX
- select GENERIC_HARDIRQS_NO__DO_IRQ
-
config PMC_MSP
bool "PMC-Sierra MSP chipsets"
depends on EXPERIMENTAL
simulate actual MIPS hardware platforms. More information on Qemu
can be found at http://www.linux-mips.org/wiki/Qemu.
-config MARKEINS
- bool "NEC EMMA2RH Mark-eins"
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select IRQ_CPU
- select SWAP_IO_SPACE
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select SYS_HAS_CPU_R5000
- help
- This enables support for the R5432-based NEC Mark-eins
- boards with R5500 CPU.
-
config SGI_IP22
bool "SGI IP22 (Indy/Indigo2)"
select ARC
help
If you want this kernel to run on SGI O2 workstation, say Y here.
-config SIBYTE_BIGSUR
- bool "Sibyte BCM91480B-BigSur"
+config SIBYTE_CRHINE
+ bool "Sibyte BCM91120C-CRhine"
+ depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
- select NR_CPUS_DEFAULT_4
- select PCI_DOMAINS
- select SIBYTE_BCM1x80
+ select SIBYTE_BCM1120
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_SWARM
- bool "Sibyte BCM91250A-SWARM"
+config SIBYTE_CARMEL
+ bool "Sibyte BCM91120x-Carmel"
+ depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
- select NR_CPUS_DEFAULT_2
- select SIBYTE_SB1250
+ select SIBYTE_BCM1120
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_HIGHMEM
- select SYS_SUPPORTS_KGDB
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_SENTOSA
- bool "Sibyte BCM91250E-Sentosa"
+config SIBYTE_CRHONE
+ bool "Sibyte BCM91125C-CRhone"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
- select NR_CPUS_DEFAULT_2
- select SIBYTE_SB1250
+ select SIBYTE_BCM1125
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_RHONE
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_CARMEL
- bool "Sibyte BCM91120x-Carmel"
- depends on EXPERIMENTAL
+config SIBYTE_SWARM
+ bool "Sibyte BCM91250A-SWARM"
select BOOT_ELF32
select DMA_COHERENT
- select SIBYTE_BCM1120
+ select NR_CPUS_DEFAULT_2
+ select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_KGDB
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_PTSWARM
- bool "Sibyte BCM91250PT-PTSWARM"
+config SIBYTE_LITTLESUR
+ bool "Sibyte BCM91250C2-LittleSur"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_LITTLESUR
- bool "Sibyte BCM91250C2-LittleSur"
+config SIBYTE_SENTOSA
+ bool "Sibyte BCM91250E-Sentosa"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_CRHINE
- bool "Sibyte BCM91120C-CRhine"
+config SIBYTE_PTSWARM
+ bool "Sibyte BCM91250PT-PTSWARM"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
- select SIBYTE_BCM1120
+ select NR_CPUS_DEFAULT_2
+ select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_CRHONE
- bool "Sibyte BCM91125C-CRhone"
- depends on EXPERIMENTAL
+config SIBYTE_BIGSUR
+ bool "Sibyte BCM91480B-BigSur"
select BOOT_ELF32
select DMA_COHERENT
- select SIBYTE_BCM1125
+ select NR_CPUS_DEFAULT_4
+ select PCI_DOMAINS
+ select SIBYTE_BCM1x80
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
config SNI_RM
select GENERIC_HARDIRQS_NO__DO_IRQ
config TOSHIBA_RBTX4927
- bool "Toshiba TBTX49[23]7 board"
+ bool "Toshiba RBTX49[23]7 board"
select DMA_NONCOHERENT
select HAS_TXX9_SERIAL
select HW_HAS_PCI
This Toshiba board is based on the TX4938 processor. Say Y here to
support this machine type
+config WR_PPMC
+ bool "Wind River PPMC board"
+ select IRQ_CPU
+ select BOOT_ELF32
+ select DMA_NONCOHERENT
+ select HW_HAS_PCI
+ select PCI_GT64XXX_PCI0
+ select SWAP_IO_SPACE
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_HAS_CPU_MIPS64_R1
+ select SYS_HAS_CPU_NEVADA
+ select SYS_HAS_CPU_RM7000
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ help
+ This enables support for the Wind River MIPS32 4KC PPMC evaluation
+ board, which is based on GT64120 bridge chip.
+
endchoice
source "arch/mips/au1000/Kconfig"
-source "arch/mips/ddb5xxx/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/pmc-sierra/Kconfig"
source "arch/mips/sgi-ip27/Kconfig"
config IRQ_MSP_CIC
bool
-config DDB5XXX_COMMON
- bool
- select SYS_SUPPORTS_KGDB
-
config MIPS_BOARDS_GEN
bool
This is a kernel model which is known a SMTC or lately has been
marketesed into SMVP.
-config MIPS_VPE_LOADER
- bool "VPE loader support."
- depends on SYS_SUPPORTS_MULTITHREADING
- select CPU_MIPSR2_IRQ_VI
- select CPU_MIPSR2_IRQ_EI
- select CPU_MIPSR2_SRS
- select MIPS_MT
- help
- Includes a loader for loading an elf relocatable object
- onto another VPE and running it.
-
endchoice
config MIPS_MT
config MIPS_MT_FPAFF
bool "Dynamic FPU affinity for FP-intensive threads"
- depends on MIPS_MT
default y
+ depends on MIPS_MT_SMP || MIPS_MT_SMTC
+
+config MIPS_VPE_LOADER
+ bool "VPE loader support."
+ depends on SYS_SUPPORTS_MULTITHREADING
+ select CPU_MIPSR2_IRQ_VI
+ select CPU_MIPSR2_IRQ_EI
+ select CPU_MIPSR2_SRS
+ select MIPS_MT
+ help
+ Includes a loader for loading an elf relocatable object
+ onto another VPE and running it.
config MIPS_MT_SMTC_INSTANT_REPLAY
bool "Low-latency Dispatch of Deferred SMTC IPIs"
config SECCOMP
bool "Enable seccomp to safely compute untrusted bytecode"
- depends on PROC_FS && BROKEN
+ depends on PROC_FS
default y
help
This kernel feature is useful for number crunching applications
endif
endif
+all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32)
+all-$(CONFIG_BOOT_ELF64) := $(vmlinux-64)
#
# GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel
cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-atlas
cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-mips
load-$(CONFIG_MIPS_ATLAS) += 0xffffffff80100000
+all-$(CONFIG_MIPS_ATLAS) := vmlinux.srec
#
# MIPS Malta board
core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/malta/
cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-mips
load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000
+all-$(CONFIG_MIPS_MALTA) := vmlinux.srec
#
# MIPS SEAD board
core-$(CONFIG_MIPS_SEAD) += arch/mips/mips-boards/sead/
cflags-$(CONFIG_MIPS_SEAD) += -Iinclude/asm-mips/mach-mips
load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000
+all-$(CONFIG_MIPS_SEAD) := vmlinux.srec
#
# MIPS SIM
cflags-$(CONFIG_MIPS_SIM) += -Iinclude/asm-mips/mach-mipssim
load-$(CONFIG_MIPS_SIM) += 0x80100000
-#
-# Momentum Ocelot board
-#
-# The Ocelot setup.o must be linked early - it does the ioremap() for the
-# mips_io_port_base.
-#
-core-$(CONFIG_MOMENCO_OCELOT) += arch/mips/gt64120/common/ \
- arch/mips/gt64120/momenco_ocelot/
-cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot
-load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000
-
#
# PMC-Sierra MSP SOCs
#
core-$(CONFIG_QEMU) += arch/mips/qemu/
cflags-$(CONFIG_QEMU) += -Iinclude/asm-mips/mach-qemu
load-$(CONFIG_QEMU) += 0xffffffff80010000
+all-$(CONFIG_QEMU) := vmlinux.bin
#
# Basler eXcite
cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite
load-$(CONFIG_BASLER_EXCITE) += 0x80100000
-#
-# NEC DDB
-#
-core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/
-
-#
-# NEC DDB Vrc-5477
-#
-core-$(CONFIG_DDB5477) += arch/mips/ddb5xxx/ddb5477/
-load-$(CONFIG_DDB5477) += 0xffffffff80100000
-
#
# Common VR41xx
#
core-$(CONFIG_SNI_RM) += arch/mips/sni/
cflags-$(CONFIG_SNI_RM) += -Iinclude/asm-mips/mach-rm
load-$(CONFIG_SNI_RM) += 0xffffffff80600000
+all-$(CONFIG_SNI_RM) := vmlinux.ecoff
#
# Toshiba JMR-TX3927 board
makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
-ifdef CONFIG_BOOT_ELF32
-all: $(vmlinux-32)
-endif
-
-ifdef CONFIG_BOOT_ELF64
-all: $(vmlinux-64)
-endif
-
-ifdef CONFIG_MIPS_ATLAS
-all: vmlinux.srec
-endif
-
-ifdef CONFIG_MIPS_MALTA
-all: vmlinux.srec
-endif
-
-ifdef CONFIG_MIPS_SEAD
-all: vmlinux.srec
-endif
-
-ifdef CONFIG_QEMU
-all: vmlinux.bin
-endif
-
-ifdef CONFIG_SNI_RM
-all: vmlinux.ecoff
-endif
+all: $(all-y)
vmlinux.bin: $(vmlinux-32)
+@$(call makeboot,$@)
archclean:
@$(MAKE) $(clean)=arch/mips/boot
+define archhelp
+ echo ' vmlinux.ecoff - ECOFF boot image'
+ echo ' vmlinux.bin - Raw binary boot image'
+ echo ' vmlinux.srec - SREC boot image'
+ echo
+ echo ' These will be default as apropriate for a configured platform.'
+endef
+
CLEAN_FILES += vmlinux.32 \
vmlinux.64 \
vmlinux.ecoff
#include <asm/arc/types.h>
#include <asm/sgialib.h>
-LONG __init
+LONG
ArcGetDirectoryEntry(ULONG FileID, struct linux_vdirent *Buffer,
ULONG N, ULONG *Count)
{
return ARC_CALL4(get_vdirent, FileID, Buffer, N, Count);
}
-LONG __init
+LONG
ArcOpen(CHAR *Path, enum linux_omode OpenMode, ULONG *FileID)
{
return ARC_CALL3(open, Path, OpenMode, FileID);
}
-LONG __init
+LONG
ArcClose(ULONG FileID)
{
return ARC_CALL1(close, FileID);
}
-LONG __init
+LONG
ArcRead(ULONG FileID, VOID *Buffer, ULONG N, ULONG *Count)
{
return ARC_CALL4(read, FileID, Buffer, N, Count);
}
-LONG __init
+LONG
ArcGetReadStatus(ULONG FileID)
{
return ARC_CALL1(get_rstatus, FileID);
}
-LONG __init
+LONG
ArcWrite(ULONG FileID, PVOID Buffer, ULONG N, PULONG Count)
{
return ARC_CALL4(write, FileID, Buffer, N, Count);
}
-LONG __init
+LONG
ArcSeek(ULONG FileID, struct linux_bigint *Position, enum linux_seekmode SeekMode)
{
return ARC_CALL3(seek, FileID, Position, SeekMode);
}
-LONG __init
+LONG
ArcMount(char *name, enum linux_mountops op)
{
return ARC_CALL2(mount, name, op);
}
-LONG __init
+LONG
ArcGetFileInformation(ULONG FileID, struct linux_finfo *Information)
{
return ARC_CALL2(get_finfo, FileID, Information);
}
-LONG __init ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags,
- ULONG AttributeMask)
+LONG ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags,
+ ULONG AttributeMask)
{
return ARC_CALL3(set_finfo, FileID, AttributeFlags, AttributeMask);
}
obj-$(CONFIG_KGDB) += dbg_io.o
obj-$(CONFIG_PCI) += pci.o
+
+EXTRA_CFLAGS += -Werror
$(obj)/addinitrd: $(obj)/addinitrd.c
$(HOSTCC) -o $@ $^
-archhelp:
- @echo '* vmlinux.ecoff - ECOFF boot image'
- @echo '* vmlinux.srec - SREC boot image'
-
clean-files += addinitrd \
elf2ecoff \
vmlinux.bin \
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_EARLY_PRINTK) += console.o
obj-$(CONFIG_MTD_PHYSMAP) += mtd.o
+
+EXTRA_CFLAGS += -Werror
int retval;
/*
- * Cobalt Qube1 and RAQ1 have no UART.
+ * Cobalt Qube1 has no UART.
*/
- if (cobalt_board_id <= COBALT_BRD_ID_RAQ1)
+ if (cobalt_board_id == COBALT_BRD_ID_QUBE1)
return 0;
pdev = platform_device_alloc("serial8250", -1);
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
+++ /dev/null
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:28 2007
-#
-CONFIG_MIPS=y
-
-#
-# Machine selection
-#
-CONFIG_ZONE_DMA=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
-# CONFIG_MIPS_COBALT is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_WR_PPMC is not set
-# CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
-# CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-CONFIG_DDB5477=y
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_QEMU is not set
-# CONFIG_MARKEINS is not set
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_PTSWARM is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_DDB5477_BUS_FREQUENCY=0
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_I8259=y
-# CONFIG_CPU_BIG_ENDIAN is not set
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_IRQ_CPU=y
-CONFIG_DDB5XXX_COMMON=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-
-#
-# CPU selection
-#
-# CONFIG_CPU_MIPS32_R1 is not set
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_VR41XX is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_R5000 is not set
-CONFIG_CPU_R5432=y
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_SYS_HAS_CPU_R5432=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-
-#
-# Kernel type
-#
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_8KB is not set
-# CONFIG_PAGE_SIZE_16KB is not set
-# CONFIG_PAGE_SIZE_64KB is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-# CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_128 is not set
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
-# CONFIG_HZ_1024 is not set
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-# CONFIG_KEXEC is not set
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_RELAY=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-# CONFIG_MODULES is not set
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Bus options (PCI, PCMCIA, EISA, ISA, TC)
-#
-CONFIG_HW_HAS_PCI=y
-CONFIG_PCI=y
-CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# PCI Hotplug Support
-#
-# CONFIG_HOTPLUG_PCI is not set
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
-CONFIG_TRAD_SIGNALS=y
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
-# CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=y
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-CONFIG_IEEE80211=y
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=y
-CONFIG_IEEE80211_CRYPT_CCMP=y
-CONFIG_IEEE80211_SOFTMAC=y
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
-CONFIG_WIRELESS_EXT=y
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=y
-CONFIG_PROC_EVENTS=y
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CDROM_PKTCDVD=y
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=y
-
-#
-# Misc devices
-#
-CONFIG_SGI_IOC4=y
-# CONFIG_TIFM_CORE is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_RAID_ATTRS=y
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_IEEE1394 is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_QSEMI_PHY=y
-CONFIG_LXT_PHY=y
-CONFIG_CICADA_PHY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_SMSC_PHY=y
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_FIXED_PHY is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_DM9000 is not set
-
-#
-# Tulip family network device support
-#
-# CONFIG_NET_TULIP is not set
-# CONFIG_HP100 is not set
-CONFIG_NET_PCI=y
-CONFIG_PCNET32=y
-# CONFIG_PCNET32_NAPI is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-# CONFIG_DGRS is not set
-# CONFIG_EEPRO100 is not set
-# CONFIG_E100 is not set
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_TLAN is not set
-# CONFIG_VIA_RHINE is not set
-# CONFIG_SC92031 is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-# CONFIG_E1000 is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_VIA_VELOCITY is not set
-# CONFIG_TIGON3 is not set
-# CONFIG_BNX2 is not set
-CONFIG_QLA3XXX=y
-# CONFIG_ATL1 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-CONFIG_CHELSIO_T3=y
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-CONFIG_NETXEN_NIC=y
-
-#
-# Token Ring devices
-#
-# CONFIG_TR is not set
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_PCIPS2 is not set
-# CONFIG_SERIO_LIBPS2 is not set
-CONFIG_SERIO_RAW=y
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SERIAL_8250_EXTENDED is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# HID Devices
-#
-# CONFIG_HID is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-# CONFIG_USB is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
-# CONFIG_INFINIBAND is not set
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
-# CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Auxiliary Display support
-#
-
-#
-# Virtualization
-#
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_FUSE_FS=y
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=y
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=y
-# CONFIG_NFSD_V3 is not set
-# CONFIG_NFSD_TCP is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=y
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE="ip=any"
-CONFIG_SYS_SUPPORTS_KGDB=y
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_WP512=y
-CONFIG_CRYPTO_TGR192=y
-CONFIG_CRYPTO_GF128MUL=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_PCBC=y
-CONFIG_CRYPTO_LRW=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_FCRYPT=y
-CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_TWOFISH_COMMON=y
-CONFIG_CRYPTO_SERPENT=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_CAST5=y
-CONFIG_CRYPTO_CAST6=y
-CONFIG_CRYPTO_TEA=y
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_KHAZAD=y
-CONFIG_CRYPTO_ANUBIS=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CAMELLIA=y
-
-#
-# Hardware crypto devices
-#
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-CONFIG_CRC16=y
-CONFIG_CRC32=y
-CONFIG_LIBCRC32C=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
CONFIG_MIPS_SIM=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
CONFIG_PMC_MSP=y
# CONFIG_PMC_YOSEMITE is not set
+++ /dev/null
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:36 2007
-#
-CONFIG_MIPS=y
-
-#
-# Machine selection
-#
-CONFIG_ZONE_DMA=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
-# CONFIG_MIPS_COBALT is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_WR_PPMC is not set
-# CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-CONFIG_MOMENCO_OCELOT=y
-# CONFIG_MOMENCO_OCELOT_G is not set
-# CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_QEMU is not set
-# CONFIG_MARKEINS is not set
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_PTSWARM is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_CPU_BIG_ENDIAN=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_CPU_RM7K=y
-CONFIG_MIPS_GT64120=y
-CONFIG_SWAP_IO_SPACE=y
-# CONFIG_SYSCLK_75 is not set
-# CONFIG_SYSCLK_83 is not set
-CONFIG_SYSCLK_100=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-
-#
-# CPU selection
-#
-# CONFIG_CPU_MIPS32_R1 is not set
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_VR41XX is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_R10000 is not set
-CONFIG_CPU_RM7000=y
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_SYS_HAS_CPU_RM7000=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-
-#
-# Kernel type
-#
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_8KB is not set
-# CONFIG_PAGE_SIZE_16KB is not set
-# CONFIG_PAGE_SIZE_64KB is not set
-CONFIG_BOARD_SCACHE=y
-CONFIG_RM7000_CPU_SCACHE=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
-# CONFIG_64BIT_PHYS_ADDR is not set
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-# CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_128 is not set
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
-# CONFIG_HZ_1024 is not set
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-# CONFIG_KEXEC is not set
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_RELAY=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_HOTPLUG is not set
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-# CONFIG_MODULES is not set
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Bus options (PCI, PCMCIA, EISA, ISA, TC)
-#
-CONFIG_HW_HAS_PCI=y
-# CONFIG_PCI is not set
-CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-
-#
-# PCI Hotplug Support
-#
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
-CONFIG_TRAD_SIGNALS=y
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
-# CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-# CONFIG_PACKET is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=y
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-CONFIG_IEEE80211=y
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=y
-CONFIG_IEEE80211_CRYPT_CCMP=y
-CONFIG_IEEE80211_SOFTMAC=y
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
-CONFIG_WIRELESS_EXT=y
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=y
-CONFIG_PROC_EVENTS=y
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CDROM_PKTCDVD=y
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=y
-
-#
-# Misc devices
-#
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_RAID_ATTRS=y
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# PHY device support
-#
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_QSEMI_PHY=y
-CONFIG_LXT_PHY=y
-CONFIG_CICADA_PHY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_SMSC_PHY=y
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_FIXED_PHY is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-# CONFIG_MII is not set
-# CONFIG_DM9000 is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_LIBPS2 is not set
-CONFIG_SERIO_RAW=y
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SERIAL_8250_EXTENDED is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# HID Devices
-#
-# CONFIG_HID is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
-# CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Auxiliary Display support
-#
-
-#
-# Virtualization
-#
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-CONFIG_FUSE_FS=y
-CONFIG_GENERIC_ACL=y
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=y
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=y
-# CONFIG_NFSD_V3 is not set
-# CONFIG_NFSD_TCP is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=y
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_WP512=y
-CONFIG_CRYPTO_TGR192=y
-CONFIG_CRYPTO_GF128MUL=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_PCBC=y
-CONFIG_CRYPTO_LRW=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_FCRYPT=y
-CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_TWOFISH_COMMON=y
-CONFIG_CRYPTO_SERPENT=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_CAST5=y
-CONFIG_CRYPTO_CAST6=y
-CONFIG_CRYPTO_TEA=y
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_KHAZAD=y
-CONFIG_CRYPTO_ANUBIS=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CAMELLIA=y
-
-#
-# Hardware crypto devices
-#
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-CONFIG_CRC16=y
-CONFIG_CRC32=y
-CONFIG_LIBCRC32C=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
CONFIG_PNX8550_JBS=y
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
CONFIG_PNX8550_STB810=y
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
CONFIG_QEMU=y
# CONFIG_MIPS_SEAD is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
CONFIG_WR_PPMC=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
CONFIG_PMC_YOSEMITE=y
# CONFIG_QEMU is not set
+++ /dev/null
-config DDB5477_BUS_FREQUENCY
- int "bus frequency (in kHZ, 0 for auto-detect)"
- depends on DDB5477
- default 0
+++ /dev/null
-#
-# Makefile for the common code of NEC DDB-Vrc5xxx board
-#
-
-obj-y += nile4.o prom.o rtc_ds1386.o
+++ /dev/null
-/*
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * arch/mips/ddb5xxx/common/nile4.c
- * misc low-level routines for vrc-5xxx controllers.
- *
- * derived from original code by Geert Uytterhoeven <geert@sonycom.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-u32
-ddb_calc_pdar(u32 phys, u32 size, int width,
- int on_memory_bus, int pci_visible)
-{
- u32 maskbits;
- u32 widthbits;
-
- switch (size) {
-#if 0 /* We don't support 4 GB yet */
- case 0x100000000: /* 4 GB */
- maskbits = 4;
- break;
-#endif
- case 0x80000000: /* 2 GB */
- maskbits = 5;
- break;
- case 0x40000000: /* 1 GB */
- maskbits = 6;
- break;
- case 0x20000000: /* 512 MB */
- maskbits = 7;
- break;
- case 0x10000000: /* 256 MB */
- maskbits = 8;
- break;
- case 0x08000000: /* 128 MB */
- maskbits = 9;
- break;
- case 0x04000000: /* 64 MB */
- maskbits = 10;
- break;
- case 0x02000000: /* 32 MB */
- maskbits = 11;
- break;
- case 0x01000000: /* 16 MB */
- maskbits = 12;
- break;
- case 0x00800000: /* 8 MB */
- maskbits = 13;
- break;
- case 0x00400000: /* 4 MB */
- maskbits = 14;
- break;
- case 0x00200000: /* 2 MB */
- maskbits = 15;
- break;
- case 0: /* OFF */
- maskbits = 0;
- break;
- default:
- panic("nile4_set_pdar: unsupported size %p", (void *) size);
- }
- switch (width) {
- case 8:
- widthbits = 0;
- break;
- case 16:
- widthbits = 1;
- break;
- case 32:
- widthbits = 2;
- break;
- case 64:
- widthbits = 3;
- break;
- default:
- panic("nile4_set_pdar: unsupported width %d", width);
- }
-
- return maskbits | (on_memory_bus ? 0x10 : 0) |
- (pci_visible ? 0x20 : 0) | (widthbits << 6) |
- (phys & 0xffe00000);
-}
-
-void
-ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
- int on_memory_bus, int pci_visible)
-{
- u32 temp= ddb_calc_pdar(phys, size, width, on_memory_bus, pci_visible);
- ddb_out32(pdar, temp);
- ddb_out32(pdar + 4, 0);
-
- /*
- * When programming a PDAR, the register should be read immediately
- * after writing it. This ensures that address decoders are properly
- * configured.
- * [jsun] is this really necessary?
- */
- ddb_in32(pdar);
- ddb_in32(pdar + 4);
-}
-
-/*
- * routines that mess with PCIINITx registers
- */
-
-void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options)
-{
- switch (type) {
- case DDB_PCICMD_IACK: /* PCI Interrupt Acknowledge */
- case DDB_PCICMD_IO: /* PCI I/O Space */
- case DDB_PCICMD_MEM: /* PCI Memory Space */
- case DDB_PCICMD_CFG: /* PCI Configuration Space */
- break;
- default:
- panic("nile4_set_pmr: invalid type %d", type);
- }
- ddb_out32(pmr, (type << 1) | (addr & 0xffe00000) | options );
- ddb_out32(pmr + 4, 0);
-}
+++ /dev/null
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/bootmem.h>
-
-#include <asm/addrspace.h>
-#include <asm/bootinfo.h>
-#include <asm/ddb5xxx/ddb5xxx.h>
-#include <asm/debug.h>
-
-const char *get_system_type(void)
-{
- switch (mips_machtype) {
- case MACH_NEC_DDB5477: return "NEC DDB Vrc-5477";
- case MACH_NEC_ROCKHOPPER: return "NEC Rockhopper";
- case MACH_NEC_ROCKHOPPERII: return "NEC RockhopperII";
- default: return "Unknown NEC board";
- }
-}
-
-#if defined(CONFIG_DDB5477)
-void ddb5477_runtime_detection(void);
-#endif
-
-/* [jsun@junsun.net] PMON passes arguments in C main() style */
-void __init prom_init(void)
-{
- int argc = fw_arg0;
- char **arg = (char**) fw_arg1;
- int i;
-
- /* if user passes kernel args, ignore the default one */
- if (argc > 1)
- arcs_cmdline[0] = '\0';
-
- /* arg[0] is "g", the rest is boot parameters */
- for (i = 1; i < argc; i++) {
- if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
- >= sizeof(arcs_cmdline))
- break;
- strcat(arcs_cmdline, arg[i]);
- strcat(arcs_cmdline, " ");
- }
-
- mips_machgroup = MACH_GROUP_NEC_DDB;
-
-#if defined(CONFIG_DDB5477)
- ddb5477_runtime_detection();
- add_memory_region(0, board_ram_size, BOOT_MEM_RAM);
-#endif
-}
-
-void __init prom_free_prom_memory(void)
-{
-}
-
-#if defined(CONFIG_DDB5477)
-
-#define DEFAULT_LCS1_BASE 0x19000000
-#define TESTVAL1 'K'
-#define TESTVAL2 'S'
-
-int board_ram_size;
-void ddb5477_runtime_detection(void)
-{
- volatile char *test_offset;
- char saved_test_byte;
-
- /* Determine if this is a DDB5477 board, or a BSB-VR0300
- base board. We can tell by checking for the location of
- the NVRAM. It lives at the beginning of LCS1 on the DDB5477,
- and the beginning of LCS1 on the BSB-VR0300 is flash memory.
- The first 2K of the NVRAM are reserved, so don't we'll poke
- around just after that.
- */
-
- /* We can only use the PCI bus to distinquish between
- the Rockhopper and RockhopperII backplanes and this must
- wait until ddb5477_board_init() in setup.c after the 5477
- is initialized. So, until then handle
- both Rockhopper and RockhopperII backplanes as Rockhopper 1
- */
-
- test_offset = (char *)KSEG1ADDR(DEFAULT_LCS1_BASE + 0x800);
- saved_test_byte = *test_offset;
-
- *test_offset = TESTVAL1;
- if (*test_offset != TESTVAL1) {
- /* We couldn't set our test value, so it must not be NVRAM,
- so it's a BSB_VR0300 */
- mips_machtype = MACH_NEC_ROCKHOPPER;
- } else {
- /* We may have gotten lucky, and the TESTVAL1 was already
- stored at the test location, so we must check a second
- test value */
- *test_offset = TESTVAL2;
- if (*test_offset != TESTVAL2) {
- /* OK, we couldn't set this value either, so it must
- definately be a BSB_VR0300 */
- mips_machtype = MACH_NEC_ROCKHOPPER;
- } else {
- /* We could change the value twice, so it must be
- NVRAM, so it's a DDB_VRC5477 */
- mips_machtype = MACH_NEC_DDB5477;
- }
- }
- /* Restore the original byte */
- *test_offset = saved_test_byte;
-
- /* before we know a better way, we will trust PMON for getting
- * RAM size
- */
- board_ram_size = 1 << (36 - (ddb_in32(DDB_SDRAM0) & 0xf));
-
- db_run(printk("DDB run-time detection : %s, %d MB RAM\n",
- mips_machtype == MACH_NEC_DDB5477 ?
- "DDB5477" : "Rockhopper",
- board_ram_size >> 20));
-
- /* we can't handle ram size > 128 MB */
- db_assert(board_ram_size <= (128 << 20));
-}
-#endif
+++ /dev/null
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * arch/mips/ddb5xxx/common/rtc_ds1386.c
- * low-level RTC hookups for s for Dallas 1396 chip.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-
-/*
- * This file exports a function, rtc_ds1386_init(), which expects an
- * uncached base address as the argument. It will set the two function
- * pointers expected by the MIPS generic timer code.
- */
-
-#include <linux/types.h>
-#include <linux/time.h>
-#include <linux/bcd.h>
-
-#include <asm/time.h>
-#include <asm/addrspace.h>
-
-#include <asm/mc146818rtc.h>
-#include <asm/debug.h>
-
-#define EPOCH 2000
-
-#define READ_RTC(x) *(volatile unsigned char*)(rtc_base+x)
-#define WRITE_RTC(x, y) *(volatile unsigned char*)(rtc_base+x) = y
-
-static unsigned long rtc_base;
-
-static unsigned long
-rtc_ds1386_get_time(void)
-{
- u8 byte;
- u8 temp;
- unsigned int year, month, day, hour, minute, second;
- unsigned long flags;
-
- spin_lock_irqsave(&rtc_lock, flags);
- /* let us freeze external registers */
- byte = READ_RTC(0xB);
- byte &= 0x3f;
- WRITE_RTC(0xB, byte);
-
- /* read time data */
- year = BCD2BIN(READ_RTC(0xA)) + EPOCH;
- month = BCD2BIN(READ_RTC(0x9) & 0x1f);
- day = BCD2BIN(READ_RTC(0x8));
- minute = BCD2BIN(READ_RTC(0x2));
- second = BCD2BIN(READ_RTC(0x1));
-
- /* hour is special - deal with it later */
- temp = READ_RTC(0x4);
-
- /* enable time transfer */
- byte |= 0x80;
- WRITE_RTC(0xB, byte);
- spin_unlock_irqrestore(&rtc_lock, flags);
-
- /* calc hour */
- if (temp & 0x40) {
- /* 12 hour format */
- hour = BCD2BIN(temp & 0x1f);
- if (temp & 0x20) hour += 12; /* PM */
- } else {
- /* 24 hour format */
- hour = BCD2BIN(temp & 0x3f);
- }
-
- return mktime(year, month, day, hour, minute, second);
-}
-
-static int
-rtc_ds1386_set_time(unsigned long t)
-{
- struct rtc_time tm;
- u8 byte;
- u8 temp;
- u8 year, month, day, hour, minute, second;
- unsigned long flags;
-
- spin_lock_irqsave(&rtc_lock, flags);
- /* let us freeze external registers */
- byte = READ_RTC(0xB);
- byte &= 0x3f;
- WRITE_RTC(0xB, byte);
-
- /* convert */
- to_tm(t, &tm);
-
-
- /* check each field one by one */
- year = BIN2BCD(tm.tm_year - EPOCH);
- if (year != READ_RTC(0xA)) {
- WRITE_RTC(0xA, year);
- }
-
- temp = READ_RTC(0x9);
- month = BIN2BCD(tm.tm_mon+1); /* tm_mon starts from 0 to 11 */
- if (month != (temp & 0x1f)) {
- WRITE_RTC( 0x9,
- (month & 0x1f) | (temp & ~0x1f) );
- }
-
- day = BIN2BCD(tm.tm_mday);
- if (day != READ_RTC(0x8)) {
- WRITE_RTC(0x8, day);
- }
-
- temp = READ_RTC(0x4);
- if (temp & 0x40) {
- /* 12 hour format */
- hour = 0x40;
- if (tm.tm_hour > 12) {
- hour |= 0x20 | (BIN2BCD(hour-12) & 0x1f);
- } else {
- hour |= BIN2BCD(tm.tm_hour);
- }
- } else {
- /* 24 hour format */
- hour = BIN2BCD(tm.tm_hour) & 0x3f;
- }
- if (hour != temp) WRITE_RTC(0x4, hour);
-
- minute = BIN2BCD(tm.tm_min);
- if (minute != READ_RTC(0x2)) {
- WRITE_RTC(0x2, minute);
- }
-
- second = BIN2BCD(tm.tm_sec);
- if (second != READ_RTC(0x1)) {
- WRITE_RTC(0x1, second);
- }
- spin_unlock_irqrestore(&rtc_lock, flags);
-
- return 0;
-}
-
-void
-rtc_ds1386_init(unsigned long base)
-{
- unsigned char byte;
-
- /* remember the base */
- rtc_base = base;
- db_assert((rtc_base & 0xe0000000) == KSEG1);
-
- /* turn on RTC if it is not on */
- byte = READ_RTC(0x9);
- if (byte & 0x80) {
- byte &= 0x7f;
- WRITE_RTC(0x9, byte);
- }
-
- /* enable time transfer */
- byte = READ_RTC(0xB);
- byte |= 0x80;
- WRITE_RTC(0xB, byte);
-
- /* set the function pointers */
- rtc_mips_get_time = rtc_ds1386_get_time;
- rtc_mips_set_time = rtc_ds1386_set_time;
-}
+++ /dev/null
-#
-# Makefile for NEC DDB-Vrc5477 board
-#
-
-obj-y += ddb5477-platform.o irq.o irq_5477.o setup.o \
- lcd44780.o
-
-obj-$(CONFIG_RUNTIME_DEBUG) += debug.o
-obj-$(CONFIG_KGDB) += kgdb_io.o
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/serial_8250.h>
-
-#include <asm/ddb5xxx/ddb5477.h>
-
-#define DDB_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
-
-#define DDB5477_PORT(base, int) \
-{ \
- .mapbase = base, \
- .irq = int, \
- .uartclk = 1843200, \
- .iotype = UPIO_MEM, \
- .flags = DDB_UART_FLAGS, \
- .regshift = 3, \
-}
-
-static struct plat_serial8250_port uart8250_data[] = {
- DDB5477_PORT(0xbfa04200, VRC5477_IRQ_UART0),
- DDB5477_PORT(0xbfa04240, VRC5477_IRQ_UART1),
- { },
-};
-
-static struct platform_device uart8250_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = uart8250_data,
- },
-};
-
-static int __init uart8250_init(void)
-{
- return platform_device_register(&uart8250_device);
-}
-
-module_init(uart8250_init);
-
-MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("8250 UART probe driver for the NEC DDB5477");
+++ /dev/null
-/***********************************************************************
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * arch/mips/ddb5xxx/ddb5477/debug.c
- * vrc5477 specific debug routines.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- ***********************************************************************
- */
-
-#include <linux/kernel.h>
-
-#include <asm/mipsregs.h>
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-typedef struct {
- const char *regname;
- unsigned regaddr;
-} Register;
-
-void jsun_show_regs(char *name, Register *regs)
-{
- int i;
-
- printk("\nshow regs: %s\n", name);
- for(i=0;regs[i].regname!= NULL; i++) {
- printk("%-16s= %08x\t\t(@%08x)\n",
- regs[i].regname,
- *(unsigned *)(regs[i].regaddr),
- regs[i].regaddr);
- }
-}
-
-static Register int_regs[] = {
- {"DDB_INTCTRL0", DDB_BASE + DDB_INTCTRL0},
- {"DDB_INTCTRL1", DDB_BASE + DDB_INTCTRL1},
- {"DDB_INTCTRL2", DDB_BASE + DDB_INTCTRL2},
- {"DDB_INTCTRL3", DDB_BASE + DDB_INTCTRL3},
- {"DDB_INT0STAT", DDB_BASE + DDB_INT0STAT},
- {"DDB_INT1STAT", DDB_BASE + DDB_INT1STAT},
- {"DDB_INT2STAT", DDB_BASE + DDB_INT2STAT},
- {"DDB_INT3STAT", DDB_BASE + DDB_INT3STAT},
- {"DDB_INT4STAT", DDB_BASE + DDB_INT4STAT},
- {"DDB_NMISTAT", DDB_BASE + DDB_NMISTAT},
- {"DDB_INTPPES0", DDB_BASE + DDB_INTPPES0},
- {"DDB_INTPPES1", DDB_BASE + DDB_INTPPES1},
- {NULL, 0x0}
-};
-
-void vrc5477_show_int_regs()
-{
- jsun_show_regs("interrupt registers", int_regs);
- printk("CPU CAUSE = %08x\n", read_c0_cause());
- printk("CPU STATUS = %08x\n", read_c0_status());
-}
-static Register pdar_regs[] = {
- {"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0},
- {"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1},
- {"DDB_LCS0", DDB_BASE + DDB_LCS0},
- {"DDB_LCS1", DDB_BASE + DDB_LCS1},
- {"DDB_LCS2", DDB_BASE + DDB_LCS2},
- {"DDB_INTCS", DDB_BASE + DDB_INTCS},
- {"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS},
- {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
- {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
- {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
- {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
- {NULL, 0x0}
-};
-void vrc5477_show_pdar_regs(void)
-{
- jsun_show_regs("PDAR regs", pdar_regs);
-}
-
-static Register bar_regs[] = {
- {"DDB_BARC0", DDB_BASE + DDB_BARC0},
- {"DDB_BARM010", DDB_BASE + DDB_BARM010},
- {"DDB_BARM230", DDB_BASE + DDB_BARM230},
- {"DDB_BAR00", DDB_BASE + DDB_BAR00},
- {"DDB_BAR10", DDB_BASE + DDB_BAR10},
- {"DDB_BAR20", DDB_BASE + DDB_BAR20},
- {"DDB_BAR30", DDB_BASE + DDB_BAR30},
- {"DDB_BAR40", DDB_BASE + DDB_BAR40},
- {"DDB_BAR50", DDB_BASE + DDB_BAR50},
- {"DDB_BARB0", DDB_BASE + DDB_BARB0},
- {"DDB_BARC1", DDB_BASE + DDB_BARC1},
- {"DDB_BARM011", DDB_BASE + DDB_BARM011},
- {"DDB_BARM231", DDB_BASE + DDB_BARM231},
- {"DDB_BAR01", DDB_BASE + DDB_BAR01},
- {"DDB_BAR11", DDB_BASE + DDB_BAR11},
- {"DDB_BAR21", DDB_BASE + DDB_BAR21},
- {"DDB_BAR31", DDB_BASE + DDB_BAR31},
- {"DDB_BAR41", DDB_BASE + DDB_BAR41},
- {"DDB_BAR51", DDB_BASE + DDB_BAR51},
- {"DDB_BARB1", DDB_BASE + DDB_BARB1},
- {NULL, 0x0}
-};
-void vrc5477_show_bar_regs(void)
-{
- jsun_show_regs("BAR regs", bar_regs);
-}
-
-static Register pci_regs[] = {
- {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
- {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
- {"DDB_PCIINIT00", DDB_BASE + DDB_PCIINIT00},
- {"DDB_PCIINIT10", DDB_BASE + DDB_PCIINIT10},
- {"DDB_PCICTL0_L", DDB_BASE + DDB_PCICTL0_L},
- {"DDB_PCICTL0_H", DDB_BASE + DDB_PCICTL0_H},
- {"DDB_PCIARB0_L", DDB_BASE + DDB_PCIARB0_L},
- {"DDB_PCIARB0_H", DDB_BASE + DDB_PCIARB0_H},
- {"DDB_PCISWP0", DDB_BASE + DDB_PCISWP0},
- {"DDB_PCIERR0", DDB_BASE + DDB_PCIERR0},
- {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
- {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
- {"DDB_PCIINIT01", DDB_BASE + DDB_PCIINIT01},
- {"DDB_PCIINIT11", DDB_BASE + DDB_PCIINIT11},
- {"DDB_PCICTL1_L", DDB_BASE + DDB_PCICTL1_L},
- {"DDB_PCICTL1_H", DDB_BASE + DDB_PCICTL1_H},
- {"DDB_PCIARB1_L", DDB_BASE + DDB_PCIARB1_L},
- {"DDB_PCIARB1_H", DDB_BASE + DDB_PCIARB1_H},
- {"DDB_PCISWP1", DDB_BASE + DDB_PCISWP1},
- {"DDB_PCIERR1", DDB_BASE + DDB_PCIERR1},
- {NULL, 0x0}
-};
-void vrc5477_show_pci_regs(void)
-{
- jsun_show_regs("PCI regs", pci_regs);
-}
-
-static Register lb_regs[] = {
- {"DDB_LCNFG", DDB_BASE + DDB_LCNFG},
- {"DDB_LCST0", DDB_BASE + DDB_LCST0},
- {"DDB_LCST1", DDB_BASE + DDB_LCST1},
- {"DDB_LCST2", DDB_BASE + DDB_LCST2},
- {"DDB_ERRADR", DDB_BASE + DDB_ERRADR},
- {"DDB_ERRCS", DDB_BASE + DDB_ERRCS},
- {"DDB_BTM", DDB_BASE + DDB_BTM},
- {"DDB_BCST", DDB_BASE + DDB_BCST},
- {NULL, 0x0}
-};
-void vrc5477_show_lb_regs(void)
-{
- jsun_show_regs("Local Bus regs", lb_regs);
-}
-
-void vrc5477_show_all_regs(void)
-{
- vrc5477_show_pdar_regs();
- vrc5477_show_pci_regs();
- vrc5477_show_bar_regs();
- vrc5477_show_int_regs();
- vrc5477_show_lb_regs();
-}
+++ /dev/null
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * arch/mips/ddb5xxx/ddb5477/irq.c
- * The irq setup and misc routines for DDB5476.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-
-#include <asm/i8259.h>
-#include <asm/irq_cpu.h>
-#include <asm/system.h>
-#include <asm/mipsregs.h>
-#include <asm/debug.h>
-#include <asm/addrspace.h>
-#include <asm/bootinfo.h>
-
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-
-/*
- * IRQ mapping
- *
- * 0-7: 8 CPU interrupts
- * 0 - software interrupt 0
- * 1 - software interrupt 1
- * 2 - most Vrc5477 interrupts are routed to this pin
- * 3 - (optional) some other interrupts routed to this pin for debugg
- * 4 - not used
- * 5 - not used
- * 6 - not used
- * 7 - cpu timer (used by default)
- *
- * 8-39: 32 Vrc5477 interrupt sources
- * (refer to the Vrc5477 manual)
- */
-
-#define PCI0 DDB_INTPPES0
-#define PCI1 DDB_INTPPES1
-
-#define ACTIVE_LOW 1
-#define ACTIVE_HIGH 0
-
-#define LEVEL_SENSE 2
-#define EDGE_TRIGGER 0
-
-#define INTA 0
-#define INTB 1
-#define INTC 2
-#define INTD 3
-#define INTE 4
-
-static inline void
-set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
-{
- u32 reg_value;
- u32 reg_bitmask;
-
- reg_value = ddb_in32(pci);
- reg_bitmask = 0x3 << (intn * 2);
-
- reg_value &= ~reg_bitmask;
- reg_value |= (active | trigger) << (intn * 2);
- ddb_out32(pci, reg_value);
-}
-
-extern void vrc5477_irq_init(u32 base);
-static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
-
-void __init arch_init_irq(void)
-{
- /* by default, we disable all interrupts and route all vrc5477
- * interrupts to pin 0 (irq 2) */
- ddb_out32(DDB_INTCTRL0, 0);
- ddb_out32(DDB_INTCTRL1, 0);
- ddb_out32(DDB_INTCTRL2, 0);
- ddb_out32(DDB_INTCTRL3, 0);
-
- clear_c0_status(0xff00);
- set_c0_status(0x0400);
-
- /* setup PCI interrupt attributes */
- set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
- set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
- if (mips_machtype == MACH_NEC_ROCKHOPPERII)
- set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
- else
- set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
- set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
- set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
-
- set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
- set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
- set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
- set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
- set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
-
- /*
- * for debugging purpose, we enable several error interrupts
- * and route them to pin 1. (IP3)
- */
- /* cpu parity check - 0 */
- ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
- /* cpu no-target decode - 1 */
- ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
- /* local bus read time-out - 7 */
- ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
- /* PCI SERR# - 14 */
- ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
- /* PCI internal error - 15 */
- ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
- /* IOPCI SERR# - 30 */
- ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
- /* IOPCI internal error - 31 */
- ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
-
- /* init all controllers */
- init_i8259_irqs();
- mips_cpu_irq_init();
- vrc5477_irq_init(VRC5477_IRQ_BASE);
-
-
- /* setup cascade interrupts */
- setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
- setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
-}
-
-u8 i8259_interrupt_ack(void)
-{
- u8 irq;
- u32 reg;
-
- /* Set window 0 for interrupt acknowledge */
- reg = ddb_in32(DDB_PCIINIT10);
-
- ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
- irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
- ddb_out32(DDB_PCIINIT10, reg);
-
- return irq;
-}
-/*
- * the first level int-handler will jump here if it is a vrc5477 irq
- */
-#define NUM_5477_IRQS 32
-static void vrc5477_irq_dispatch(void)
-{
- u32 intStatus;
- u32 bitmask;
- u32 i;
-
- db_assert(ddb_in32(DDB_INT2STAT) == 0);
- db_assert(ddb_in32(DDB_INT3STAT) == 0);
- db_assert(ddb_in32(DDB_INT4STAT) == 0);
- db_assert(ddb_in32(DDB_NMISTAT) == 0);
-
- if (ddb_in32(DDB_INT1STAT) != 0) {
-#if defined(CONFIG_RUNTIME_DEBUG)
- vrc5477_show_int_regs();
-#endif
- panic("error interrupt has happened.");
- }
-
- intStatus = ddb_in32(DDB_INT0STAT);
-
- if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
- /* check for i8259 interrupts */
- if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
- int i8259_irq = i8259_interrupt_ack();
- do_IRQ(i8259_irq);
- return;
- }
- }
-
- for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
- /* do we need to "and" with the int mask? */
- if (intStatus & bitmask) {
- do_IRQ(VRC5477_IRQ_BASE + i);
- return;
- }
- }
-}
-
-#define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6)
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
-
- if (pending & STATUSF_IP7)
- do_IRQ(CPU_IRQ_BASE + 7);
- else if (pending & VR5477INTS)
- vrc5477_irq_dispatch();
- else if (pending & STATUSF_IP0)
- do_IRQ(CPU_IRQ_BASE);
- else if (pending & STATUSF_IP1)
- do_IRQ(CPU_IRQ_BASE + 1);
- else
- spurious_interrupt();
-}
+++ /dev/null
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * arch/mips/ddb5xxx/ddb5477/irq_5477.c
- * This file defines the irq handler for Vrc5477.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-/*
- * Vrc5477 defines 32 IRQs.
- *
- * This file exports one function:
- * vrc5477_irq_init(u32 irq_base);
- */
-
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-
-#include <asm/debug.h>
-
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-/* number of total irqs supported by Vrc5477 */
-#define NUM_5477_IRQ 32
-
-static int vrc5477_irq_base = -1;
-
-
-static void
-vrc5477_irq_enable(unsigned int irq)
-{
- db_assert(vrc5477_irq_base != -1);
- db_assert(irq >= vrc5477_irq_base);
- db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
-
- ll_vrc5477_irq_enable(irq - vrc5477_irq_base);
-}
-
-static void
-vrc5477_irq_disable(unsigned int irq)
-{
- db_assert(vrc5477_irq_base != -1);
- db_assert(irq >= vrc5477_irq_base);
- db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
-
- ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
-}
-
-static void
-vrc5477_irq_ack(unsigned int irq)
-{
- db_assert(vrc5477_irq_base != -1);
- db_assert(irq >= vrc5477_irq_base);
- db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
-
- /* clear the interrupt bit */
- /* some irqs require the driver to clear the sources */
- ddb_out32(DDB_INTCLR32, 1 << (irq - vrc5477_irq_base));
-
- /* disable interrupt - some handler will re-enable the irq
- * and if the interrupt is leveled, we will have infinite loop
- */
- ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
-}
-
-static void
-vrc5477_irq_end(unsigned int irq)
-{
- db_assert(vrc5477_irq_base != -1);
- db_assert(irq >= vrc5477_irq_base);
- db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
-
- if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- ll_vrc5477_irq_enable( irq - vrc5477_irq_base);
-}
-
-struct irq_chip vrc5477_irq_controller = {
- .name = "vrc5477_irq",
- .ack = vrc5477_irq_ack,
- .mask = vrc5477_irq_disable,
- .mask_ack = vrc5477_irq_ack,
- .unmask = vrc5477_irq_enable,
- .end = vrc5477_irq_end
-};
-
-void __init vrc5477_irq_init(u32 irq_base)
-{
- u32 i;
-
- for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++)
- set_irq_chip(i, &vrc5477_irq_controller);
-
- vrc5477_irq_base = irq_base;
-}
-
-void ll_vrc5477_irq_route(int vrc5477_irq, int ip)
-{
- u32 reg_value;
- u32 reg_bitmask;
- u32 reg_index;
-
- db_assert(vrc5477_irq >= 0);
- db_assert(vrc5477_irq < NUM_5477_IRQ);
- db_assert(ip >= 0);
- db_assert((ip < 5) || (ip == 6));
-
- reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
- reg_value = ddb_in32(reg_index);
- reg_bitmask = 7 << (vrc5477_irq % 8 * 4);
- reg_value &= ~reg_bitmask;
- reg_value |= ip << (vrc5477_irq % 8 * 4);
- ddb_out32(reg_index, reg_value);
-}
-
-void ll_vrc5477_irq_enable(int vrc5477_irq)
-{
- u32 reg_value;
- u32 reg_bitmask;
- u32 reg_index;
-
- db_assert(vrc5477_irq >= 0);
- db_assert(vrc5477_irq < NUM_5477_IRQ);
-
- reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
- reg_value = ddb_in32(reg_index);
- reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
- db_assert((reg_value & reg_bitmask) == 0);
- ddb_out32(reg_index, reg_value | reg_bitmask);
-}
-
-void ll_vrc5477_irq_disable(int vrc5477_irq)
-{
- u32 reg_value;
- u32 reg_bitmask;
- u32 reg_index;
-
- db_assert(vrc5477_irq >= 0);
- db_assert(vrc5477_irq < NUM_5477_IRQ);
-
- reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
- reg_value = ddb_in32(reg_index);
- reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
-
- /* we assert that the interrupt is enabled (perhaps over-zealous) */
- db_assert( (reg_value & reg_bitmask) != 0);
- ddb_out32(reg_index, reg_value & ~reg_bitmask);
-}
+++ /dev/null
-/*
- * kgdb io functions for DDB5477. We use the second serial port (upper one).
- *
- * Copyright (C) 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-/* ======================= CONFIG ======================== */
-
-/* [jsun] we use the second serial port for kdb */
-#define BASE 0xbfa04240
-#define MAX_BAUD 115200
-
-/* distance in bytes between two serial registers */
-#define REG_OFFSET 8
-
-/*
- * 0 - kgdb does serial init
- * 1 - kgdb skip serial init
- */
-static int remoteDebugInitialized = 0;
-
-/*
- * the default baud rate *if* kgdb does serial init
- */
-#define BAUD_DEFAULT UART16550_BAUD_38400
-
-/* ======================= END OF CONFIG ======================== */
-
-typedef unsigned char uint8;
-typedef unsigned int uint32;
-
-#define UART16550_BAUD_2400 2400
-#define UART16550_BAUD_4800 4800
-#define UART16550_BAUD_9600 9600
-#define UART16550_BAUD_19200 19200
-#define UART16550_BAUD_38400 38400
-#define UART16550_BAUD_57600 57600
-#define UART16550_BAUD_115200 115200
-
-#define UART16550_PARITY_NONE 0
-#define UART16550_PARITY_ODD 0x08
-#define UART16550_PARITY_EVEN 0x18
-#define UART16550_PARITY_MARK 0x28
-#define UART16550_PARITY_SPACE 0x38
-
-#define UART16550_DATA_5BIT 0x0
-#define UART16550_DATA_6BIT 0x1
-#define UART16550_DATA_7BIT 0x2
-#define UART16550_DATA_8BIT 0x3
-
-#define UART16550_STOP_1BIT 0x0
-#define UART16550_STOP_2BIT 0x4
-
-/* register offset */
-#define OFS_RCV_BUFFER 0
-#define OFS_TRANS_HOLD 0
-#define OFS_SEND_BUFFER 0
-#define OFS_INTR_ENABLE (1*REG_OFFSET)
-#define OFS_INTR_ID (2*REG_OFFSET)
-#define OFS_DATA_FORMAT (3*REG_OFFSET)
-#define OFS_LINE_CONTROL (3*REG_OFFSET)
-#define OFS_MODEM_CONTROL (4*REG_OFFSET)
-#define OFS_RS232_OUTPUT (4*REG_OFFSET)
-#define OFS_LINE_STATUS (5*REG_OFFSET)
-#define OFS_MODEM_STATUS (6*REG_OFFSET)
-#define OFS_RS232_INPUT (6*REG_OFFSET)
-#define OFS_SCRATCH_PAD (7*REG_OFFSET)
-
-#define OFS_DIVISOR_LSB (0*REG_OFFSET)
-#define OFS_DIVISOR_MSB (1*REG_OFFSET)
-
-
-/* memory-mapped read/write of the port */
-#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
-#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
-
-void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
-{
- /* disable interrupts */
- UART16550_WRITE(OFS_INTR_ENABLE, 0);
-
- /* set up baud rate */
- {
- uint32 divisor;
-
- /* set DIAB bit */
- UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
-
- /* set divisor */
- divisor = MAX_BAUD / baud;
- UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
- UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
-
- /* clear DIAB bit */
- UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
- }
-
- /* set data format */
- UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
-}
-
-
-uint8 getDebugChar(void)
-{
- if (!remoteDebugInitialized) {
- remoteDebugInitialized = 1;
- debugInit(BAUD_DEFAULT,
- UART16550_DATA_8BIT,
- UART16550_PARITY_NONE, UART16550_STOP_1BIT);
- }
-
- while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
- return UART16550_READ(OFS_RCV_BUFFER);
-}
-
-
-int putDebugChar(uint8 byte)
-{
- if (!remoteDebugInitialized) {
- remoteDebugInitialized = 1;
- debugInit(BAUD_DEFAULT,
- UART16550_DATA_8BIT,
- UART16550_PARITY_NONE, UART16550_STOP_1BIT);
- }
-
- while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
- UART16550_WRITE(OFS_SEND_BUFFER, byte);
- return 1;
-}
+++ /dev/null
-/*
- * lcd44780.c
- * Simple "driver" for a memory-mapped 44780-style LCD display.
- *
- * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#define LCD44780_COMMAND ((volatile unsigned char *)0xbe020000)
-#define LCD44780_DATA ((volatile unsigned char *)0xbe020001)
-
-#define LCD44780_4BIT_1LINE 0x20
-#define LCD44780_4BIT_2LINE 0x28
-#define LCD44780_8BIT_1LINE 0x30
-#define LCD44780_8BIT_2LINE 0x38
-#define LCD44780_MODE_DEC 0x04
-#define LCD44780_MODE_DEC_SHIFT 0x05
-#define LCD44780_MODE_INC 0x06
-#define LCD44780_MODE_INC_SHIFT 0x07
-#define LCD44780_SCROLL_LEFT 0x18
-#define LCD44780_SCROLL_RIGHT 0x1e
-#define LCD44780_CURSOR_UNDERLINE 0x0e
-#define LCD44780_CURSOR_BLOCK 0x0f
-#define LCD44780_CURSOR_OFF 0x0c
-#define LCD44780_CLEAR 0x01
-#define LCD44780_BLANK 0x08
-#define LCD44780_RESTORE 0x0c // Same as CURSOR_OFF
-#define LCD44780_HOME 0x02
-#define LCD44780_LEFT 0x10
-#define LCD44780_RIGHT 0x14
-
-void lcd44780_wait(void)
-{
- int i, j;
- for(i=0; i < 400; i++)
- for(j=0; j < 10000; j++);
-}
-
-void lcd44780_command(unsigned char c)
-{
- *LCD44780_COMMAND = c;
- lcd44780_wait();
-}
-
-void lcd44780_data(unsigned char c)
-{
- *LCD44780_DATA = c;
- lcd44780_wait();
-}
-
-void lcd44780_puts(const char* s)
-{
- int j;
- int pos = 0;
-
- lcd44780_command(LCD44780_CLEAR);
- while(*s) {
- lcd44780_data(*s);
- s++;
- pos++;
- if (pos == 8) {
- /* We must write 32 of spaces to get cursor to 2nd line */
- for (j=0; j<32; j++) {
- lcd44780_data(' ');
- }
- }
- if (pos == 16) {
- /* We have filled all 16 character positions, so stop
- outputing data */
- break;
- }
- }
-#ifdef LCD44780_PUTS_PAUSE
- {
- int i;
-
- for(i = 1; i < 2000; i++)
- lcd44780_wait();
- }
-#endif
-}
-
-void lcd44780_init(void)
-{
- // The display on the RockHopper is physically a single
- // 16 char line (two 8 char lines concatenated). bdl
- lcd44780_command(LCD44780_8BIT_2LINE);
- lcd44780_command(LCD44780_MODE_INC);
- lcd44780_command(LCD44780_CURSOR_BLOCK);
- lcd44780_command(LCD44780_CLEAR);
-}
+++ /dev/null
-/*
- * lcd44780.h
- * Simple "driver" for a memory-mapped 44780-style LCD display.
- *
- * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-void lcd44780_puts(const char* s);
-void lcd44780_init(void);
+++ /dev/null
-/*
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- *
- * arch/mips/ddb5xxx/ddb5477/setup.c
- * Setup file for DDB5477.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/pci.h>
-#include <linux/ide.h>
-#include <linux/irq.h>
-#include <linux/fs.h>
-#include <linux/ioport.h>
-#include <linux/param.h> /* for HZ */
-#include <linux/major.h>
-#include <linux/kdev_t.h>
-#include <linux/root_dev.h>
-#include <linux/pm.h>
-
-#include <asm/cpu.h>
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-#include <asm/time.h>
-#include <asm/bcache.h>
-#include <asm/irq.h>
-#include <asm/reboot.h>
-#include <asm/gdb-stub.h>
-#include <asm/traps.h>
-#include <asm/debug.h>
-
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-#include "lcd44780.h"
-
-
-#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
-
-#define SP_TIMER_BASE DDB_SPT1CTRL_L
-#define SP_TIMER_IRQ VRC5477_IRQ_SPT1
-
-static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000;
-
-static void ddb_machine_restart(char *command)
-{
- static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
-
- u32 t;
-
- /* PCI cold reset */
- ddb_pci_reset_bus();
-
- /* CPU cold reset */
- t = ddb_in32(DDB_CPUSTAT);
- db_assert((t&1));
- ddb_out32(DDB_CPUSTAT, t);
-
- /* Call the PROM */
- back_to_prom();
-}
-
-static void ddb_machine_halt(void)
-{
- printk("DDB Vrc-5477 halted.\n");
- while (1);
-}
-
-static void ddb_machine_power_off(void)
-{
- printk("DDB Vrc-5477 halted. Please turn off the power.\n");
- while (1);
-}
-
-extern void rtc_ds1386_init(unsigned long base);
-
-static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
-{
- unsigned int freq;
- unsigned char c;
- unsigned int t1, t2;
- unsigned i;
-
- ddb_out32(SP_TIMER_BASE, 0xffffffff);
- ddb_out32(SP_TIMER_BASE+4, 0x1);
- ddb_out32(SP_TIMER_BASE+8, 0xffffffff);
-
- /* check if rtc is running */
- c= *(volatile unsigned char*)rtc_base;
- for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++);
- if (c == *(volatile unsigned char*)rtc_base) {
- printk("Failed to detect bus frequency. Use default 83.3MHz.\n");
- return 83333000;
- }
-
- c= *(volatile unsigned char*)rtc_base;
- while (c == *(volatile unsigned char*)rtc_base);
- /* we are now at the turn of 1/100th second, if no error. */
- t1 = ddb_in32(SP_TIMER_BASE+8);
-
- for (i=0; i< 10; i++) {
- c= *(volatile unsigned char*)rtc_base;
- while (c == *(volatile unsigned char*)rtc_base);
- /* we are now at the turn of another 1/100th second */
- t2 = ddb_in32(SP_TIMER_BASE+8);
- }
-
- ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */
-
- freq = (t1 - t2)*10;
- printk("DDB bus frequency detection : %u \n", freq);
- return freq;
-}
-
-static void __init ddb_time_init(void)
-{
- unsigned long rtc_base;
- unsigned int i;
-
- /* we have ds1396 RTC chip */
- if (mips_machtype == MACH_NEC_ROCKHOPPER
- || mips_machtype == MACH_NEC_ROCKHOPPERII) {
- rtc_base = KSEG1ADDR(DDB_LCS2_BASE);
- } else {
- rtc_base = KSEG1ADDR(DDB_LCS1_BASE);
- }
- rtc_ds1386_init(rtc_base);
-
- /* do we need to do run-time detection of bus speed? */
- if (bus_frequency == 0) {
- bus_frequency = detect_bus_frequency(rtc_base);
- }
-
- /* mips_hpt_frequency is 1/2 of the cpu core freq */
- i = (read_c0_config() >> 28 ) & 7;
- if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
- i = 4;
- mips_hpt_frequency = bus_frequency*(i+4)/4;
-}
-
-void __init plat_timer_setup(struct irqaction *irq)
-{
-#if defined(USE_CPU_COUNTER_TIMER)
-
- /* we are using the cpu counter for timer interrupts */
- setup_irq(CPU_IRQ_BASE + 7, irq);
-
-#else
-
- /* if we use Special purpose timer 1 */
- ddb_out32(SP_TIMER_BASE, bus_frequency/HZ);
- ddb_out32(SP_TIMER_BASE+4, 0x1);
- setup_irq(SP_TIMER_IRQ, irq);
-
-#endif
-}
-
-static void ddb5477_board_init(void);
-
-extern struct pci_controller ddb5477_ext_controller;
-extern struct pci_controller ddb5477_io_controller;
-
-void __init plat_mem_setup(void)
-{
- /* initialize board - we don't trust the loader */
- ddb5477_board_init();
-
- set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
-
- board_time_init = ddb_time_init;
-
- _machine_restart = ddb_machine_restart;
- _machine_halt = ddb_machine_halt;
- pm_power_off = ddb_machine_power_off;
-
- /* setup resource limits */
- ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
- iomem_resource.end = 0xffffffff;
-
- /* Reboot on panic */
- panic_timeout = 180;
-
- register_pci_controller (&ddb5477_ext_controller);
- register_pci_controller (&ddb5477_io_controller);
-}
-
-static void __init ddb5477_board_init(void)
-{
- /* ----------- setup PDARs ------------ */
-
- /* SDRAM should have been set */
- db_assert(ddb_in32(DDB_SDRAM0) ==
- ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1));
-
- /* SDRAM1 should be turned off. What is this for anyway ? */
- db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
-
- /* Setup local bus. */
-
- /* Flash U12 PDAR and timing. */
- ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
- ddb_out32(DDB_LCST0, 0x00090842);
-
- /* We need to setup LCS1 and LCS2 differently based on the
- board_version */
- if (mips_machtype == MACH_NEC_ROCKHOPPER) {
- /* Flash U13 PDAR and timing. */
- ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0);
- ddb_out32(DDB_LCST1, 0x00090842);
-
- /* EPLD (NVRAM, switch, LCD, and mezzanie). */
- ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0);
- } else {
- /* misc */
- ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
- /* mezzanie (?) */
- ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
- }
-
- /* verify VRC5477 base addr */
- db_assert(ddb_in32(DDB_VRC5477) ==
- ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
-
- /* verify BOOT ROM addr */
- db_assert(ddb_in32(DDB_BOOTCS) ==
- ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
-
- /* setup PCI windows - window0 for MEM/config, window1 for IO */
- ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
- ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
- ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
- ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
-
- /* ------------ reset PCI bus and BARs ----------------- */
- ddb_pci_reset_bus();
-
- ddb_out32(DDB_BARM010, 0x00000008);
- ddb_out32(DDB_BARM011, 0x00000008);
-
- ddb_out32(DDB_BARC0, 0xffffffff);
- ddb_out32(DDB_BARM230, 0xffffffff);
- ddb_out32(DDB_BAR00, 0xffffffff);
- ddb_out32(DDB_BAR10, 0xffffffff);
- ddb_out32(DDB_BAR20, 0xffffffff);
- ddb_out32(DDB_BAR30, 0xffffffff);
- ddb_out32(DDB_BAR40, 0xffffffff);
- ddb_out32(DDB_BAR50, 0xffffffff);
- ddb_out32(DDB_BARB0, 0xffffffff);
-
- ddb_out32(DDB_BARC1, 0xffffffff);
- ddb_out32(DDB_BARM231, 0xffffffff);
- ddb_out32(DDB_BAR01, 0xffffffff);
- ddb_out32(DDB_BAR11, 0xffffffff);
- ddb_out32(DDB_BAR21, 0xffffffff);
- ddb_out32(DDB_BAR31, 0xffffffff);
- ddb_out32(DDB_BAR41, 0xffffffff);
- ddb_out32(DDB_BAR51, 0xffffffff);
- ddb_out32(DDB_BARB1, 0xffffffff);
-
- /*
- * We use pci master register 0 for memory space / config space
- * And we use register 1 for IO space.
- * Note that for memory space, we bump up the pci base address
- * so that we have 1:1 mapping between PCI memory and cpu physical.
- * For PCI IO space, it starts from 0 in PCI IO space but with
- * DDB_xx_IO_BASE in CPU physical address space.
- */
- ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
- DDB_PCI_ACCESS_32);
- ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
-
- ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
- DDB_PCI_ACCESS_32);
- ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
- DDB_PCI_ACCESS_32);
-
-
- /* PCI cross window should be set properly */
- ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
- ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
- ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
- ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
-
- if (mips_machtype == MACH_NEC_ROCKHOPPER
- || mips_machtype == MACH_NEC_ROCKHOPPERII) {
- /* Disable bus diagnostics. */
- ddb_out32(DDB_PCICTL0_L, 0);
- ddb_out32(DDB_PCICTL0_H, 0);
- ddb_out32(DDB_PCICTL1_L, 0);
- ddb_out32(DDB_PCICTL1_H, 0);
- }
-
- if (mips_machtype == MACH_NEC_ROCKHOPPER) {
- u16 vid;
- struct pci_bus bus;
- struct pci_dev dev_m1533;
- extern struct pci_ops ddb5477_ext_pci_ops;
-
- bus.parent = NULL; /* we scan the top level only */
- bus.ops = &ddb5477_ext_pci_ops;
- dev_m1533.bus = &bus;
- dev_m1533.sysdata = NULL;
- dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
- pci_read_config_word(&dev_m1533, 0, &vid);
- if (vid == PCI_VENDOR_ID_AL) {
- printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n");
- mips_machtype = MACH_NEC_ROCKHOPPERII;
- }
- }
-
- /* enable USB input buffers */
- ddb_out32(DDB_PIBMISC, 0x00000007);
-
- /* For dual-function pins, make them all non-GPIO */
- ddb_out32(DDB_GIUFUNSEL, 0x0);
- // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */
-
- if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
-
- /* enable IDE controller on Ali chip (south bridge) */
- u8 temp8;
- struct pci_bus bus;
- struct pci_dev dev_m1533;
- struct pci_dev dev_m5229;
- extern struct pci_ops ddb5477_ext_pci_ops;
-
- /* Setup M1535 registers */
- bus.parent = NULL; /* we scan the top level only */
- bus.ops = &ddb5477_ext_pci_ops;
- dev_m1533.bus = &bus;
- dev_m1533.sysdata = NULL;
- dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
-
- /* setup IDE controller
- * enable IDE controller (bit 6 - 1)
- * IDE IDSEL to be addr:A15 (bit 4:5 - 11)
- * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
- * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1)
- */
- pci_write_config_byte(&dev_m1533, 0x58, 0x74);
-
- /*
- * positive decode (bit6 -0)
- * enable IDE controler interrupt (bit 4 -1)
- * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
- */
- pci_write_config_byte(&dev_m1533, 0x44, 0x1d);
-
- /* Setup M5229 registers */
- dev_m5229.bus = &bus;
- dev_m5229.sysdata = NULL;
- dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
-
- /*
- * enable IDE in the M5229 config register 0x50 (bit 0 - 1)
- * M5229 IDSEL is addr:15; see above setting
- */
- pci_read_config_byte(&dev_m5229, 0x50, &temp8);
- pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
-
- /*
- * enable bus master (bit 2) and IO decoding (bit 0)
- */
- pci_read_config_byte(&dev_m5229, 0x04, &temp8);
- pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
-
- /*
- * enable native, copied from arch/ppc/k2boot/head.S
- * TODO - need volatile, need to be portable
- */
- pci_write_config_byte(&dev_m5229, 0x09, 0xef);
-
- /* Set Primary Channel Command Block Timing */
- pci_write_config_byte(&dev_m5229, 0x59, 0x31);
-
- /*
- * Enable primary channel 40-pin cable
- * M5229 register 0x4a (bit 0)
- */
- pci_read_config_byte(&dev_m5229, 0x4a, &temp8);
- pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1);
- }
-
- if (mips_machtype == MACH_NEC_ROCKHOPPER
- || mips_machtype == MACH_NEC_ROCKHOPPERII) {
- printk("lcd44780: initializing\n");
- lcd44780_init();
- lcd44780_puts("MontaVista Linux");
- }
-}
obj-$(CONFIG_PROM_CONSOLE) += promcon.o
obj-$(CONFIG_TC) += tc.o
obj-$(CONFIG_CPU_HAS_WB) += wbflush.o
+
+EXTRA_CFLAGS += -Werror
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
+++ /dev/null
-#
-# Makefile for common code of gt64120-based boards.
-#
-
-obj-y += time.o
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * Galileo Technology chip interrupt handler
- */
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <asm/irq_regs.h>
-#include <asm/gt64120.h>
-
-/*
- * These are interrupt handlers for the GT on-chip interrupts. They all come
- * in to the MIPS on a single interrupt line, and have to be handled and ack'ed
- * differently than other MIPS interrupts.
- */
-
-static irqreturn_t gt64120_irq(int irq, void *dev_id)
-{
- unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask;
- int handled = 0;
-
- irq_src = GT_READ(GT_INTRCAUSE_OFS);
- irq_src_mask = GT_READ(GT_INTRMASK_OFS);
- int_high_src = GT_READ(GT_HINTRCAUSE_OFS);
- int_high_src_mask = GT_READ(GT_HINTRMASK_OFS);
- irq_src = irq_src & irq_src_mask;
- int_high_src = int_high_src & int_high_src_mask;
-
- if (irq_src & 0x00000800) { /* Check for timer interrupt */
- handled = 1;
- irq_src &= ~0x00000800;
- do_timer(1);
-#ifndef CONFIG_SMP
- update_process_times(user_mode(get_irq_regs()));
-#endif
- }
-
- GT_WRITE(GT_INTRCAUSE_OFS, 0);
- GT_WRITE(GT_HINTRCAUSE_OFS, 0);
-
- return IRQ_HANDLED;
-}
-
-/*
- * Initializes timer using galileo's built in timer.
- */
-#ifdef CONFIG_SYSCLK_100
-#define Sys_clock (100 * 1000000) // 100 MHz
-#endif
-#ifdef CONFIG_SYSCLK_83
-#define Sys_clock (83.333 * 1000000) // 83.333 MHz
-#endif
-#ifdef CONFIG_SYSCLK_75
-#define Sys_clock (75 * 1000000) // 75 MHz
-#endif
-
-/*
- * This will ignore the standard MIPS timer interrupt handler that is passed in
- * as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt
- * handling.
- */
-void __init plat_timer_setup(struct irqaction *irq)
-{
- static struct irqaction timer;
-
- /* Disable timer first */
- GT_WRITE(GT_TC_CONTROL_OFS, 0);
- /* Load timer value for 100 Hz */
- GT_WRITE(GT_TC3_OFS, Sys_clock / HZ);
-
- /*
- * Create the IRQ structure entry for the timer. Since we're too early
- * in the boot process to use the "request_irq()" call, we'll hard-code
- * the values to the correct interrupt line.
- */
- timer.handler = gt64120_irq;
- timer.flags = IRQF_SHARED | IRQF_DISABLED;
- timer.name = "timer";
- timer.dev_id = NULL;
- timer.next = NULL;
- timer.mask = CPU_MASK_NONE;
- irq_desc[GT_TIMER].action = &timer;
-
- enable_irq(GT_TIMER);
-
- /* Enable timer ints */
- GT_WRITE(GT_TC_CONTROL_OFS, 0xc0);
- /* clear Cause register first */
- GT_WRITE(GT_INTRCAUSE_OFS, 0x0);
- /* Unmask timer int */
- GT_WRITE(GT_INTRMASK_OFS, 0x800);
- /* Clear High int register */
- GT_WRITE(GT_HINTRCAUSE_OFS, 0x0);
- /* Mask All interrupts at High cause interrupt */
- GT_WRITE(GT_HINTRMASK_OFS, 0x0);
-}
+++ /dev/null
-#
-# Makefile for Momentum's Ocelot board.
-#
-
-obj-y += irq.o ocelot-platform.o prom.o reset.o setup.o
-
-obj-$(CONFIG_KGDB) += dbg_io.o
+++ /dev/null
-
-#include <asm/serial.h> /* For the serial port location and base baud */
-
-/* --- CONFIG --- */
-
-typedef unsigned char uint8;
-typedef unsigned int uint32;
-
-/* --- END OF CONFIG --- */
-
-#define UART16550_BAUD_2400 2400
-#define UART16550_BAUD_4800 4800
-#define UART16550_BAUD_9600 9600
-#define UART16550_BAUD_19200 19200
-#define UART16550_BAUD_38400 38400
-#define UART16550_BAUD_57600 57600
-#define UART16550_BAUD_115200 115200
-
-#define UART16550_PARITY_NONE 0
-#define UART16550_PARITY_ODD 0x08
-#define UART16550_PARITY_EVEN 0x18
-#define UART16550_PARITY_MARK 0x28
-#define UART16550_PARITY_SPACE 0x38
-
-#define UART16550_DATA_5BIT 0x0
-#define UART16550_DATA_6BIT 0x1
-#define UART16550_DATA_7BIT 0x2
-#define UART16550_DATA_8BIT 0x3
-
-#define UART16550_STOP_1BIT 0x0
-#define UART16550_STOP_2BIT 0x4
-
-/* ----------------------------------------------------- */
-
-/* === CONFIG === */
-
-/* [jsun] we use the second serial port for kdb */
-#define BASE OCELOT_SERIAL1_BASE
-#define MAX_BAUD OCELOT_BASE_BAUD
-
-/* === END OF CONFIG === */
-
-#define REG_OFFSET 4
-
-/* register offset */
-#define OFS_RCV_BUFFER 0
-#define OFS_TRANS_HOLD 0
-#define OFS_SEND_BUFFER 0
-#define OFS_INTR_ENABLE (1*REG_OFFSET)
-#define OFS_INTR_ID (2*REG_OFFSET)
-#define OFS_DATA_FORMAT (3*REG_OFFSET)
-#define OFS_LINE_CONTROL (3*REG_OFFSET)
-#define OFS_MODEM_CONTROL (4*REG_OFFSET)
-#define OFS_RS232_OUTPUT (4*REG_OFFSET)
-#define OFS_LINE_STATUS (5*REG_OFFSET)
-#define OFS_MODEM_STATUS (6*REG_OFFSET)
-#define OFS_RS232_INPUT (6*REG_OFFSET)
-#define OFS_SCRATCH_PAD (7*REG_OFFSET)
-
-#define OFS_DIVISOR_LSB (0*REG_OFFSET)
-#define OFS_DIVISOR_MSB (1*REG_OFFSET)
-
-
-/* memory-mapped read/write of the port */
-#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
-#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
-
-void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
-{
- /* disable interrupts */
- UART16550_WRITE(OFS_INTR_ENABLE, 0);
-
- /* set up baud rate */
- {
- uint32 divisor;
-
- /* set DIAB bit */
- UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
-
- /* set divisor */
- divisor = MAX_BAUD / baud;
- UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
- UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
-
- /* clear DIAB bit */
- UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
- }
-
- /* set data format */
- UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
-}
-
-static int remoteDebugInitialized = 0;
-
-uint8 getDebugChar(void)
-{
- if (!remoteDebugInitialized) {
- remoteDebugInitialized = 1;
- debugInit(UART16550_BAUD_38400,
- UART16550_DATA_8BIT,
- UART16550_PARITY_NONE, UART16550_STOP_1BIT);
- }
-
- while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
- return UART16550_READ(OFS_RCV_BUFFER);
-}
-
-
-int putDebugChar(uint8 byte)
-{
- if (!remoteDebugInitialized) {
- remoteDebugInitialized = 1;
- debugInit(UART16550_BAUD_38400,
- UART16550_DATA_8BIT,
- UART16550_PARITY_NONE, UART16550_STOP_1BIT);
- }
-
- while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
- UART16550_WRITE(OFS_SEND_BUFFER, byte);
- return 1;
-}
+++ /dev/null
-/*
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: RidgeRun, Inc.
- * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- * Copyright (C) 2000, 2001, 2003 Ralf Baechle (ralf@gnu.org)
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/bitops.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-#include <asm/system.h>
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int pending = read_c0_status() & read_c0_cause();
-
- if (pending & STATUSF_IP2) /* int0 hardware line */
- do_IRQ(2);
- else if (pending & STATUSF_IP3) /* int1 hardware line */
- do_IRQ(3);
- else if (pending & STATUSF_IP4) /* int2 hardware line */
- do_IRQ(4);
- else if (pending & STATUSF_IP5) /* int3 hardware line */
- do_IRQ(5);
- else if (pending & STATUSF_IP6) /* int4 hardware line */
- do_IRQ(6);
- else if (pending & STATUSF_IP7) /* cpu timer */
- do_IRQ(7);
- else {
- /*
- * Now look at the extended interrupts
- */
- pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
-
- if (pending & STATUSF_IP8) /* int6 hardware line */
- do_IRQ(8);
- else if (pending & STATUSF_IP9) /* int7 hardware line */
- do_IRQ(9);
- else if (pending & STATUSF_IP10) /* int8 hardware line */
- do_IRQ(10);
- else if (pending & STATUSF_IP11) /* int9 hardware line */
- do_IRQ(11);
- }
-}
-
-void __init arch_init_irq(void)
-{
- /*
- * Clear all of the interrupts while we change the able around a bit.
- * int-handler is not on bootstrap
- */
- clear_c0_status(ST0_IM);
- local_irq_disable();
-
- mips_cpu_irq_init();
- rm7k_cpu_irq_init();
-}
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
- *
- * A NS16552 DUART with a 20MHz crystal.
- *
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/serial_8250.h>
-
-#define OCELOT_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
-
-static struct plat_serial8250_port uart8250_data[] = {
- {
- .mapbase = 0xe0001020,
- .irq = 4,
- .uartclk = 20000000,
- .iotype = UPIO_MEM,
- .flags = OCELOT_UART_FLAGS,
- .regshift = 2,
- },
- { },
-};
-
-static struct platform_device uart8250_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = uart8250_data,
- },
-};
-
-static int __init uart8250_init(void)
-{
- return platform_device_register(&uart8250_device);
-}
-
-module_init(uart8250_init);
-
-MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("8250 UART probe driver for the Momenco Ocelot");
+++ /dev/null
-/*
- * Ocelot Board Register Definitions
- *
- * (C) 2001 Red Hat, Inc.
- *
- * GPL'd
- */
-#ifndef __MOMENCO_OCELOT_PLD_H__
-#define __MOMENCO_OCELOT_PLD_H__
-
-#define OCELOT_CS0_ADDR (0xe0020000)
-
-#define OCELOT_REG_BOARDREV (0)
-#define OCELOT_REG_PLD1_ID (1)
-#define OCELOT_REG_PLD2_ID (2)
-#define OCELOT_REG_RESET_STATUS (3)
-#define OCELOT_REG_BOARD_STATUS (4)
-#define OCELOT_REG_CPCI_ID (5)
-#define OCELOT_REG_I2C_CTRL (8)
-#define OCELOT_REG_EEPROM_MODE (9)
-#define OCELOT_REG_INTMASK (10)
-#define OCELOT_REG_INTSTATUS (11)
-#define OCELOT_REG_INTSET (12)
-#define OCELOT_REG_INTCLR (13)
-
-#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y)
-#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x)
-
-
-#endif /* __MOMENCO_OCELOT_PLD_H__ */
+++ /dev/null
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/bootmem.h>
-
-#include <asm/addrspace.h>
-#include <asm/bootinfo.h>
-#include <asm/pmon.h>
-
-struct callvectors* debug_vectors;
-
-extern unsigned long gt64120_base;
-
-const char *get_system_type(void)
-{
- return "Momentum Ocelot";
-}
-
-/* [jsun@junsun.net] PMON passes arguments in C main() style */
-void __init prom_init(void)
-{
- int argc = fw_arg0;
- char **arg = (char **) fw_arg1;
- char **env = (char **) fw_arg2;
- struct callvectors *cv = (struct callvectors *) fw_arg3;
- int i;
-
- /* save the PROM vectors for debugging use */
- debug_vectors = cv;
-
- /* arg[0] is "g", the rest is boot parameters */
- arcs_cmdline[0] = '\0';
- for (i = 1; i < argc; i++) {
- if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
- >= sizeof(arcs_cmdline))
- break;
- strcat(arcs_cmdline, arg[i]);
- strcat(arcs_cmdline, " ");
- }
-
- mips_machgroup = MACH_GROUP_MOMENCO;
- mips_machtype = MACH_MOMENCO_OCELOT;
-
- while (*env) {
- if (strncmp("gtbase", *env, 6) == 0) {
- gt64120_base = simple_strtol(*env + strlen("gtbase="),
- NULL, 16);
- break;
- }
- *env++;
- }
-
- debug_vectors->printf("Booting Linux kernel...\n");
-
- /* All the boards have at least 64MiB. If there's more, we
- detect and register it later */
- add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
-}
-
-void __init prom_free_prom_memory(void)
-{
-}
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * Copyright (C) 1997, 2001 Ralf Baechle
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/system.h>
-#include <linux/delay.h>
-
-void momenco_ocelot_restart(char *command)
-{
- void *nvram = ioremap_nocache(0x2c807000, 0x1000);
-
- if (!nvram) {
- printk(KERN_NOTICE "ioremap of reset register failed\n");
- return;
- }
- writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
- assert reset in 1/16 second */
- mdelay(10+(1000/16));
- iounmap(nvram);
- printk(KERN_NOTICE "Watchdog reset failed\n");
-}
-
-void momenco_ocelot_halt(void)
-{
- printk(KERN_NOTICE "\n** You can safely turn off the power\n");
- while (1)
- __asm__(".set\tmips3\n\t"
- "wait\n\t"
- ".set\tmips0");
-}
-
-void momenco_ocelot_power_off(void)
-{
- momenco_ocelot_halt();
-}
+++ /dev/null
-/*
- * setup.c
- *
- * BRIEF MODULE DESCRIPTION
- * Momentum Computer Ocelot (CP7000) - board dependent boot routines
- *
- * Copyright (C) 1996, 1997, 2001, 06 Ralf Baechle (ralf@linux-mips.org)
- * Copyright (C) 2000 RidgeRun, Inc.
- * Copyright (C) 2001 Red Hat, Inc.
- * Copyright (C) 2002 Momentum Computer
- *
- * Author: RidgeRun, Inc.
- * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/swap.h>
-#include <linux/ioport.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#include <linux/timex.h>
-#include <linux/vmalloc.h>
-#include <linux/pm.h>
-
-#include <asm/time.h>
-#include <asm/bootinfo.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/pci.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/traps.h>
-#include <linux/bootmem.h>
-#include <linux/initrd.h>
-#include <asm/gt64120.h>
-#include "ocelot_pld.h"
-
-unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE);
-
-/* These functions are used for rebooting or halting the machine*/
-extern void momenco_ocelot_restart(char *command);
-extern void momenco_ocelot_halt(void);
-extern void momenco_ocelot_power_off(void);
-
-extern void momenco_ocelot_irq_setup(void);
-
-static char reset_reason;
-
-#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1)
-
-static void __init setup_l3cache(unsigned long size);
-
-/* setup code for a handoff from a version 1 PMON 2000 PROM */
-static void PMON_v1_setup(void)
-{
- /* A wired TLB entry for the GT64120A and the serial port. The
- GT64120A is going to be hit on every IRQ anyway - there's
- absolutely no point in letting it be a random TLB entry, as
- it'll just cause needless churning of the TLB. And we use
- the other half for the serial port, which is just a PITA
- otherwise :)
-
- Device Physical Virtual
- GT64120 Internal Regs 0x24000000 0xe0000000
- UARTs (CS2) 0x2d000000 0xe0001000
- */
- add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K);
-
- /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
- in the CS[012] region. We can't use ioremap() yet. The NVRAM
- is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
-
- Ocelot PLD (CS0) 0x2c000000 0xe0020000
- NVRAM 0x2c800000 0xe0030000
- */
-
- add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K);
-
- /* Relocate the CS3/BootCS region */
- GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21);
-
- /* Relocate CS[012] */
- GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21);
-
- /* Relocate the GT64120A itself... */
- GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21);
- mb();
- gt64120_base = 0xe0000000;
-
- /* ...and the PCI0 view of it. */
- GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020);
- GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000);
- GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024);
- GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001);
-}
-
-/* setup code for a handoff from a version 2 PMON 2000 PROM */
-void PMON_v2_setup()
-{
- /* A wired TLB entry for the GT64120A and the serial port. The
- GT64120A is going to be hit on every IRQ anyway - there's
- absolutely no point in letting it be a random TLB entry, as
- it'll just cause needless churning of the TLB. And we use
- the other half for the serial port, which is just a PITA
- otherwise :)
-
- Device Physical Virtual
- GT64120 Internal Regs 0xf4000000 0xe0000000
- UARTs (CS2) 0xfd000000 0xe0001000
- */
- add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K);
-
- /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
- in the CS[012] region. We can't use ioremap() yet. The NVRAM
- is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
-
- Ocelot PLD (CS0) 0xfc000000 0xe0020000
- NVRAM 0xfc800000 0xe0030000
- */
- add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K);
-
- gt64120_base = 0xe0000000;
-}
-
-void __init plat_mem_setup(void)
-{
- void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
- unsigned int tmpword;
-
- _machine_restart = momenco_ocelot_restart;
- _machine_halt = momenco_ocelot_halt;
- pm_power_off = momenco_ocelot_power_off;
-
- /*
- * initrd_start = (unsigned long)ocelot_initrd_start;
- * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
- * initrd_below_start_ok = 1;
- */
-
- /* do handoff reconfiguration */
- if (gt64120_base == KSEG1ADDR(GT_DEF_BASE))
- PMON_v1_setup();
- else
- PMON_v2_setup();
-
- /* Turn off the Bit-Error LED */
- OCELOT_PLD_WRITE(0x80, INTCLR);
-
- /* Relocate all the PCI1 stuff, not that we use it */
- GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21);
- GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
- GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
-
- /* Relocate PCI0 I/O and Mem0 */
- GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21);
- GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21);
-
- /* Relocate PCI0 Mem1 */
- GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21);
-
- /* For the initial programming, we assume 512MB configuration */
- /* Relocate the CPU's view of the RAM... */
- GT_WRITE(GT_SCS10LD_OFS, 0);
- GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21);
- GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21);
- GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
-
- GT_WRITE(GT_SCS1LD_OFS, 0xff);
- GT_WRITE(GT_SCS1HD_OFS, 0x00);
- GT_WRITE(GT_SCS0LD_OFS, 0);
- GT_WRITE(GT_SCS0HD_OFS, 0xff);
- GT_WRITE(GT_SCS3LD_OFS, 0xff);
- GT_WRITE(GT_SCS3HD_OFS, 0x00);
- GT_WRITE(GT_SCS2LD_OFS, 0);
- GT_WRITE(GT_SCS2HD_OFS, 0xff);
-
- /* ...and the PCI0 view of it. */
- GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010);
- GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000);
- GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
- GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000);
- GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
- GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
-
- tmpword = OCELOT_PLD_READ(BOARDREV);
- if (tmpword < 26)
- printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword);
- else
- printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword);
-
- tmpword = OCELOT_PLD_READ(PLD1_ID);
- printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
- tmpword = OCELOT_PLD_READ(PLD2_ID);
- printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
- tmpword = OCELOT_PLD_READ(RESET_STATUS);
- printk("Reset reason: 0x%x\n", tmpword);
- reset_reason = tmpword;
- OCELOT_PLD_WRITE(0xff, RESET_STATUS);
-
- tmpword = OCELOT_PLD_READ(BOARD_STATUS);
- printk("Board Status register: 0x%02x\n", tmpword);
- printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
- printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
- printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
- printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
- printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
-
- if (tmpword&12)
- l3func((1<<(((tmpword&12) >> 2)+20)));
-
- switch(tmpword &3) {
- case 3:
- /* 512MiB */
- /* Decoders are allready set -- just add the
- * appropriate region */
- add_memory_region( 0x40<<20, 0xC0<<20, BOOT_MEM_RAM);
- add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
- break;
- case 2:
- /* 256MiB -- two banks of 128MiB */
- GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21);
- GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21);
- GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
-
- GT_WRITE(GT_SCS0HD_OFS, 0x7f);
- GT_WRITE(GT_SCS2LD_OFS, 0x80);
- GT_WRITE(GT_SCS2HD_OFS, 0xff);
-
- /* reconfigure the PCI0 interface view of memory */
- GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
- GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000);
- GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
- GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
-
- add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
- add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
- break;
- case 1:
- /* 128MiB -- 64MiB per bank */
- GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21);
- GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21);
- GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21);
-
- GT_WRITE(GT_SCS0HD_OFS, 0x3f);
- GT_WRITE(GT_SCS2LD_OFS, 0x40);
- GT_WRITE(GT_SCS2HD_OFS, 0x7f);
-
- /* reconfigure the PCI0 interface view of memory */
- GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
- GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
- GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000);
- GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000);
-
- /* add the appropriate region */
- add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
- break;
- case 0:
- /* 64MiB */
- GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21);
- GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21);
- GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21);
-
- GT_WRITE(GT_SCS0HD_OFS, 0x1f);
- GT_WRITE(GT_SCS2LD_OFS, 0x20);
- GT_WRITE(GT_SCS2HD_OFS, 0x3f);
-
- /* reconfigure the PCI0 interface view of memory */
- GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
- GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
- GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000);
- GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000);
-
- break;
- }
-
- /* Fix up the DiskOnChip mapping */
- GT_WRITE(GT_DEV_B3_OFS, 0xfef73);
-}
-
-extern int rm7k_tcache_enabled;
-/*
- * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
- */
-#define Page_Invalidate_T 0x16
-static void __init setup_l3cache(unsigned long size)
-{
- int register i;
- unsigned long tmp;
-
- printk("Enabling L3 cache...");
-
- /* Enable the L3 cache in the GT64120A's CPU Configuration register */
- tmp = GT_READ(GT_CPU_OFS);
- GT_WRITE(GT_CPU_OFS, tmp | (1<<14));
-
- /* Enable the L3 cache in the CPU */
- set_c0_config(1<<12 /* CONF_TE */);
-
- /* Clear the cache */
- write_c0_taglo(0);
- write_c0_taghi(0);
-
- for (i=0; i < size; i+= 4096) {
- __asm__ __volatile__ (
- ".set noreorder\n\t"
- ".set mips3\n\t"
- "cache %1, (%0)\n\t"
- ".set mips0\n\t"
- ".set reorder"
- :
- : "r" (KSEG0ADDR(i)),
- "i" (Page_Invalidate_T));
- }
-
- /* Let the RM7000 MM code know that the tertiary cache is enabled */
- rm7k_tcache_enabled = 1;
-
- printk("Done\n");
-}
-
-
-/* This needs to be one of the first initcalls, because no I/O port access
- can work before this */
-
-static int io_base_ioremap(void)
-{
- void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE);
-
- if (!io_remap_range) {
- panic("Could not ioremap I/O port range");
- }
- set_io_port_base(io_remap_range - GT_PCI_IO_BASE);
-
- return 0;
-}
-
-module_init(io_base_ioremap);
#
obj-y += irq.o reset.o setup.o time.o pci.o
+
+EXTRA_CFLAGS += -Werror
#
obj-y := irq.o jazzdma.o jazz-platform.o reset.o setup.o
+
+EXTRA_CFLAGS += -Werror
#
obj-y += prom.o puts.o
+
+EXTRA_CFLAGS += -Werror
obj-y += init.o irq.o setup.o
obj-$(CONFIG_KGDB) += kgdb_io.o
+
+EXTRA_CFLAGS += -Werror
CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o
+
+EXTRA_CFLAGS += -Werror
offset("#define THREAD_ECODE ", struct task_struct, \
thread.error_code);
offset("#define THREAD_TRAPNO ", struct task_struct, thread.trap_no);
- offset("#define THREAD_MFLAGS ", struct task_struct, thread.mflags);
offset("#define THREAD_TRAMP ", struct task_struct, \
thread.irix_trampoline);
offset("#define THREAD_OLDCTX ", struct task_struct, \
.fill 0x400
#endif
-EXPORT(stext) # used for profiling
EXPORT(_stext)
#ifndef CONFIG_BOOT_RAW
#define MTSP_O_EXCL 0x0800
#define MTSP_O_BINARY 0x8000
-#define SP_VPE 1
+extern int tclimit;
struct apsp_table {
int sp;
/* Run the syscall at the priviledge of the user who loaded the
SP program */
- if (vpe_getuid(SP_VPE))
- sp_setfsuidgid( vpe_getuid(SP_VPE), vpe_getgid(SP_VPE));
+ if (vpe_getuid(tclimit))
+ sp_setfsuidgid(vpe_getuid(tclimit), vpe_getgid(tclimit));
switch (sc.cmd) {
/* needs the flags argument translating from SDE kit to
case MTSP_SYSCALL_EXIT:
list_for_each_entry(n, &kspd_notifylist, list)
- n->kspd_sp_exit(SP_VPE);
+ n->kspd_sp_exit(tclimit);
sp_stopping = 1;
printk(KERN_DEBUG "KSPD got exit syscall from SP exitcode %d\n",
case MTSP_SYSCALL_OPEN:
generic.arg1 = translate_open_flags(generic.arg1);
- vcwd = vpe_getcwd(SP_VPE);
+ vcwd = vpe_getcwd(tclimit);
/* change to the cwd of the process that loaded the SP program */
old_fs = get_fs();
break;
} /* switch */
- if (vpe_getuid(SP_VPE))
+ if (vpe_getuid(tclimit))
sp_setfsuidgid( 0, 0);
old_fs = get_fs();
}
INIT_WORK(&work, sp_work);
- queue_work(workqueue, &work);
- } else
- queue_work(workqueue, &work);
+ }
+ queue_work(workqueue, &work);
}
static void stopwork(int vpe)
notify.start = startwork;
notify.stop = stopwork;
- vpe_notify(SP_VPE, ¬ify);
+ vpe_notify(tclimit, ¬ify);
return 0;
}
flags);
}
+asmlinkage long sys32_fallocate(int fd, int mode, unsigned offset_a2,
+ unsigned offset_a3, unsigned len_a4, unsigned len_a5)
+{
+ return sys_fallocate(fd, mode, merge_64(offset_a2, offset_a3),
+ merge_64(len_a4, len_a5));
+}
+
save_static_function(sys32_clone);
static int noinline __used
_sys32_clone(nabi_no_regargs struct pt_regs regs)
#include <asm/page.h>
extern const unsigned char relocate_new_kernel[];
-extern const unsigned int relocate_new_kernel_size;
+extern const size_t relocate_new_kernel_size;
extern unsigned long kexec_start_address;
extern unsigned long kexec_indirection_page;
{
}
+typedef void (*noretfun_t)(void) __attribute__((noreturn));
+
void
machine_kexec(struct kimage *image)
{
(unsigned long)page_address(image->control_code_page);
kexec_start_address = image->start;
- kexec_indirection_page = phys_to_virt(image->head & PAGE_MASK);
+ kexec_indirection_page =
+ (unsigned long) phys_to_virt(image->head & PAGE_MASK);
memcpy((void*)reboot_code_buffer, relocate_new_kernel,
relocate_new_kernel_size);
phys_to_virt(entry & PAGE_MASK) : ptr + 1) {
if (*ptr & IND_SOURCE || *ptr & IND_INDIRECTION ||
*ptr & IND_DESTINATION)
- *ptr = phys_to_virt(*ptr);
+ *ptr = (unsigned long) phys_to_virt(*ptr);
}
/*
flush_icache_range(reboot_code_buffer,
reboot_code_buffer + KEXEC_CONTROL_CODE_SIZE);
- printk("Will call new kernel at %08x\n", image->start);
+ printk("Will call new kernel at %08lx\n", image->start);
printk("Bye ...\n");
flush_cache_all();
- ((void (*)(void))reboot_code_buffer)();
+ ((noretfun_t) reboot_code_buffer)();
}
cpumask_t effective_mask;
int retval;
struct task_struct *p;
+ struct thread_info *ti;
if (len < sizeof(new_mask))
return -EINVAL;
read_unlock(&tasklist_lock);
/* Compute new global allowed CPU set if necessary */
- if ((p->thread.mflags & MF_FPUBOUND)
- && cpus_intersects(new_mask, mt_fpu_cpumask)) {
+ ti = task_thread_info(p);
+ if (test_ti_thread_flag(ti, TIF_FPUBOUND) &&
+ cpus_intersects(new_mask, mt_fpu_cpumask)) {
cpus_and(effective_mask, new_mask, mt_fpu_cpumask);
retval = set_cpus_allowed(p, effective_mask);
} else {
- p->thread.mflags &= ~MF_FPUBOUND;
+ clear_ti_thread_flag(ti, TIF_FPUBOUND);
retval = set_cpus_allowed(p, new_mask);
}
-
out_unlock:
put_task_struct(p);
unlock_cpu_hotplug();
#include <asm/r4kcache.h>
#include <asm/cacheflush.h>
+int vpelimit;
+
+static int __init maxvpes(char *str)
+{
+ get_option(&str, &vpelimit);
+
+ return 1;
+}
+
+__setup("maxvpes=", maxvpes);
+
+int tclimit;
+
+static int __init maxtcs(char *str)
+{
+ get_option(&str, &tclimit);
+
+ return 1;
+}
+
+__setup("maxtcs=", maxtcs);
+
/*
* Dump new MIPS MT state for the core. Does not leave TCs halted.
* Takes an argument which taken to be a pre-call MVPControl value.
status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK);
#ifdef CONFIG_64BIT
status &= ~ST0_FR;
- status |= (current->thread.mflags & MF_32BIT_REGS) ? 0 : ST0_FR;
+ status |= test_thread_flag(TIF_32BIT_REGS) ? 0 : ST0_FR;
#endif
status |= KU_USER;
regs->cp0_status = status;
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ptrace.h>
-#include <linux/audit.h>
#include <linux/smp.h>
#include <linux/user.h>
#include <linux/security.h>
-#include <linux/signal.h>
+#include <linux/audit.h>
+#include <linux/seccomp.h>
#include <asm/byteorder.h>
#include <asm/cpu.h>
*/
asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
{
+ /* do the secure computing check first */
+ if (!entryexit)
+ secure_computing(regs->regs[0]);
+
if (unlikely(current->audit_context) && entryexit)
audit_syscall_exit(AUDITSC_RESULT(regs->regs[2]),
regs->regs[2]);
if (!(current->ptrace & PT_PTRACED))
goto out;
+
if (!test_thread_flag(TIF_SYSCALL_TRACE))
goto out;
send_sig(current->exit_code, current, 1);
current->exit_code = 0;
}
- out:
+
+out:
if (unlikely(current->audit_context) && !entryexit)
- audit_syscall_entry(audit_arch(), regs->regs[2],
+ audit_syscall_entry(audit_arch(), regs->regs[0],
regs->regs[4], regs->regs[5],
regs->regs[6], regs->regs[7]);
}
#include <asm/stackframe.h>
#include <asm/addrspace.h>
- .globl relocate_new_kernel
-relocate_new_kernel:
-
- PTR_L s0, kexec_indirection_page
- PTR_L s1, kexec_start_address
+LEAF(relocate_new_kernel)
+ PTR_L s0, kexec_indirection_page
+ PTR_L s1, kexec_start_address
process_entry:
- PTR_L s2, (s0)
- PTR_ADD s0, s0, SZREG
+ PTR_L s2, (s0)
+ PTR_ADD s0, s0, SZREG
/* destination page */
- and s3, s2, 0x1
- beq s3, zero, 1f
- and s4, s2, ~0x1 /* store destination addr in s4 */
- move a0, s4
- b process_entry
+ and s3, s2, 0x1
+ beq s3, zero, 1f
+ and s4, s2, ~0x1 /* store destination addr in s4 */
+ move a0, s4
+ b process_entry
1:
/* indirection page, update s0 */
- and s3, s2, 0x2
- beq s3, zero, 1f
- and s0, s2, ~0x2
- b process_entry
+ and s3, s2, 0x2
+ beq s3, zero, 1f
+ and s0, s2, ~0x2
+ b process_entry
1:
/* done page */
- and s3, s2, 0x4
- beq s3, zero, 1f
- b done
+ and s3, s2, 0x4
+ beq s3, zero, 1f
+ b done
1:
/* source page */
- and s3, s2, 0x8
- beq s3, zero, process_entry
- and s2, s2, ~0x8
- li s6, (1 << PAGE_SHIFT) / SZREG
+ and s3, s2, 0x8
+ beq s3, zero, process_entry
+ and s2, s2, ~0x8
+ li s6, (1 << PAGE_SHIFT) / SZREG
copy_word:
/* copy page word by word */
- REG_L s5, (s2)
- REG_S s5, (s4)
- INT_ADD s4, s4, SZREG
- INT_ADD s2, s2, SZREG
- INT_SUB s6, s6, 1
- beq s6, zero, process_entry
- b copy_word
- b process_entry
+ REG_L s5, (s2)
+ REG_S s5, (s4)
+ PTR_ADD s4, s4, SZREG
+ PTR_ADD s2, s2, SZREG
+ LONG_SUB s6, s6, 1
+ beq s6, zero, process_entry
+ b copy_word
+ b process_entry
done:
/* jump to kexec_start_address */
- j s1
+ j s1
+ END(relocate_new_kernel)
- .globl kexec_start_address
kexec_start_address:
- .long 0x0
+ EXPORT(kexec_start_address)
+ PTR 0x0
+ .size kexec_start_address, PTRSIZE
- .globl kexec_indirection_page
kexec_indirection_page:
- .long 0x0
+ EXPORT(kexec_indirection_page)
+ PTR 0
+ .size kexec_indirection_page, PTRSIZE
relocate_new_kernel_end:
- .globl relocate_new_kernel_size
relocate_new_kernel_size:
- .long relocate_new_kernel_end - relocate_new_kernel
+ EXPORT(relocate_new_kernel_size)
+ PTR relocate_new_kernel_end - relocate_new_kernel
+ .size relocate_new_kernel_size, PTRSIZE
#include <asm/atomic.h>
#include <asm/cpu.h>
#include <asm/processor.h>
+#include <asm/mips_mt.h>
#include <asm/system.h>
#include <asm/vpe.h>
#include <asm/rtlx.h>
-#define RTLX_TARG_VPE 1
-
static struct rtlx_info *rtlx;
static int major;
static char module_name[] = "rtlx";
}
if (rtlx == NULL) {
- if( (p = vpe_get_shared(RTLX_TARG_VPE)) == NULL) {
+ if( (p = vpe_get_shared(tclimit)) == NULL) {
if (can_sleep) {
__wait_event_interruptible(channel_wqs[index].lx_queue,
- (p = vpe_get_shared(RTLX_TARG_VPE)),
+ (p = vpe_get_shared(tclimit)),
ret);
if (ret)
goto out_fail;
static char register_chrdev_failed[] __initdata =
KERN_ERR "rtlx_module_init: unable to register device\n";
-static int rtlx_module_init(void)
+static int __init rtlx_module_init(void)
{
struct device *dev;
int i, err;
+ if (!cpu_has_mipsmt) {
+ printk("VPE loader: not a MIPS MT capable processor\n");
+ return -ENODEV;
+ }
+
+ if (tclimit == 0) {
+ printk(KERN_WARNING "No TCs reserved for AP/SP, not "
+ "initializing RTLX.\nPass maxtcs=<n> argument as kernel "
+ "argument\n");
+
+ return -ENODEV;
+ }
+
major = register_chrdev(0, module_name, &rtlx_fops);
if (major < 0) {
printk(register_chrdev_failed);
/* set up notifiers */
notify.start = starting;
notify.stop = stopping;
- vpe_notify(RTLX_TARG_VPE, ¬ify);
+ vpe_notify(tclimit, ¬ify);
if (cpu_has_vint)
set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch);
sys sys_signalfd 3
sys sys_timerfd 4
sys sys_eventfd 1
+ sys sys_fallocate 6 /* 4320 */
.endm
/* We pre-compute the number of _instruction_ bytes needed to
PTR sys_signalfd
PTR sys_timerfd
PTR sys_eventfd
+ PTR sys_fallocate
.size sys_call_table,.-sys_call_table
PTR compat_sys_signalfd /* 5280 */
PTR compat_sys_timerfd
PTR sys_eventfd
+ PTR sys_fallocate
.size sysn32_call_table,.-sysn32_call_table
PTR compat_sys_signalfd
PTR compat_sys_timerfd
PTR sys_eventfd
+ PTR sys_fallocate /* 4320 */
.size sys_call_table,.-sys_call_table
#include <linux/errno.h>
#include <linux/wait.h>
#include <linux/ptrace.h>
-#include <linux/compat.h>
#include <linux/suspend.h>
#include <linux/compiler.h>
#include <linux/uaccess.h>
}
}
+int smp_call_function_single(int cpu, void (*func) (void *info), void *info,
+ int retry, int wait)
+{
+ struct call_data_struct data;
+ int me;
+
+ /*
+ * Can die spectacularly if this CPU isn't yet marked online
+ */
+ if (!cpu_online(cpu))
+ return 0;
+
+ me = get_cpu();
+ BUG_ON(!cpu_online(me));
+
+ if (cpu == me) {
+ local_irq_disable();
+ func(info);
+ local_irq_enable();
+ put_cpu();
+ return 0;
+ }
+
+ /* Can deadlock when called with interrupts disabled */
+ WARN_ON(irqs_disabled());
+
+ data.func = func;
+ data.info = info;
+ atomic_set(&data.started, 0);
+ data.wait = wait;
+ if (wait)
+ atomic_set(&data.finished, 0);
+
+ spin_lock(&smp_call_lock);
+ call_data = &data;
+ smp_mb();
+
+ /* Send a message to the other CPU */
+ core_send_ipi(cpu, SMP_CALL_FUNCTION);
+
+ /* Wait for response */
+ /* FIXME: lock-up detection, backtrace on lock-up */
+ while (atomic_read(&data.started) != 1)
+ barrier();
+
+ if (wait)
+ while (atomic_read(&data.finished) != 1)
+ barrier();
+ call_data = NULL;
+ spin_unlock(&smp_call_lock);
+
+ put_cpu();
+ return 0;
+}
+
static void stop_this_cpu(void *dummy)
{
/*
/* Boot command line configuration overrides */
-static int vpelimit = 0;
-static int tclimit = 0;
static int ipibuffers = 0;
static int nostlb = 0;
static int asidmask = 0;
unsigned long smtc_asid_mask = 0xff;
-static int __init maxvpes(char *str)
-{
- get_option(&str, &vpelimit);
- return 1;
-}
-
-static int __init maxtcs(char *str)
-{
- get_option(&str, &tclimit);
- return 1;
-}
-
static int __init ipibufs(char *str)
{
get_option(&str, &ipibuffers);
return 1;
}
-__setup("maxvpes=", maxvpes);
-__setup("maxtcs=", maxtcs);
__setup("ipibufs=", ipibufs);
__setup("nostlb", stlb_disable);
__setup("asidmask=", asidmask_set);
__setup("tintq=", tintq);
-int imstuckcount[2][8];
+static int imstuckcount[2][8];
/* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
-int vpemask[2][8] = {
+static int vpemask[2][8] = {
{0, 0, 1, 0, 0, 0, 0, 1},
{0, 0, 0, 0, 0, 0, 0, 1}
};
* (unsigned long)idle->thread_info the gp
*
*/
-void smtc_boot_secondary(int cpu, struct task_struct *idle)
+void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
{
extern u32 kernelsp[NR_CPUS];
long flags;
* Send clock tick to all TCs except the one executing the funtion
*/
-void smtc_timer_broadcast(int vpe)
+void smtc_timer_broadcast(void)
{
int cpu;
int myTC = cpu_data[smp_processor_id()].tc_id;
do_IRQ(cpu_ipi_irq);
}
-static struct irqaction irq_ipi;
+static struct irqaction irq_ipi = {
+ .handler = ipi_interrupt,
+ .flags = IRQF_DISABLED,
+ .name = "SMTC_IPI",
+ .flags = IRQF_PERCPU
+};
static void setup_cross_vpe_interrupts(unsigned int nvpe)
{
set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch);
- irq_ipi.handler = ipi_interrupt;
- irq_ipi.flags = IRQF_DISABLED;
- irq_ipi.name = "SMTC_IPI";
-
setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
- irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU;
set_irq_handler(cpu_ipi_irq, handle_percpu_irq);
}
asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
{
- int tmp;
-
- switch(cmd) {
+ switch (cmd) {
case MIPS_ATOMIC_SET:
printk(KERN_CRIT "How did I get here?\n");
return -EINVAL;
case MIPS_FIXADE:
- tmp = current->thread.mflags & ~3;
- current->thread.mflags = tmp | (arg1 & 3);
+ if (arg1 & ~3)
+ return -EINVAL;
+
+ if (arg1 & 1)
+ set_thread_flag(TIF_FIXADE);
+ else
+ clear_thread_flag(TIF_FIXADE);
+ if (arg1 & 2)
+ set_thread_flag(TIF_LOGADE);
+ else
+ clear_thread_flag(TIF_FIXADE);
+
return 0;
case FLUSH_CACHE:
cpus_and(tmask, current->thread.user_cpus_allowed,
mt_fpu_cpumask);
set_cpus_allowed(current, tmask);
- current->thread.mflags |= MF_FPUBOUND;
+ set_thread_flag(TIF_FPUBOUND);
}
}
#endif /* CONFIG_MIPS_MT_FPAFF */
#endif
extern void show_registers(struct pt_regs *regs);
-static inline int emulate_load_store_insn(struct pt_regs *regs,
- void __user *addr, unsigned int __user *pc,
- unsigned long **regptr, unsigned long *newvalue)
+static void emulate_load_store_insn(struct pt_regs *regs,
+ void __user *addr, unsigned int __user *pc)
{
union mips_instruction insn;
unsigned long value;
unsigned int res;
regs->regs[0] = 0;
- *regptr=NULL;
/*
* This load never faults.
: "r" (addr), "i" (-EFAULT));
if (res)
goto fault;
- *newvalue = value;
- *regptr = ®s->regs[insn.i_format.rt];
+ compute_return_epc(regs);
+ regs->regs[insn.i_format.rt] = value;
break;
case lw_op:
: "r" (addr), "i" (-EFAULT));
if (res)
goto fault;
- *newvalue = value;
- *regptr = ®s->regs[insn.i_format.rt];
+ compute_return_epc(regs);
+ regs->regs[insn.i_format.rt] = value;
break;
case lhu_op:
: "r" (addr), "i" (-EFAULT));
if (res)
goto fault;
- *newvalue = value;
- *regptr = ®s->regs[insn.i_format.rt];
+ compute_return_epc(regs);
+ regs->regs[insn.i_format.rt] = value;
break;
case lwu_op:
: "r" (addr), "i" (-EFAULT));
if (res)
goto fault;
- *newvalue = value;
- *regptr = ®s->regs[insn.i_format.rt];
+ compute_return_epc(regs);
+ regs->regs[insn.i_format.rt] = value;
break;
#endif /* CONFIG_64BIT */
: "r" (addr), "i" (-EFAULT));
if (res)
goto fault;
- *newvalue = value;
- *regptr = ®s->regs[insn.i_format.rt];
+ compute_return_epc(regs);
+ regs->regs[insn.i_format.rt] = value;
break;
#endif /* CONFIG_64BIT */
: "r" (value), "r" (addr), "i" (-EFAULT));
if (res)
goto fault;
+ compute_return_epc(regs);
break;
case sw_op:
: "r" (value), "r" (addr), "i" (-EFAULT));
if (res)
goto fault;
+ compute_return_epc(regs);
break;
case sd_op:
: "r" (value), "r" (addr), "i" (-EFAULT));
if (res)
goto fault;
+ compute_return_epc(regs);
break;
#endif /* CONFIG_64BIT */
unaligned_instructions++;
#endif
- return 0;
+ return;
fault:
/* Did we have an exception handler installed? */
if (fixup_exception(regs))
- return 1;
+ return;
die_if_kernel ("Unhandled kernel unaligned access", regs);
send_sig(SIGSEGV, current, 1);
- return 0;
+ return;
sigbus:
die_if_kernel("Unhandled kernel unaligned access", regs);
send_sig(SIGBUS, current, 1);
- return 0;
+ return;
sigill:
die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs);
send_sig(SIGILL, current, 1);
-
- return 0;
}
asmlinkage void do_ade(struct pt_regs *regs)
{
- unsigned long *regptr, newval;
extern int do_dsemulret(struct pt_regs *);
unsigned int __user *pc;
mm_segment_t seg;
goto sigbus;
pc = (unsigned int __user *) exception_epc(regs);
- if (user_mode(regs) && (current->thread.mflags & MF_FIXADE) == 0)
+ if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
goto sigbus;
if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
goto sigbus;
seg = get_fs();
if (!user_mode(regs))
set_fs(KERNEL_DS);
- if (!emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc,
- ®ptr, &newval)) {
- compute_return_epc(regs);
- /*
- * Now that branch is evaluated, update the dest
- * register if necessary
- */
- if (regptr)
- *regptr = newval;
- }
+ emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc);
set_fs(seg);
return;
* To load and run, simply cat a SP 'program file' to /dev/vpe1.
* i.e cat spapp >/dev/vpe1.
*/
-
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/module.h>
#include <asm/system.h>
#include <asm/vpe.h>
#include <asm/kspd.h>
+#include <asm/mips_mt.h>
typedef void *vpe_handle;
/* If this is set, the section belongs in the init part of the module */
#define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1))
+/*
+ * The number of TCs and VPEs physically available on the core
+ */
+static int hw_tcs, hw_vpes;
static char module_name[] = "vpe";
static int major;
static const int minor = 1; /* fixed for now */
/* the list of who wants to know when something major happens */
struct list_head notify;
+
+ unsigned int ntcs;
};
struct tc {
enum tc_state state;
int index;
- /* parent VPE */
- struct vpe *pvpe;
-
- /* The list of TC's with this VPE */
- struct list_head tc;
-
- /* The global list of tc's */
- struct list_head list;
+ struct vpe *pvpe; /* parent VPE */
+ struct list_head tc; /* The list of TC's with this VPE */
+ struct list_head list; /* The global list of tc's */
};
struct {
/* allocate a tc. At startup only tc0 is running, all other can be halted. */
struct tc *alloc_tc(int index)
{
- struct tc *t;
+ struct tc *tc;
- if ((t = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) {
- return NULL;
- }
-
- INIT_LIST_HEAD(&t->tc);
- list_add_tail(&t->list, &vpecontrol.tc_list);
+ if ((tc = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL)
+ goto out;
- t->index = index;
+ INIT_LIST_HEAD(&tc->tc);
+ tc->index = index;
+ list_add_tail(&tc->list, &vpecontrol.tc_list);
- return t;
+out:
+ return tc;
}
/* clean up and free everything */
}
#endif
-static void dump_tc(struct tc *t)
-{
- unsigned long val;
-
- settc(t->index);
- printk(KERN_DEBUG "VPE loader: TC index %d targtc %ld "
- "TCStatus 0x%lx halt 0x%lx\n",
- t->index, read_c0_vpecontrol() & VPECONTROL_TARGTC,
- read_tc_c0_tcstatus(), read_tc_c0_tchalt());
-
- printk(KERN_DEBUG " tcrestart 0x%lx\n", read_tc_c0_tcrestart());
- printk(KERN_DEBUG " tcbind 0x%lx\n", read_tc_c0_tcbind());
-
- val = read_c0_vpeconf0();
- printk(KERN_DEBUG " VPEConf0 0x%lx MVP %ld\n", val,
- (val & VPECONF0_MVP) >> VPECONF0_MVP_SHIFT);
-
- printk(KERN_DEBUG " c0 status 0x%lx\n", read_vpe_c0_status());
- printk(KERN_DEBUG " c0 cause 0x%lx\n", read_vpe_c0_cause());
-
- printk(KERN_DEBUG " c0 badvaddr 0x%lx\n", read_vpe_c0_badvaddr());
- printk(KERN_DEBUG " c0 epc 0x%lx\n", read_vpe_c0_epc());
-}
-
-static void dump_tclist(void)
-{
- struct tc *t;
-
- list_for_each_entry(t, &vpecontrol.tc_list, list) {
- dump_tc(t);
- }
-}
-
/* We are prepared so configure and start the VPE... */
static int vpe_run(struct vpe * v)
{
+ unsigned long flags, val, dmt_flag;
struct vpe_notifications *n;
- unsigned long val, dmt_flag;
+ unsigned int vpeflags;
struct tc *t;
/* check we are the Master VPE */
+ local_irq_save(flags);
val = read_c0_vpeconf0();
if (!(val & VPECONF0_MVP)) {
printk(KERN_WARNING
"VPE loader: only Master VPE's are allowed to configure MT\n");
+ local_irq_restore(flags);
+
return -1;
}
- /* disable MT (using dvpe) */
- dvpe();
+ dmt_flag = dmt();
+ vpeflags = dvpe();
if (!list_empty(&v->tc)) {
if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) {
- printk(KERN_WARNING "VPE loader: TC %d is already in use.\n",
- t->index);
+ evpe(vpeflags);
+ emt(dmt_flag);
+ local_irq_restore(flags);
+
+ printk(KERN_WARNING
+ "VPE loader: TC %d is already in use.\n",
+ t->index);
return -ENOEXEC;
}
} else {
- printk(KERN_WARNING "VPE loader: No TC's associated with VPE %d\n",
+ evpe(vpeflags);
+ emt(dmt_flag);
+ local_irq_restore(flags);
+
+ printk(KERN_WARNING
+ "VPE loader: No TC's associated with VPE %d\n",
v->minor);
+
return -ENOEXEC;
}
/* should check it is halted, and not activated */
if ((read_tc_c0_tcstatus() & TCSTATUS_A) || !(read_tc_c0_tchalt() & TCHALT_H)) {
- printk(KERN_WARNING "VPE loader: TC %d is already doing something!\n",
+ evpe(vpeflags);
+ emt(dmt_flag);
+ local_irq_restore(flags);
+
+ printk(KERN_WARNING "VPE loader: TC %d is already active!\n",
t->index);
- dump_tclist();
+
return -ENOEXEC;
}
- /*
- * Disable multi-threaded execution whilst we activate, clear the
- * halt bit and bound the tc to the other VPE...
- */
- dmt_flag = dmt();
-
/* Write the address we want it to start running from in the TCPC register. */
write_tc_c0_tcrestart((unsigned long)v->__start);
write_tc_c0_tccontext((unsigned long)0);
+
/*
* Mark the TC as activated, not interrupt exempt and not dynamically
* allocatable
* here... Or set $a3 to zero and define DFLT_STACK_SIZE and
* DFLT_HEAP_SIZE when you compile your program
*/
- mttgpr(7, physical_memsize);
-
+ mttgpr(6, v->ntcs);
+ mttgpr(7, physical_memsize);
/* set up VPE1 */
/*
* bind the TC to VPE 1 as late as possible so we only have the final
* VPE registers to set up, and so an EJTAG probe can trigger on it
*/
- write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | v->minor);
+ write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1);
write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA));
/* take system out of configuration state */
clear_c0_mvpcontrol(MVPCONTROL_VPC);
- /* now safe to re-enable multi-threading */
- emt(dmt_flag);
-
- /* set it running */
+#ifdef CONFIG_SMP
evpe(EVPE_ENABLE);
+#else
+ evpe(vpeflags);
+#endif
+ emt(dmt_flag);
+ local_irq_restore(flags);
- list_for_each_entry(n, &v->notify, list) {
- n->start(v->minor);
- }
+ list_for_each_entry(n, &v->notify, list)
+ n->start(minor);
return 0;
}
return 0;
}
-void __used dump_vpe(struct vpe * v)
-{
- struct tc *t;
-
- settc(v->minor);
-
- printk(KERN_DEBUG "VPEControl 0x%lx\n", read_vpe_c0_vpecontrol());
- printk(KERN_DEBUG "VPEConf0 0x%lx\n", read_vpe_c0_vpeconf0());
-
- list_for_each_entry(t, &vpecontrol.tc_list, list)
- dump_tc(t);
-}
-
static void cleanup_tc(struct tc *tc)
{
+ unsigned long flags;
+ unsigned int mtflags, vpflags;
int tmp;
+ local_irq_save(flags);
+ mtflags = dmt();
+ vpflags = dvpe();
/* Put MVPE's into 'configuration state' */
set_c0_mvpcontrol(MVPCONTROL_VPC);
write_tc_c0_tchalt(TCHALT_H);
/* bind it to anything other than VPE1 */
- write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE
+// write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE
clear_c0_mvpcontrol(MVPCONTROL_VPC);
+ evpe(vpflags);
+ emt(mtflags);
+ local_irq_restore(flags);
}
static int getcwd(char *buff, int size)
/* checks VPE is unused and gets ready to load program */
static int vpe_open(struct inode *inode, struct file *filp)
{
- int minor, ret;
enum vpe_state state;
- struct vpe *v;
struct vpe_notifications *not;
+ struct vpe *v;
+ int ret;
- /* assume only 1 device at the mo. */
- if ((minor = iminor(inode)) != 1) {
+ if (minor != iminor(inode)) {
+ /* assume only 1 device at the moment. */
printk(KERN_WARNING "VPE loader: only vpe1 is supported\n");
return -ENODEV;
}
- if ((v = get_vpe(minor)) == NULL) {
+ if ((v = get_vpe(tclimit)) == NULL) {
printk(KERN_WARNING "VPE loader: unable to get vpe\n");
return -ENODEV;
}
state = xchg(&v->state, VPE_STATE_INUSE);
if (state != VPE_STATE_UNUSED) {
- dvpe();
-
printk(KERN_DEBUG "VPE loader: tc in use dumping regs\n");
- dump_tc(get_tc(minor));
-
list_for_each_entry(not, &v->notify, list) {
- not->stop(minor);
+ not->stop(tclimit);
}
release_progmem(v->load_addr);
- cleanup_tc(get_tc(minor));
+ cleanup_tc(get_tc(tclimit));
}
/* this of-course trashes what was there before... */
v->shared_ptr = NULL;
v->__start = 0;
+
return 0;
}
static int vpe_release(struct inode *inode, struct file *filp)
{
- int minor, ret = 0;
struct vpe *v;
Elf_Ehdr *hdr;
+ int ret = 0;
- minor = iminor(inode);
- if ((v = get_vpe(minor)) == NULL)
+ v = get_vpe(tclimit);
+ if (v == NULL)
return -ENODEV;
- // simple case of fire and forget, so tell the VPE to run...
-
hdr = (Elf_Ehdr *) v->pbuffer;
if (memcmp(hdr->e_ident, ELFMAG, 4) == 0) {
- if (vpe_elfload(v) >= 0)
+ if (vpe_elfload(v) >= 0) {
vpe_run(v);
- else {
+ } else {
printk(KERN_WARNING "VPE loader: ELF load failed.\n");
ret = -ENOEXEC;
}
static ssize_t vpe_write(struct file *file, const char __user * buffer,
size_t count, loff_t * ppos)
{
- int minor;
size_t ret = count;
struct vpe *v;
- minor = iminor(file->f_path.dentry->d_inode);
- if ((v = get_vpe(minor)) == NULL)
+ if (iminor(file->f_path.dentry->d_inode) != minor)
+ return -ENODEV;
+
+ v = get_vpe(tclimit);
+ if (v == NULL)
return -ENODEV;
if (v->pbuffer == NULL) {
}
#endif
-static struct device *vpe_dev;
+static ssize_t store_kill(struct class_device *dev, const char *buf, size_t len)
+{
+ struct vpe *vpe = get_vpe(tclimit);
+ struct vpe_notifications *not;
+
+ list_for_each_entry(not, &vpe->notify, list) {
+ not->stop(tclimit);
+ }
+
+ release_progmem(vpe->load_addr);
+ cleanup_tc(get_tc(tclimit));
+ vpe_stop(vpe);
+ vpe_free(vpe);
+
+ return len;
+}
+
+static ssize_t show_ntcs(struct class_device *cd, char *buf)
+{
+ struct vpe *vpe = get_vpe(tclimit);
+
+ return sprintf(buf, "%d\n", vpe->ntcs);
+}
+
+static ssize_t store_ntcs(struct class_device *dev, const char *buf, size_t len)
+{
+ struct vpe *vpe = get_vpe(tclimit);
+ unsigned long new;
+ char *endp;
+
+ new = simple_strtoul(buf, &endp, 0);
+ if (endp == buf)
+ goto out_einval;
+
+ if (new == 0 || new > (hw_tcs - tclimit))
+ goto out_einval;
+
+ vpe->ntcs = new;
+
+ return len;
+
+out_einval:
+ return -EINVAL;;
+}
+
+static struct class_device_attribute vpe_class_attributes[] = {
+ __ATTR(kill, S_IWUSR, NULL, store_kill),
+ __ATTR(ntcs, S_IRUGO | S_IWUSR, show_ntcs, store_ntcs),
+ {}
+};
+
+static void vpe_class_device_release(struct class_device *cd)
+{
+ kfree(cd);
+}
+
+struct class vpe_class = {
+ .name = "vpe",
+ .owner = THIS_MODULE,
+ .release = vpe_class_device_release,
+ .class_dev_attrs = vpe_class_attributes,
+};
+
+struct class_device vpe_device;
static int __init vpe_module_init(void)
{
+ unsigned int mtflags, vpflags;
+ unsigned long flags, val;
struct vpe *v = NULL;
- struct device *dev;
struct tc *t;
- unsigned long val;
- int i, err;
+ int tc, err;
if (!cpu_has_mipsmt) {
printk("VPE loader: not a MIPS MT capable processor\n");
return -ENODEV;
}
+ if (vpelimit == 0) {
+ printk(KERN_WARNING "No VPEs reserved for AP/SP, not "
+ "initializing VPE loader.\nPass maxvpes=<n> argument as "
+ "kernel argument\n");
+
+ return -ENODEV;
+ }
+
+ if (tclimit == 0) {
+ printk(KERN_WARNING "No TCs reserved for AP/SP, not "
+ "initializing VPE loader.\nPass maxtcs=<n> argument as "
+ "kernel argument\n");
+
+ return -ENODEV;
+ }
+
major = register_chrdev(0, module_name, &vpe_fops);
if (major < 0) {
printk("VPE loader: unable to register character device\n");
return major;
}
- dev = device_create(mt_class, NULL, MKDEV(major, minor),
- "tc%d", minor);
- if (IS_ERR(dev)) {
- err = PTR_ERR(dev);
+ err = class_register(&vpe_class);
+ if (err) {
+ printk(KERN_ERR "vpe_class registration failed\n");
goto out_chrdev;
}
- vpe_dev = dev;
- dmt();
- dvpe();
+ class_device_initialize(&vpe_device);
+ vpe_device.class = &vpe_class,
+ vpe_device.parent = NULL,
+ strlcpy(vpe_device.class_id, "vpe1", BUS_ID_SIZE);
+ vpe_device.devt = MKDEV(major, minor);
+ err = class_device_add(&vpe_device);
+ if (err) {
+ printk(KERN_ERR "Adding vpe_device failed\n");
+ goto out_class;
+ }
+
+ local_irq_save(flags);
+ mtflags = dmt();
+ vpflags = dvpe();
/* Put MVPE's into 'configuration state' */
set_c0_mvpcontrol(MVPCONTROL_VPC);
/* dump_mtregs(); */
-
val = read_c0_mvpconf0();
- for (i = 0; i < ((val & MVPCONF0_PTC) + 1); i++) {
- t = alloc_tc(i);
+ hw_tcs = (val & MVPCONF0_PTC) + 1;
+ hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
+
+ for (tc = tclimit; tc < hw_tcs; tc++) {
+ /*
+ * Must re-enable multithreading temporarily or in case we
+ * reschedule send IPIs or similar we might hang.
+ */
+ clear_c0_mvpcontrol(MVPCONTROL_VPC);
+ evpe(vpflags);
+ emt(mtflags);
+ local_irq_restore(flags);
+ t = alloc_tc(tc);
+ if (!t) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ local_irq_save(flags);
+ mtflags = dmt();
+ vpflags = dvpe();
+ set_c0_mvpcontrol(MVPCONTROL_VPC);
/* VPE's */
- if (i < ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1) {
- settc(i);
+ if (tc < hw_tcs) {
+ settc(tc);
- if ((v = alloc_vpe(i)) == NULL) {
+ if ((v = alloc_vpe(tc)) == NULL) {
printk(KERN_WARNING "VPE: unable to allocate VPE\n");
- return -ENODEV;
+
+ goto out_reenable;
}
+ v->ntcs = hw_tcs - tclimit;
+
/* add the tc to the list of this vpe's tc's. */
list_add(&t->tc, &v->tc);
/* deactivate all but vpe0 */
- if (i != 0) {
+ if (tc >= tclimit) {
unsigned long tmp = read_vpe_c0_vpeconf0();
tmp &= ~VPECONF0_VPA;
/* disable multi-threading with TC's */
write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
- if (i != 0) {
+ if (tc >= vpelimit) {
/*
* Set config to be the same as vpe0,
* particularly kseg0 coherency alg
/* TC's */
t->pvpe = v; /* set the parent vpe */
- if (i != 0) {
+ if (tc >= tclimit) {
unsigned long tmp;
- settc(i);
+ settc(tc);
/* Any TC that is bound to VPE0 gets left as is - in case
we are running SMTC on VPE0. A TC that is bound to any
}
}
+out_reenable:
/* release config state */
clear_c0_mvpcontrol(MVPCONTROL_VPC);
+ evpe(vpflags);
+ emt(mtflags);
+ local_irq_restore(flags);
+
#ifdef CONFIG_MIPS_APSP_KSPD
kspd_events.kspd_sp_exit = kspd_sp_exit;
#endif
return 0;
+out_class:
+ class_unregister(&vpe_class);
out_chrdev:
unregister_chrdev(major, module_name);
+out:
return err;
}
}
}
- device_destroy(mt_class, MKDEV(major, minor));
+ class_device_del(&vpe_device);
unregister_chrdev(major, module_name);
}
#
obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o
-EXTRA_AFLAGS := $(CFLAGS)
+EXTRA_AFLAGS := $(CFLAGS)
+EXTRA_CFLAGS += -Werror
*/
#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/irq.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
* option) any later version.
*/
#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
#include <linux/bootmem.h>
-
-#include <asm/addrspace.h>
#include <asm/bootinfo.h>
extern unsigned long bus_clock;
-extern unsigned long cpu_clock;
+extern unsigned long cpu_clock_freq;
extern unsigned int memsize, highmemsize;
extern int putDebugChar(unsigned char byte);
l = (long)*env;
while (l != 0) {
parse_even_earlier(bus_clock, "busclock", l);
- parse_even_earlier(cpu_clock, "cpuclock", l);
+ parse_even_earlier(cpu_clock_freq, "cpuclock", l);
parse_even_earlier(memsize, "memsize", l);
parse_even_earlier(highmemsize, "highmemsize", l);
env++;
memsize = 256;
pr_info("busclock=%ld, cpuclock=%ld,memsize=%d,highmemsize=%d\n",
- bus_clock, cpu_clock, memsize, highmemsize);
+ bus_clock, cpu_clock_freq, memsize, highmemsize);
}
void __init prom_free_prom_memory(void)
*/
#include <linux/bootmem.h>
#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/mc146818rtc.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/tty.h>
-#include <linux/types.h>
#include <asm/bootinfo.h>
#include <asm/mc146818-time.h>
#define PTR_PAD(p) (p)
#endif
-unsigned long cpu_clock;
+unsigned long cpu_clock_freq;
unsigned long bus_clock;
unsigned int memsize;
unsigned int highmemsize = 0;
static void __init loongson2e_time_init(void)
{
/* setup mips r4k timer */
- mips_hpt_frequency = cpu_clock / 2;
+ mips_hpt_frequency = cpu_clock_freq / 2;
}
static unsigned long __init mips_rtc_get_time(void)
sp_div.o sp_mul.o sp_sub.o sp_add.o sp_fdp.o sp_cmp.o sp_logb.o \
sp_scalb.o sp_simple.o sp_tint.o sp_fint.o sp_tlong.o sp_flong.o \
dp_sqrt.o sp_sqrt.o kernel_linkage.o dsemul.o
+
+EXTRA_CFLAGS += -Werror
obj-y := atlas_int.o atlas_setup.o
obj-$(CONFIG_KGDB) += atlas_gdb.o
+
+EXTRA_CFLAGS += -Werror
case MIPS_REVISION_CORID_CORE_MSC:
case MIPS_REVISION_CORID_CORE_FPGA2:
case MIPS_REVISION_CORID_CORE_FPGA3:
+ case MIPS_REVISION_CORID_CORE_FPGA4:
case MIPS_REVISION_CORID_CORE_24K:
case MIPS_REVISION_CORID_CORE_EMUL_MSC:
if (cpu_has_veic)
obj-$(CONFIG_EARLY_PRINTK) += console.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_KGDB) += gdb_hook.o
+
+EXTRA_CFLAGS += -Werror
case MIPS_REVISION_CORID_CORE_MSC:
case MIPS_REVISION_CORID_CORE_FPGA2:
case MIPS_REVISION_CORID_CORE_FPGA3:
+ case MIPS_REVISION_CORID_CORE_FPGA4:
case MIPS_REVISION_CORID_CORE_24K:
case MIPS_REVISION_CORID_CORE_EMUL_MSC:
mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;
static int mips_cpu_timer_irq;
extern int cp0_perfcount_irq;
-extern void smtc_timer_broadcast(int);
+extern void smtc_timer_broadcast(void);
static void mips_timer_dispatch(void)
{
(mips_hpt_frequency/HZ));
local_timer_interrupt(irq, dev_id);
}
- smtc_timer_broadcast(cpu_data[cpu].vpe_id);
+ smtc_timer_broadcast();
}
#else /* CONFIG_MIPS_MT_SMTC */
int r2 = cpu_has_mips_r2;
obj-$(CONFIG_MTD) += malta_mtd.o
obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o
+
+EXTRA_CFLAGS += -Werror
(0x100 << MIPSCPU_INT_I8259A));
setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
&corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
+ /*
+ * Temporary hack to ensure that the subsidiary device
+ * interrupts coing in via the i8259A, but associated
+ * with low IRQ numbers, will restore the Status.IM
+ * value associated with the i8259A.
+ */
+ {
+ int i;
+
+ for (i = 0; i < 16; i++)
+ irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
+ }
#else /* Not SMTC */
setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
* but it may be multithreaded.
*/
-void plat_smp_setup(void)
+void __cpuinit plat_smp_setup(void)
{
if (read_c0_config3() & (1<<2))
mipsmt_build_cpu_map(0);
#
obj-y := sead_int.o sead_setup.o
+
+EXTRA_CFLAGS += -Werror
obj-$(CONFIG_EARLY_PRINTK) += sim_console.o
obj-$(CONFIG_SMP) += sim_smp.o
+
+EXTRA_CFLAGS += -Werror
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/ioport.h>
-#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
+
+EXTRA_CFLAGS += -Werror
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/r4kcache.h>
+#include <asm/sections.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
#include <asm/war.h>
*/
static int __init probe_scache(void)
{
- extern unsigned long stext;
unsigned long flags, addr, begin, end, pow2;
unsigned int config = read_c0_config();
struct cpuinfo_mips *c = ¤t_cpu_data;
if (config & CONF_SC)
return 0;
- begin = (unsigned long) &stext;
+ begin = (unsigned long) &_stext;
begin &= ~((4 * 1024 * 1024) - 1);
end = begin + (4 * 1024 * 1024);
static irqreturn_t rm9000_perfcount_handler(int irq, void * dev_id)
{
unsigned int control = read_c0_perfcontrol();
+ struct pt_regs *regs = get_irq_regs();
uint32_t counter1, counter2;
uint64_t counters;
# These are still pretty much in the old state, watch, go blind.
#
obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
-obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o
obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
-obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o
+++ /dev/null
-/*
- *
- * BRIEF MODULE DESCRIPTION
- * Board specific pci fixups.
- *
- * Copyright 2001, 2002, 2003 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-static void ddb5477_fixup(struct pci_dev *dev)
-{
- u8 old;
-
- printk(KERN_NOTICE "Enabling ALI M1533/35 PS2 keyboard/mouse.\n");
- pci_read_config_byte(dev, 0x41, &old);
- pci_write_config_byte(dev, 0x41, old | 0xd0);
-}
-
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533,
- ddb5477_fixup);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1535,
- ddb5477_fixup);
-
-/*
- * Fixup baseboard AMD chip so that tx does not underflow.
- * bcr_18 |= 0x0800
- * This sets NOUFLO bit which makes tx not start until whole pkt
- * is fetched to the chip.
- */
-#define PCNET32_WIO_RDP 0x10
-#define PCNET32_WIO_RAP 0x12
-#define PCNET32_WIO_RESET 0x14
-#define PCNET32_WIO_BDP 0x16
-
-static void ddb5477_amd_lance_fixup(struct pci_dev *dev)
-{
- unsigned long ioaddr;
- u16 temp;
-
- ioaddr = pci_resource_start(dev, 0);
-
- inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */
-
- /* bcr_18 |= 0x0800 */
- outw(18, ioaddr + PCNET32_WIO_RAP);
- temp = inw(ioaddr + PCNET32_WIO_BDP);
- temp |= 0x0800;
- outw(18, ioaddr + PCNET32_WIO_RAP);
- outw(temp, ioaddr + PCNET32_WIO_BDP);
-}
-
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE,
- ddb5477_amd_lance_fixup);
+++ /dev/null
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * arch/mips/gt64120/momenco_ocelot/pci.c
- * Board-specific PCI routines for gt64120 controller.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/pci.h>
-
-
-void __devinit pcibios_fixup_bus(struct pci_bus *bus)
-{
- struct pci_bus *current_bus = bus;
- struct pci_dev *devices;
- struct list_head *devices_link;
- u16 cmd;
-
- list_for_each(devices_link, &(current_bus->devices)) {
-
- devices = pci_dev_b(devices_link);
- if (devices == NULL)
- continue;
-
- if (PCI_SLOT(devices->devfn) == 1) {
- /*
- * Slot 1 is primary ether port, i82559
- * we double-check against that assumption
- */
- if ((devices->vendor != 0x8086) ||
- (devices->device != 0x1209)) {
- panic("pcibios_fixup_bus: found "
- "unexpected PCI device in slot 1.");
- }
- devices->irq = 2; /* irq_nr is 2 for INT0 */
- } else if (PCI_SLOT(devices->devfn) == 2) {
- /*
- * Slot 2 is secondary ether port, i21143
- * we double-check against that assumption
- */
- if ((devices->vendor != 0x1011) ||
- (devices->device != 0x19)) {
- panic("galileo_pcibios_fixup_bus: "
- "found unexpected PCI device in slot 2.");
- }
- devices->irq = 3; /* irq_nr is 3 for INT1 */
- } else if (PCI_SLOT(devices->devfn) == 4) {
- /* PMC Slot 1 */
- devices->irq = 8; /* irq_nr is 8 for INT6 */
- } else if (PCI_SLOT(devices->devfn) == 5) {
- /* PMC Slot 1 */
- devices->irq = 9; /* irq_nr is 9 for INT7 */
- } else {
- /* We don't have assign interrupts for other devices. */
- devices->irq = 0xff;
- }
-
- /* Assign an interrupt number for the device */
- bus->ops->write_byte(devices, PCI_INTERRUPT_LINE,
- devices->irq);
-
- /* enable master */
- bus->ops->read_word(devices, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_MASTER;
- bus->ops->write_word(devices, PCI_COMMAND, cmd);
- }
-}
TX4927_IRQ_IOC_PCIC}
};
-int pci_get_irq(struct pci_dev *dev, int pin)
+static int pci_get_irq(const struct pci_dev *dev, int pin)
{
unsigned char irq = pin;
extern struct pci_controller tx4938_pci_controller[];
-int pci_get_irq(struct pci_dev *dev, int pin)
+static int pci_get_irq(const struct pci_dev *dev, int pin)
{
int irq = pin;
u8 slot = PCI_SLOT(dev->devfn);
+++ /dev/null
-/***********************************************************************
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * arch/mips/ddb5xxx/ddb5477/pci_ops.c
- * Define the pci_ops for DB5477.
- *
- * Much of the code is derived from the original DDB5074 port by
- * Geert Uytterhoeven <geert@sonycom.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- ***********************************************************************
- */
-
-/*
- * DDB5477 has two PCI channels, external PCI and IOPIC (internal)
- * Therefore we provide two sets of pci_ops.
- */
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-#include <asm/addrspace.h>
-#include <asm/debug.h>
-
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-/*
- * config_swap structure records what set of pdar/pmr are used
- * to access pci config space. It also provides a place hold the
- * original values for future restoring.
- */
-struct pci_config_swap {
- u32 pdar;
- u32 pmr;
- u32 config_base;
- u32 config_size;
- u32 pdar_backup;
- u32 pmr_backup;
-};
-
-/*
- * On DDB5477, we have two sets of swap registers, for ext PCI and IOPCI.
- */
-struct pci_config_swap ext_pci_swap = {
- DDB_PCIW0,
- DDB_PCIINIT00,
- DDB_PCI0_CONFIG_BASE,
- DDB_PCI0_CONFIG_SIZE
-};
-struct pci_config_swap io_pci_swap = {
- DDB_IOPCIW0,
- DDB_PCIINIT01,
- DDB_PCI1_CONFIG_BASE,
- DDB_PCI1_CONFIG_SIZE
-};
-
-
-/*
- * access config space
- */
-static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */
- u32 slot_num)
-{
- u32 pci_addr = 0;
- u32 pciinit_offset = 0;
- u32 virt_addr;
- u32 option;
-
- /* minimum pdar (window) size is 2MB */
- db_assert(swap->config_size >= (2 << 20));
-
- db_assert(slot_num < (1 << 5));
- db_assert(bus < (1 << 8));
-
- /* backup registers */
- swap->pdar_backup = ddb_in32(swap->pdar);
- swap->pmr_backup = ddb_in32(swap->pmr);
-
- /* set the pdar (pci window) register */
- ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */
- 0, /* not on local memory bus */
- 0); /* not visible from PCI bus (N/A) */
-
- /*
- * calcuate the absolute pci config addr;
- * according to the spec, we start scanning from adr:11 (0x800)
- */
- if (bus == 0) {
- /* type 0 config */
- pci_addr = 0x800 << slot_num;
- } else {
- /* type 1 config */
- pci_addr = (bus << 16) | (slot_num << 11);
- }
-
- /*
- * if pci_addr is less than pci config window size, we set
- * pciinit_offset to 0 and adjust the virt_address.
- * Otherwise we will try to adjust pciinit_offset.
- */
- if (pci_addr < swap->config_size) {
- virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
- pciinit_offset = 0;
- } else {
- db_assert((pci_addr & (swap->config_size - 1)) == 0);
- virt_addr = KSEG1ADDR(swap->config_base);
- pciinit_offset = pci_addr;
- }
-
- /* set the pmr register */
- option = DDB_PCI_ACCESS_32;
- if (bus != 0)
- option |= DDB_PCI_CFGTYPE1;
- ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
-
- return virt_addr;
-}
-
-static inline void ddb_close_config_base(struct pci_config_swap *swap)
-{
- ddb_out32(swap->pdar, swap->pdar_backup);
- ddb_out32(swap->pmr, swap->pmr_backup);
-}
-
-static int read_config_dword(struct pci_config_swap *swap,
- struct pci_bus *bus, u32 devfn, u32 where,
- u32 * val)
-{
- u32 bus_num, slot_num, func_num;
- u32 base;
-
- db_assert((where & 3) == 0);
- db_assert(where < (1 << 8));
-
- /* check if the bus is top-level */
- if (bus->parent != NULL) {
- bus_num = bus->number;
- db_assert(bus_num != 0);
- } else {
- bus_num = 0;
- }
-
- slot_num = PCI_SLOT(devfn);
- func_num = PCI_FUNC(devfn);
- base = ddb_access_config_base(swap, bus_num, slot_num);
- *val = *(volatile u32 *) (base + (func_num << 8) + where);
- ddb_close_config_base(swap);
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int read_config_word(struct pci_config_swap *swap,
- struct pci_bus *bus, u32 devfn, u32 where,
- u16 * val)
-{
- int status;
- u32 result;
-
- db_assert((where & 1) == 0);
-
- status = read_config_dword(swap, bus, devfn, where & ~3, &result);
- if (where & 2)
- result >>= 16;
- *val = result & 0xffff;
- return status;
-}
-
-static int read_config_byte(struct pci_config_swap *swap,
- struct pci_bus *bus, u32 devfn, u32 where,
- u8 * val)
-{
- int status;
- u32 result;
-
- status = read_config_dword(swap, bus, devfn, where & ~3, &result);
- if (where & 1)
- result >>= 8;
- if (where & 2)
- result >>= 16;
- *val = result & 0xff;
-
- return status;
-}
-
-static int write_config_dword(struct pci_config_swap *swap,
- struct pci_bus *bus, u32 devfn, u32 where,
- u32 val)
-{
- u32 bus_num, slot_num, func_num;
- u32 base;
-
- db_assert((where & 3) == 0);
- db_assert(where < (1 << 8));
-
- /* check if the bus is top-level */
- if (bus->parent != NULL) {
- bus_num = bus->number;
- db_assert(bus_num != 0);
- } else {
- bus_num = 0;
- }
-
- slot_num = PCI_SLOT(devfn);
- func_num = PCI_FUNC(devfn);
- base = ddb_access_config_base(swap, bus_num, slot_num);
- *(volatile u32 *) (base + (func_num << 8) + where) = val;
- ddb_close_config_base(swap);
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int write_config_word(struct pci_config_swap *swap,
- struct pci_bus *bus, u32 devfn, u32 where, u16 val)
-{
- int status, shift = 0;
- u32 result;
-
- db_assert((where & 1) == 0);
-
- status = read_config_dword(swap, bus, devfn, where & ~3, &result);
- if (status != PCIBIOS_SUCCESSFUL)
- return status;
-
- if (where & 2)
- shift += 16;
- result &= ~(0xffff << shift);
- result |= val << shift;
- return write_config_dword(swap, bus, devfn, where & ~3, result);
-}
-
-static int write_config_byte(struct pci_config_swap *swap,
- struct pci_bus *bus, u32 devfn, u32 where, u8 val)
-{
- int status, shift = 0;
- u32 result;
-
- status = read_config_dword(swap, bus, devfn, where & ~3, &result);
- if (status != PCIBIOS_SUCCESSFUL)
- return status;
-
- if (where & 2)
- shift += 16;
- if (where & 1)
- shift += 8;
- result &= ~(0xff << shift);
- result |= val << shift;
- return write_config_dword(swap, bus, devfn, where & ~3, result);
-}
-
-#define MAKE_PCI_OPS(prefix, rw, pciswap, star) \
-static int prefix##_##rw##_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 star val) \
-{ \
- if (size == 1) \
- return rw##_config_byte(pciswap, bus, devfn, where, (u8 star)val); \
- else if (size == 2) \
- return rw##_config_word(pciswap, bus, devfn, where, (u16 star)val); \
- /* Size must be 4 */ \
- return rw##_config_dword(pciswap, bus, devfn, where, val); \
-}
-
-MAKE_PCI_OPS(extpci, read, &ext_pci_swap, *)
-MAKE_PCI_OPS(extpci, write, &ext_pci_swap,)
-
-MAKE_PCI_OPS(iopci, read, &io_pci_swap, *)
-MAKE_PCI_OPS(iopci, write, &io_pci_swap,)
-
-struct pci_ops ddb5477_ext_pci_ops = {
- .read = extpci_read_config,
- .write = extpci_write_config
-};
-
-
-struct pci_ops ddb5477_io_pci_ops = {
- .read = iopci_read_config,
- .write = iopci_write_config
-};
/* check if the bus is top-level */
if (bus->parent != NULL) {
*bus_num = bus->number;
- db_assert(bus_num != 0);
+ db_assert(bus_num != NULL);
} else
*bus_num = 0;
unsigned int data = 0;
int err;
- if (bus == 0)
+ if (bus == NULL)
return -1;
err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
unsigned int data = 0;
int err;
- if (bus == 0)
+ if (bus == NULL)
return -1;
if (where & 0x01)
read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
{
int err;
- if (bus == 0)
+ if (bus == NULL)
return -1;
if (where & 0x03)
unsigned int data = (unsigned int)val;
int err;
- if (bus == 0)
+ if (bus == NULL)
return -1;
switch (where & 0x03) {
unsigned int data = (unsigned int)val;
int err;
- if (bus == 0)
+ if (bus == NULL)
return -1;
if (where & 0x01)
write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
{
int err;
- if (bus == 0)
+ if (bus == NULL)
return -1;
if (where & 0x03)
+++ /dev/null
-/*
- * PCI code for DDB5477.
- *
- * Copyright (C) 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-
-#include <asm/bootinfo.h>
-#include <asm/debug.h>
-
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-static struct resource extpci_io_resource = {
- .start = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
- .end = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
- .name = "ext pci IO space",
- .flags = IORESOURCE_IO
-};
-
-static struct resource extpci_mem_resource = {
- .start = DDB_PCI0_MEM_BASE + 0x100000,
- .end = DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
- .name = "ext pci memory space",
- .flags = IORESOURCE_MEM
-};
-
-static struct resource iopci_io_resource = {
- .start = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
- .end = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
- .name = "io pci IO space",
- .flags = IORESOURCE_IO
-};
-
-static struct resource iopci_mem_resource = {
- .start = DDB_PCI1_MEM_BASE,
- .end = DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
- .name = "ext pci memory space",
- .flags = IORESOURCE_MEM
-};
-
-extern struct pci_ops ddb5477_ext_pci_ops;
-extern struct pci_ops ddb5477_io_pci_ops;
-
-struct pci_controller ddb5477_ext_controller = {
- .pci_ops = &ddb5477_ext_pci_ops,
- .io_resource = &extpci_io_resource,
- .mem_resource = &extpci_mem_resource
-};
-
-struct pci_controller ddb5477_io_controller = {
- .pci_ops = &ddb5477_io_pci_ops,
- .io_resource = &iopci_io_resource,
- .mem_resource = &iopci_mem_resource
-};
-
-
-
-/*
- * we fix up irqs based on the slot number.
- * The first entry is at AD:11.
- * Fortunately this works because, although we have two pci buses,
- * they all have different slot numbers (except for rockhopper slot 20
- * which is handled below).
- *
- */
-
-/*
- * irq mapping : device -> pci int # -> vrc4377 irq# ,
- * ddb5477 board manual page 4 and vrc5477 manual page 46
- */
-
-/*
- * based on ddb5477 manual page 11
- */
-#define MAX_SLOT_NUM 21
-static unsigned char irq_map[MAX_SLOT_NUM] = {
- /* SLOT: 0, AD:11 */ 0xff,
- /* SLOT: 1, AD:12 */ 0xff,
- /* SLOT: 2, AD:13 */ 0xff,
- /* SLOT: 3, AD:14 */ 0xff,
- /* SLOT: 4, AD:15 */ VRC5477_IRQ_INTA, /* onboard tulip */
- /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTB, /* slot 1 */
- /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTC, /* slot 2 */
- /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 3 */
- /* SLOT: 8, AD:19 */ VRC5477_IRQ_INTE, /* slot 4 */
- /* SLOT: 9, AD:20 */ 0xff,
- /* SLOT: 10, AD:21 */ 0xff,
- /* SLOT: 11, AD:22 */ 0xff,
- /* SLOT: 12, AD:23 */ 0xff,
- /* SLOT: 13, AD:24 */ 0xff,
- /* SLOT: 14, AD:25 */ 0xff,
- /* SLOT: 15, AD:26 */ 0xff,
- /* SLOT: 16, AD:27 */ 0xff,
- /* SLOT: 17, AD:28 */ 0xff,
- /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
- /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
- /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
-};
-static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = {
- /* SLOT: 0, AD:11 */ 0xff,
- /* SLOT: 1, AD:12 */ VRC5477_IRQ_INTB, /* onboard AMD PCNET */
- /* SLOT: 2, AD:13 */ 0xff,
- /* SLOT: 3, AD:14 */ 0xff,
- /* SLOT: 4, AD:15 */ 14, /* M5229 ide ISA irq */
- /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTD, /* slot 3 */
- /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTA, /* slot 4 */
- /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 5 */
- /* SLOT: 8, AD:19 */ 0, /* M5457 modem nop */
- /* SLOT: 9, AD:20 */ VRC5477_IRQ_INTA, /* slot 2 */
- /* SLOT: 10, AD:21 */ 0xff,
- /* SLOT: 11, AD:22 */ 0xff,
- /* SLOT: 12, AD:23 */ 0xff,
- /* SLOT: 13, AD:24 */ 0xff,
- /* SLOT: 14, AD:25 */ 0xff,
- /* SLOT: 15, AD:26 */ 0xff,
- /* SLOT: 16, AD:27 */ 0xff,
- /* SLOT: 17, AD:28 */ 0, /* M7101 PMU nop */
- /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
- /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
- /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
-};
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int slot_num;
- unsigned char *slot_irq_map;
- unsigned char irq;
-
- /*
- * We ignore the swizzled slot and pin values. The original
- * pci_fixup_irq() codes largely base irq number on the dev slot
- * numbers because except for one case they are unique even
- * though there are multiple pci buses.
- */
-
- if (mips_machtype == MACH_NEC_ROCKHOPPERII)
- slot_irq_map = rockhopperII_irq_map;
- else
- slot_irq_map = irq_map;
-
- slot_num = PCI_SLOT(dev->devfn);
- irq = slot_irq_map[slot_num];
-
- db_assert(slot_num < MAX_SLOT_NUM);
-
- db_assert(irq != 0xff);
-
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
-
- if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
- /* hack to distinquish overlapping slot 20s, one
- * on bus 0 (ALI USB on the M1535 on the backplane),
- * and one on bus 2 (NEC USB controller on the CPU board)
- * Make the M1535 USB - ISA IRQ number 9.
- */
- if (slot_num == 20 && dev->bus->number == 0) {
- pci_write_config_byte(dev,
- PCI_INTERRUPT_LINE,
- 9);
- irq = 9;
- }
-
- }
-
- return irq;
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
-
-void ddb_pci_reset_bus(void)
-{
- u32 temp;
-
- /*
- * I am not sure about the "official" procedure, the following
- * steps work as far as I know:
- * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
- * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
- * The same is true for both PCI channels.
- */
- temp = ddb_in32(DDB_PCICTL0_H);
- temp |= 0x80000000;
- ddb_out32(DDB_PCICTL0_H, temp);
- temp &= ~0xc0000000;
- ddb_out32(DDB_PCICTL0_H, temp);
-
- temp = ddb_in32(DDB_PCICTL1_H);
- temp |= 0x80000000;
- ddb_out32(DDB_PCICTL1_H, temp);
- temp &= ~0xc0000000;
- ddb_out32(DDB_PCICTL1_H, temp);
-}
+++ /dev/null
-/*
- * BRIEF MODULE DESCRIPTION
- * Galileo Evaluation Boards PCI support.
- *
- * The general-purpose functions to read/write and configure the GT64120A's
- * PCI registers (function names start with pci0 or pci1) are either direct
- * copies of functions written by Galileo Technology, or are modifications
- * of their functions to work with Linux 2.4 vs Linux 2.2. These functions
- * are Copyright - Galileo Technology.
- *
- * Other functions are derived from other MIPS PCI implementations, or were
- * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc.
- * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/cache.h>
-#include <asm/pci.h>
-#include <asm/io.h>
-#include <asm/gt64120.h>
-
-static inline unsigned int pci0ReadConfigReg(unsigned int offset)
-{
- unsigned int DataForRegCf8;
- unsigned int data;
-
- DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
- (PCI_FUNC(device->devfn) << 8) |
- (offset & ~0x3)) | 0x80000000;
- GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
- GT_READ(GT_PCI0_CFGDATA_OFS, &data);
-
- return data;
-}
-
-static inline void pci0WriteConfigReg(unsigned int offset, unsigned int data)
-{
- unsigned int DataForRegCf8;
-
- DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
- (PCI_FUNC(device->devfn) << 8) |
- (offset & ~0x3)) | 0x80000000;
- GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
- GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
-}
-
-static struct resource ocelot_mem_resource = {
- .start = GT_PCI_MEM_BASE,
- .end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1,
-};
-
-static struct resource ocelot_io_resource = {
- .start = GT_PCI_IO_BASE,
- .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
-};
-
-static struct pci_controller ocelot_pci_controller = {
- .pci_ops = gt64xxx_pci0_ops,
- .mem_resource = &ocelot_mem_resource,
- .io_resource = &ocelot_io_resource,
-};
-
-static int __init ocelot_pcibios_init(void)
-{
- u32 tmp;
-
- GT_READ(GT_PCI0_CMD_OFS, &tmp);
- GT_READ(GT_PCI0_BARE_OFS, &tmp);
-
- /*
- * You have to enable bus mastering to configure any other
- * card on the bus.
- */
- tmp = pci0ReadConfigReg(PCI_COMMAND);
- tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
- pci0WriteConfigReg(PCI_COMMAND, tmp);
-
- register_pci_controller(&ocelot_pci_controller);
-}
-
-arch_initcall(ocelot_pcibios_init);
obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_KGDB) += gdb_hook.o
+
+EXTRA_CFLAGS += -Werror
# Makefile for the PMC-Sierra Titan
#
-obj-y += irq.o i2c-yosemite.o prom.o py-console.o setup.o
+obj-y += irq.o prom.o py-console.o setup.o
obj-$(CONFIG_KGDB) += dbg_io.o
obj-$(CONFIG_SMP) += smp.o
+
+EXTRA_CFLAGS += -Werror
+++ /dev/null
-/*
- * Copyright (C) 2003 PMC-Sierra Inc.
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Detailed Description:
- *
- * This block implements the I2C interface to the slave devices like the
- * Atmel 24C32 EEPROM and the MAX 1619 Sensors device. The I2C Master interface
- * can be controlled by the SCMB block. And the SCMB block kicks in only when
- * using the Ethernet Mode of operation and __not__ the SysAD mode
- *
- * The SCMB controls the two modes: MDIO and the I2C. The MDIO mode is used to
- * communicate with the Quad-PHY from Marvel. The I2C is used to communicate
- * with the I2C slave devices. It seems that the driver does not explicitly
- * deal with the control of SDA and SCL serial lines. So, the driver will set
- * the slave address, drive the command and then the data. The SCMB will then
- * control the two serial lines as required.
- *
- * It seems the documents are very unclear abt this. Hence, I took some time
- * out to write the desciption to have an idea of how the I2C can actually
- * work. Currently, this Linux driver wont be integrated into the generic Linux
- * I2C framework. And finally, the I2C interface is also known as the 2BI
- * interface. 2BI means 2-bit interface referring to SDA and SCL serial lines
- * respectively.
- *
- * - Manish Lachwani (12/09/2003)
- */
-
-#include "i2c-yosemite.h"
-
-/*
- * Poll the I2C interface for the BUSY bit.
- */
-static int titan_i2c_poll(void)
-{
- int i = 0;
- unsigned long val = 0;
-
- for (i = 0; i < TITAN_I2C_MAX_POLL; i++) {
- val = TITAN_I2C_READ(TITAN_I2C_COMMAND);
-
- if (!(val & 0x8000))
- return 0;
- }
-
- return TITAN_I2C_ERR_TIMEOUT;
-}
-
-/*
- * Execute the I2C command
- */
-int titan_i2c_xfer(unsigned int slave_addr, titan_i2c_command * cmd,
- int size, unsigned int *addr)
-{
- int loop, bytes = 0, i;
- unsigned int *write_data, data, *read_data;
- unsigned long reg_val, val;
-
- write_data = cmd->data;
- read_data = addr;
-
- TITAN_I2C_WRITE(TITAN_I2C_SLAVE_ADDRESS, slave_addr);
-
- if (cmd->type == TITAN_I2C_CMD_WRITE)
- loop = cmd->write_size;
- else
- loop = size;
-
- while (loop > 0) {
- if ((cmd->type == TITAN_I2C_CMD_WRITE) ||
- (cmd->type == TITAN_I2C_CMD_READ_WRITE)) {
-
- reg_val = TITAN_I2C_DATA;
- for (i = 0; i < TITAN_I2C_MAX_WORDS_PER_RW;
- ++i, write_data += 2, reg_val += 4) {
- if (bytes < cmd->write_size) {
- data = write_data[0];
- ++data;
- }
-
- if (bytes < cmd->write_size) {
- data = write_data[1];
- ++data;
- }
-
- TITAN_I2C_WRITE(reg_val, data);
- }
- }
-
- TITAN_I2C_WRITE(TITAN_I2C_COMMAND,
- (unsigned int) (cmd->type << 13));
- if (titan_i2c_poll() != TITAN_I2C_ERR_OK)
- return TITAN_I2C_ERR_TIMEOUT;
-
- if ((cmd->type == TITAN_I2C_CMD_READ) ||
- (cmd->type == TITAN_I2C_CMD_READ_WRITE)) {
-
- reg_val = TITAN_I2C_DATA;
- for (i = 0; i < TITAN_I2C_MAX_WORDS_PER_RW;
- ++i, read_data += 2, reg_val += 4) {
- data = TITAN_I2C_READ(reg_val);
-
- if (bytes < size) {
- read_data[0] = data & 0xff;
- ++bytes;
- }
-
- if (bytes < size) {
- read_data[1] =
- ((data >> 8) & 0xff);
- ++bytes;
- }
- }
- }
-
- loop -= (TITAN_I2C_MAX_WORDS_PER_RW * 2);
- }
-
- /*
- * Read the Interrupt status and then return the appropriate error code
- */
-
- val = TITAN_I2C_READ(TITAN_I2C_INTERRUPTS);
- if (val & 0x0020)
- return TITAN_I2C_ERR_ARB_LOST;
-
- if (val & 0x0040)
- return TITAN_I2C_ERR_NO_RESP;
-
- if (val & 0x0080)
- return TITAN_I2C_ERR_DATA_COLLISION;
-
- return TITAN_I2C_ERR_OK;
-}
-
-/*
- * Init the I2C subsystem of the PMC-Sierra Yosemite board
- */
-int titan_i2c_init(titan_i2c_config * config)
-{
- unsigned int val;
-
- /*
- * Reset the SCMB and program into the I2C mode
- */
- TITAN_I2C_WRITE(TITAN_I2C_SCMB_CONTROL, 0xA000);
- TITAN_I2C_WRITE(TITAN_I2C_SCMB_CONTROL, 0x2000);
-
- /*
- * Configure the filtera and clka values
- */
- val = TITAN_I2C_READ(TITAN_I2C_SCMB_CLOCK_A);
- val |= ((val & ~(0xF000)) | ((config->filtera << 12) & 0xF000));
- val |= ((val & ~(0x03FF)) | (config->clka & 0x03FF));
- TITAN_I2C_WRITE(TITAN_I2C_SCMB_CLOCK_A, val);
-
- /*
- * Configure the filterb and clkb values
- */
- val = TITAN_I2C_READ(TITAN_I2C_SCMB_CLOCK_B);
- val |= ((val & ~(0xF000)) | ((config->filterb << 12) & 0xF000));
- val |= ((val & ~(0x03FF)) | (config->clkb & 0x03FF));
- TITAN_I2C_WRITE(TITAN_I2C_SCMB_CLOCK_B, val);
-
- return TITAN_I2C_ERR_OK;
-}
#define HYPERTRANSPORT_INTC 0x7a /* INTC# */
#define HYPERTRANSPORT_INTD 0x7b /* INTD# */
+extern void titan_mailbox_irq(void);
+
+#ifdef CONFIG_HYPERTRANSPORT
/*
* Handle hypertransport & SMP interrupts. The interrupt lines are scarce.
* For interprocessor interrupts, the best thing to do is to use the INTMSG
do_IRQ(irq);
}
+#endif
asmlinkage void plat_irq_dispatch(void)
{
struct callvectors *debug_vectors;
extern unsigned long yosemite_base;
-extern unsigned long cpu_clock;
+extern unsigned long cpu_clock_freq;
const char *get_system_type(void)
{
16);
if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0)
- cpu_clock =
+ cpu_clock_freq =
simple_strtol(*env + strlen("cpuclock="), NULL,
10);
0x00, 0xe0, 0x04, 0x00, 0x00, 0x21
};
-unsigned long cpu_clock;
+unsigned long cpu_clock_freq;
unsigned long yosemite_base;
static struct m48t37_rtc *m48t37_base;
void yosemite_time_init(void)
{
- mips_hpt_frequency = cpu_clock / 2;
+ mips_hpt_frequency = cpu_clock_freq / 2;
mips_hpt_frequency = 33000000 * 3 * 5;
}
{
}
-asmlinkage void titan_mailbox_irq(void)
+void titan_mailbox_irq(void)
{
int cpu = smp_processor_id();
unsigned long status;
- if (cpu == 0) {
+ switch (cpu) {
+ case 0:
status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
- }
- if (cpu == 1) {
+ if (status & 0x2)
+ smp_call_function_interrupt();
+ break;
+
+ case 1:
status = OCD_READ(RM9000x2_OCD_INTP1STATUS3);
OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status);
- }
- if (status & 0x2)
- smp_call_function_interrupt();
+ if (status & 0x2)
+ smp_call_function_interrupt();
+ break;
+ }
}
/*
obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o
obj-$(CONFIG_SMP) += q-smp.o
+
+EXTRA_CFLAGS += -Werror
obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o
obj-$(CONFIG_KGDB) += ip27-dbgio.o
obj-$(CONFIG_SMP) += ip27-smp.o
+
+EXTRA_CFLAGS += -Werror
*/
void __init setup_replication_mask(void)
{
- cnodeid_t cnode;
-
/* Set only the master cnode's bit. The master cnode is always 0. */
cpus_clear(ktext_repmask);
cpu_set(0, ktext_repmask);
#ifndef CONFIG_MAPPED_KERNEL
#error Kernel replication works with mapped kernel support. No calias support.
#endif
- for_each_online_node(cnode) {
- if (cnode == 0)
- continue;
- /* Advertise that we have a copy of the kernel */
- cpu_set(cnode, ktext_repmask);
+ {
+ cnodeid_t cnode;
+
+ for_each_online_node(cnode) {
+ if (cnode == 0)
+ continue;
+ /* Advertise that we have a copy of the kernel */
+ cpu_set(cnode, ktext_repmask);
+ }
}
#endif
/* Set up a GDA pointer to the replication mask. */
0, (void *) sp, (void *) gp);
}
-void prom_init_secondary(void)
+void __cpuinit prom_init_secondary(void)
{
per_cpu_init();
local_irq_enable();
obj-y += ip32-berr.o ip32-irq.o ip32-platform.o ip32-setup.o ip32-reset.o \
crime.o ip32-memory.o
+
+EXTRA_CFLAGS += -Werror
blink_timer.function = blink_timeout;
atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
- request_irq(MACEISA_RTC_IRQ, ip32_rtc_int, 0, "rtc", NULL);
+ if (request_irq(MACEISA_RTC_IRQ, ip32_rtc_int, 0, "rtc", NULL))
+ panic("Can't allocate MACEISA RTC IRQ");
return 0;
}
obj-y := setup.o irq.o time.o
obj-$(CONFIG_SMP) += smp.o
+
+EXTRA_CFLAGS += -Werror
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/reboot.h>
#include <linux/string.h>
obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o
EXTRA_AFLAGS := $(CFLAGS)
+EXTRA_CFLAGS += -Werror
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SIBYTE_STANDALONE) += prom.o
obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o
+
+EXTRA_CFLAGS += -Werror
obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o
obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o
+
+EXTRA_CFLAGS += -Werror
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/tx4927/tx4927.h>
+#ifdef CONFIG_TOSHIBA_RBTX4927
+#include <asm/tx4927/toshiba_rbtx4927.h>
+#endif
/*
* DEBUG
int toshiba_rbtx4927_irq_nested(int sw_irq)
{
u32 level3;
- u32 level4;
- u32 level5;
level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
if (level3) {
#ifdef CONFIG_TOSHIBA_FPCIB0
{
if (tx4927_using_backplane) {
+ u32 level4;
+ u32 level5;
outb(0x0A, 0x20);
level4 = inb(0x20) & 0xff;
if (level4) {
char *toshiba_name = "";
#ifdef CONFIG_PCI
-static void tx4927_pcierr_interrupt(int irq, void *dev_id)
-{
-#ifdef CONFIG_BLK_DEV_IDEPCI
- /* ignore MasterAbort for ide probing... */
- if (irq == TX4927_IRQ_IRC_PCIERR &&
- ((tx4927_pcicptr->pcistatus >> 16) & 0xf900) ==
- PCI_STATUS_REC_MASTER_ABORT) {
- tx4927_pcicptr->pcistatus =
- (tx4927_pcicptr->
- pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
- << 16);
-
- return;
- }
-#endif
- printk("PCI error interrupt (irq 0x%x).\n", irq);
-
- printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n",
- (unsigned short) (tx4927_pcicptr->pcistatus >> 16),
- tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus);
- printk("ccfg:%08lx, tear:%02lx_%08lx\n",
- (unsigned long) tx4927_ccfgptr->ccfg,
- (unsigned long) (tx4927_ccfgptr->tear >> 32),
- (unsigned long) tx4927_ccfgptr->tear);
- show_regs(get_irq_regs());
-}
-
-void __init toshiba_rbtx4927_pci_irq_init(void)
-{
- return;
-}
-
-void tx4927_reset_pci_pcic(void)
-{
- /* Reset PCI Bus */
- *tx4927_pcireset_ptr = 1;
- /* Reset PCIC */
- tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST;
- udelay(10000);
- /* clear PCIC reset */
- tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST;
- *tx4927_pcireset_ptr = 0;
-}
-#endif /* CONFIG_PCI */
-
-#ifdef CONFIG_PCI
-void print_pci_status(void)
-{
- printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus);
- printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus);
-}
-
extern struct pci_controller tx4927_controller;
static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
}
EARLY_PCI_OP(read, byte, u8 *)
-EARLY_PCI_OP(read, word, u16 *)
EARLY_PCI_OP(read, dword, u32 *)
EARLY_PCI_OP(write, byte, u8)
-EARLY_PCI_OP(write, word, u16)
EARLY_PCI_OP(write, dword, u32)
static int __init tx4927_pcibios_init(void)
u8 v08_64;
u32 v32_b0;
u8 v08_e1;
+#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
char *s = " sb/isa --";
+#endif
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
u8 v08_41;
u8 v08_43;
u8 v08_5c;
+#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
char *s = " sb/ide --";
+#endif
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
/* clocks */
if (txx9_master_clock) {
- /* calculate gbus_clock and cpu_clock from master_clock */
+ /* calculate gbus_clock and cpu_clock_freq from master_clock */
divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
switch (divmode) {
case TX4938_CCFG_DIVMODE_8:
if (txx9_cpu_clock == 0) {
txx9_cpu_clock = 300000000; /* 300MHz */
}
- /* calculate gbus_clock and master_clock from cpu_clock */
+ /* calculate gbus_clock and master_clock from cpu_clock_freq */
cpuclk = txx9_cpu_clock;
divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
switch (divmode) {
#
obj-y += bcu.o cmu.o giu.o icu.o init.o irq.o pmu.o rtc.o siu.o type.o
+
+EXTRA_CFLAGS += -Werror
interrupt-parent = <&/mv64x60/pic>;
};
+ wdt@b410 { /* watchdog timer */
+ compatible = "marvell,mv64x60-wdt";
+ reg = <b410 8>;
+ timeout = <a>; /* wdt timeout in seconds */
+ };
+
i2c@c000 {
device_type = "i2c";
compatible = "marvell,mv64x60-i2c";
return err;
}
+/*
+ * Create mv64x60_wdt platform devices
+ */
+static int __init mv64x60_wdt_device_setup(struct device_node *np, int id)
+{
+ struct resource r;
+ struct platform_device *pdev;
+ struct mv64x60_wdt_pdata pdata;
+ const unsigned int *prop;
+ int err;
+
+ err = of_address_to_resource(np, 0, &r);
+ if (err)
+ return err;
+
+ memset(&pdata, 0, sizeof(pdata));
+
+ prop = of_get_property(np, "timeout", NULL);
+ if (!prop)
+ return -ENODEV;
+ pdata.timeout = *prop;
+
+ np = of_get_parent(np);
+ if (!np)
+ return -ENODEV;
+
+ prop = of_get_property(np, "clock-frequency", NULL);
+ of_node_put(np);
+ if (!prop)
+ return -ENODEV;
+ pdata.bus_clk = *prop / 1000000; /* wdt driver wants freq in MHz */
+
+ pdev = platform_device_alloc(MV64x60_WDT_NAME, id);
+ if (!pdev)
+ return -ENOMEM;
+
+ err = platform_device_add_resources(pdev, &r, 1);
+ if (err)
+ goto error;
+
+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+ if (err)
+ goto error;
+
+ err = platform_device_add(pdev);
+ if (err)
+ goto error;
+
+ return 0;
+
+error:
+ platform_device_put(pdev);
+ return err;
+}
+
static int __init mv64x60_device_setup(void)
{
struct device_node *np = NULL;
if ((err = mv64x60_i2c_device_setup(np, id)))
goto error;
+ /* support up to one watchdog timer */
+ np = of_find_compatible_node(np, NULL, "marvell,mv64x60-wdt");
+ if (np) {
+ if ((err = mv64x60_wdt_device_setup(np, id)))
+ goto error;
+ of_node_put(np);
+ }
+
+
return 0;
error:
};
#endif
+#ifdef CONFIG_WATCHDOG
+static struct mv64x60_wdt_pdata mv64x60_wdt_pdata = {
+ .timeout = 10, /* default watchdog expiry in seconds */
+ .bus_clk = 133, /* default bus clock in MHz */
+};
+
+static struct resource mv64x60_wdt_resources[] = {
+ [0] = {
+ .name = "mv64x60 wdt base",
+ .start = MV64x60_WDT_WDC,
+ .end = MV64x60_WDT_WDC + 8 - 1, /* two 32-bit registers */
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device wdt_device = {
+ .name = MV64x60_WDT_NAME,
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mv64x60_wdt_resources),
+ .resource = mv64x60_wdt_resources,
+ .dev = {
+ .platform_data = &mv64x60_wdt_pdata,
+ },
+};
+#endif
+
#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
static struct mv64xxx_pdata mv64xxx_pdata = {
.hs_reg_valid = 0,
#ifdef CONFIG_I2C_MV64XXX
&i2c_device,
#endif
+#ifdef CONFIG_MV64X60_WDT
+ &wdt_device,
+#endif
#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
&mv64xxx_device,
#endif
obj-$(CONFIG_W1) += w1/
obj-$(CONFIG_POWER_SUPPLY) += power/
obj-$(CONFIG_HWMON) += hwmon/
+obj-$(CONFIG_WATCHDOG) += char/watchdog/
obj-$(CONFIG_PHONE) += telephony/
obj-$(CONFIG_MD) += md/
obj-$(CONFIG_BT) += bluetooth/
Say N to delete /proc/acpi/ files that have moved to /sys/
-config ACPI_PROCFS_SLEEP
- bool "/proc/acpi/sleep (deprecated)"
- depends on PM_SLEEP && ACPI_PROCFS
- default n
- ---help---
- Create /proc/acpi/sleep
- Deprecated by /sys/power/state
-
config ACPI_AC
tristate "AC Adapter"
depends on X86
}
#ifdef CONFIG_PM
-static struct dmi_system_id piix_broken_suspend_dmi_table[] = {
- {
- .ident = "TECRA M5",
- .matches = {
- DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
- DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
- },
- },
- {
- .ident = "Satellite U200",
- .matches = {
- DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
- DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
+static int piix_broken_suspend(void)
+{
+ static struct dmi_system_id sysids[] = {
+ {
+ .ident = "TECRA M5",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
+ },
},
- },
- {
- .ident = "Satellite U205",
- .matches = {
- DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
- DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
+ {
+ .ident = "Satellite U205",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
+ },
},
- },
- {
- .ident = "Portege M500",
- .matches = {
- DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
- DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
+ {
+ .ident = "Portege M500",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
+ },
},
- },
- { }
-};
+ { }
+ };
+ static const char *oemstrs[] = {
+ "Tecra M3,",
+ };
+ int i;
+
+ if (dmi_check_system(sysids))
+ return 1;
+
+ for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
+ if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
+ return 1;
+
+ return 0;
+}
static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
{
* cycles and power trying to do something to the sleeping
* beauty.
*/
- if (dmi_check_system(piix_broken_suspend_dmi_table) &&
- mesg.event == PM_EVENT_SUSPEND) {
+ if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
pci_save_state(pdev);
/* mark its power state as "unknown", since we don't
pci_restore_state(pdev);
/* PCI device wasn't disabled during suspend. Use
- * __pci_reenable_device() to avoid affecting the
- * enable count.
+ * pci_reenable_device() to avoid affecting the enable
+ * count.
*/
- rc = __pci_reenable_device(pdev);
+ rc = pci_reenable_device(pdev);
if (rc)
dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
"device after resume (%d)\n", rc);
{ "WDC WD740ADFD-00NLR1", NULL, ATA_HORKAGE_NONCQ, },
{ "FUJITSU MHV2080BH", "00840028", ATA_HORKAGE_NONCQ, },
{ "ST9160821AS", "3.CLF", ATA_HORKAGE_NONCQ, },
+ { "SAMSUNG HD401LJ", "ZZ100-15", ATA_HORKAGE_NONCQ, },
/* Devices with NCQ limits */
struct pci_dev *pdev = to_pci_dev(gdev);
int i, rc;
+ /* No BAR4 allocation: No DMA */
+ if (pci_resource_start(pdev, 4) == 0)
+ return 0;
+
/* TODO: If we get no DMA mask we should fall back to PIO */
rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
if (rc)
#include <linux/libata.h>
#define DRV_NAME "pata_cmd64x"
-#define DRV_VERSION "0.2.3"
+#define DRV_VERSION "0.2.4"
/*
* CMD64x specific registers definition.
.flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = 0x1f,
.mwdma_mask = 0x07,
- .udma_mask = ATA_UDMA1,
+ .udma_mask = ATA_UDMA2,
.port_ops = &cmd64x_port_ops
},
{ /* CMD 646 rev 1 */
.flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = 0x1f,
.mwdma_mask = 0x07,
- .udma_mask = ATA_UDMA2,
+ .udma_mask = ATA_UDMA4,
.port_ops = &cmd648_port_ops
},
{ /* CMD 649 */
.flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = 0x1f,
.mwdma_mask = 0x07,
- .udma_mask = ATA_UDMA3,
+ .udma_mask = ATA_UDMA5,
.port_ops = &cmd648_port_ops
}
};
* pata_sis.c - SiS ATA driver
*
* (C) 2005 Red Hat <alan@redhat.com>
+ * (C) 2007 Bartlomiej Zolnierkiewicz
*
* Based upon linux/drivers/ide/pci/sis5513.c
* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
#include "sis.h"
#define DRV_NAME "pata_sis"
-#define DRV_VERSION "0.5.1"
+#define DRV_VERSION "0.5.2"
struct sis_chipset {
u16 device; /* PCI host ID */
}
/**
- * sis_100_set_pioode - Initialize host controller PATA PIO timings
+ * sis_100_set_piomode - Initialize host controller PATA PIO timings
* @ap: Port whose timings we are configuring
* @adev: Device we are configuring for.
*
}
/**
- * sis_133_set_pioode - Initialize host controller PATA PIO timings
+ * sis_133_set_piomode - Initialize host controller PATA PIO timings
* @ap: Port whose timings we are configuring
* @adev: Device we are configuring for.
*
int drive_pci = sis_old_port_base(adev);
u16 timing;
- const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
+ const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
pci_read_config_word(pdev, drive_pci, &timing);
if (adev->dma_mode < XFER_UDMA_0) {
/* bits 3-0 hold recovery timing bits 8-10 active timing and
the higer bits are dependant on the device */
- timing &= ~ 0x870F;
+ timing &= ~0x870F;
timing |= mwdma_bits[speed];
- pci_write_config_word(pdev, drive_pci, timing);
} else {
/* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
speed = adev->dma_mode - XFER_UDMA_0;
timing &= ~0x6000;
timing |= udma_bits[speed];
}
+ pci_write_config_word(pdev, drive_pci, timing);
}
/**
int drive_pci = sis_old_port_base(adev);
u16 timing;
- const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
+ const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000};
pci_read_config_word(pdev, drive_pci, &timing);
* @adev: Device to program
*
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
- * Handles early SiS 961 bridges. Supports MWDMA as well unlike
- * the old ide/pci driver.
+ * Handles early SiS 961 bridges.
*
* LOCKING:
* None (inherited from caller).
* @adev: Device to program
*
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
- * Handles early SiS 961 bridges. Supports MWDMA as well unlike
- * the old ide/pci driver.
*
* LOCKING:
* None (inherited from caller).
obj-$(CONFIG_GPIO_TB0219) += tb0219.o
obj-$(CONFIG_TELCLOCK) += tlclk.o
-obj-$(CONFIG_WATCHDOG) += watchdog/
obj-$(CONFIG_MWAVE) += mwave/
obj-$(CONFIG_AGP) += agp/
obj-$(CONFIG_DRM) += drm/
To compile this driver as a module, choose M here: the
module will be called softdog.
+# ALPHA Architecture
+
# ARM Architecture
config AT91RM9200_WATCHDOG
config IOP_WATCHDOG
tristate "IOP Watchdog"
- depends on WATCHDOG && PLAT_IOP
+ depends on PLAT_IOP
select WATCHDOG_NOWAYOUT if (ARCH_IOP32X || ARCH_IOP33X)
help
Say Y here if to include support for the watchdog timer
operating as an Root Complex and/or Central Resource, the PCI-X
and/or PCIe busses will also be reset. THIS IS A VERY BIG HAMMER.
+config DAVINCI_WATCHDOG
+ tristate "DaVinci watchdog"
+ depends on ARCH_DAVINCI
+ help
+ Say Y here if to include support for the watchdog timer
+ in the DaVinci DM644x/DM646x processors.
+ To compile this driver as a module, choose M here: the
+ module will be called davinci_wdt.
+
+ NOTE: once enabled, this timer cannot be disabled.
+ Say N if you are unsure.
+
+# ARM26 Architecture
+
# AVR32 Architecture
config AT32AP700X_WDT
tristate "AT32AP700x watchdog"
- depends on WATCHDOG && CPU_AT32AP7000
+ depends on CPU_AT32AP7000
help
Watchdog timer embedded into AT32AP700x devices. This will reboot
your system when the timeout is reached.
+# BLACKFIN Architecture
+
+config BFIN_WDT
+ tristate "Blackfin On-Chip Watchdog Timer"
+ depends on BLACKFIN
+ ---help---
+ If you say yes here you will get support for the Blackfin On-Chip
+ Watchdog Timer. If you have one of these processors and wish to
+ have watchdog support enabled, say Y, otherwise say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called bfin_wdt.
+
+# CRIS Architecture
+
+# FRV Architecture
+
+# H8300 Architecture
+
# X86 (i386 + ia64 + x86_64) Architecture
config ACQUIRE_WDT
To compile this driver as a module, choose M here: the
module will be called sbc_epx_c3.
-# PowerPC Architecture
+# M32R Architecture
-config 8xx_WDT
- tristate "MPC8xx Watchdog Timer"
- depends on 8xx
+# M68K Architecture
-config 83xx_WDT
- tristate "MPC83xx Watchdog Timer"
- depends on PPC_83xx
-
-config MV64X60_WDT
- tristate "MV64X60 (Marvell Discovery) Watchdog Timer"
- depends on MV64X60
-
-config BOOKE_WDT
- bool "PowerPC Book-E Watchdog Timer"
- depends on BOOKE || 4xx
- ---help---
- Please see Documentation/watchdog/watchdog-api.txt for
- more information.
-
-# PPC64 Architecture
-
-config WATCHDOG_RTAS
- tristate "RTAS watchdog"
- depends on PPC_RTAS
- help
- This driver adds watchdog support for the RTAS watchdog.
-
- To compile this driver as a module, choose M here. The module
- will be called wdrtas.
+# M68KNOMMU Architecture
# MIPS Architecture
To compile this driver as a module, choose M here: the
module will be called rm9k_wdt.
+# PARISC Architecture
+
+# POWERPC Architecture
+
+config MPC5200_WDT
+ tristate "MPC5200 Watchdog Timer"
+ depends on PPC_MPC52xx
+
+config 8xx_WDT
+ tristate "MPC8xx Watchdog Timer"
+ depends on 8xx
+
+config 83xx_WDT
+ tristate "MPC83xx Watchdog Timer"
+ depends on PPC_83xx
+
+config MV64X60_WDT
+ tristate "MV64X60 (Marvell Discovery) Watchdog Timer"
+ depends on MV64X60
+
+config BOOKE_WDT
+ bool "PowerPC Book-E Watchdog Timer"
+ depends on BOOKE || 4xx
+ ---help---
+ Please see Documentation/watchdog/watchdog-api.txt for
+ more information.
+
+# PPC64 Architecture
+
+config WATCHDOG_RTAS
+ tristate "RTAS watchdog"
+ depends on PPC_RTAS
+ help
+ This driver adds watchdog support for the RTAS watchdog.
+
+ To compile this driver as a module, choose M here. The module
+ will be called wdrtas.
+
# S390 Architecture
config ZVM_WATCHDOG
To compile this driver as a module, choose M here. The module
will be called vmwatchdog.
-# SUPERH Architecture
+# SUPERH (sh + sh64) Architecture
config SH_WDT
tristate "SuperH Watchdog"
If you say Y here, user applications will be able to mmap the
WDT/CPG registers.
+# SPARC Architecture
+
# SPARC64 Architecture
config WATCHDOG_CP1XXX
machines. The watchdog timeout period is normally one minute but
can be changed with a boot-time parameter.
+# V850 Architecture
+
+# XTENSA Architecture
+
#
# ISA-based Watchdog Cards
#
# USB-based Watchdog Cards
obj-$(CONFIG_USBPCWATCHDOG) += pcwd_usb.o
+# ALPHA Architecture
+
# ARM Architecture
obj-$(CONFIG_AT91RM9200_WATCHDOG) += at91rm9200_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o
obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
+obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
+
+# ARM26 Architecture
# AVR32 Architecture
obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
+# BLACKFIN Architecture
+obj-$(CONFIG_BFIN_WDT) += bfin_wdt.o
+
+# CRIS Architecture
+
+# FRV Architecture
+
+# H8300 Architecture
+
# X86 (i386 + ia64 + x86_64) Architecture
obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o
obj-$(CONFIG_ADVANTECH_WDT) += advantechwdt.o
obj-$(CONFIG_MACHZ_WDT) += machzwd.o
obj-$(CONFIG_SBC_EPX_C3_WATCHDOG) += sbc_epx_c3.o
-# PowerPC Architecture
+# M32R Architecture
+
+# M68K Architecture
+
+# M68KNOMMU Architecture
+
+# MIPS Architecture
+obj-$(CONFIG_INDYDOG) += indydog.o
+obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
+obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
+
+# PARISC Architecture
+
+# POWERPC Architecture
obj-$(CONFIG_8xx_WDT) += mpc8xx_wdt.o
+obj-$(CONFIG_MPC5200_WDT) += mpc5200_wdt.o
obj-$(CONFIG_83xx_WDT) += mpc83xx_wdt.o
obj-$(CONFIG_MV64X60_WDT) += mv64x60_wdt.o
obj-$(CONFIG_BOOKE_WDT) += booke_wdt.o
# PPC64 Architecture
obj-$(CONFIG_WATCHDOG_RTAS) += wdrtas.o
-# MIPS Architecture
-obj-$(CONFIG_INDYDOG) += indydog.o
-obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
-obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
-
# S390 Architecture
-# SUPERH Architecture
+# SUPERH (sh + sh64) Architecture
obj-$(CONFIG_SH_WDT) += shwdt.o
+# SPARC Architecture
+
# SPARC64 Architecture
+# V850 Architecture
+
+# XTENSA Architecture
+
# Architecture Independant
obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o
--- /dev/null
+/*
+ * Blackfin On-Chip Watchdog Driver
+ * Supports BF53[123]/BF53[467]/BF54[2489]/BF561
+ *
+ * Originally based on softdog.c
+ * Copyright 2006-2007 Analog Devices Inc.
+ * Copyright 2006-2007 Michele d'Amico
+ * Copyright 1996 Alan Cox <alan@redhat.com>
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/types.h>
+#include <linux/timer.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/fs.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <asm/blackfin.h>
+#include <asm/uaccess.h>
+
+#define stamp(fmt, args...) pr_debug("%s:%i: " fmt "\n", __func__, __LINE__, ## args)
+#define stampit() stamp("here i am")
+
+#define WATCHDOG_NAME "bfin-wdt"
+#define PFX WATCHDOG_NAME ": "
+
+/* The BF561 has two watchdogs (one per core), but since Linux
+ * only runs on core A, we'll just work with that one.
+ */
+#ifdef BF561_FAMILY
+# define bfin_read_WDOG_CTL() bfin_read_WDOGA_CTL()
+# define bfin_read_WDOG_CNT() bfin_read_WDOGA_CNT()
+# define bfin_read_WDOG_STAT() bfin_read_WDOGA_STAT()
+# define bfin_write_WDOG_CTL(x) bfin_write_WDOGA_CTL(x)
+# define bfin_write_WDOG_CNT(x) bfin_write_WDOGA_CNT(x)
+# define bfin_write_WDOG_STAT(x) bfin_write_WDOGA_STAT(x)
+#endif
+
+/* Bit in SWRST that indicates boot caused by watchdog */
+#define SWRST_RESET_WDOG 0x4000
+
+/* Bit in WDOG_CTL that indicates watchdog has expired (WDR0) */
+#define WDOG_EXPIRED 0x8000
+
+/* Masks for WDEV field in WDOG_CTL register */
+#define ICTL_RESET 0x0
+#define ICTL_NMI 0x2
+#define ICTL_GPI 0x4
+#define ICTL_NONE 0x6
+#define ICTL_MASK 0x6
+
+/* Masks for WDEN field in WDOG_CTL register */
+#define WDEN_MASK 0x0FF0
+#define WDEN_ENABLE 0x0000
+#define WDEN_DISABLE 0x0AD0
+
+/* some defaults */
+#define WATCHDOG_TIMEOUT 20
+
+static unsigned int timeout = WATCHDOG_TIMEOUT;
+static int nowayout = WATCHDOG_NOWAYOUT;
+static struct watchdog_info bfin_wdt_info;
+static unsigned long open_check;
+static char expect_close;
+static spinlock_t bfin_wdt_spinlock = SPIN_LOCK_UNLOCKED;
+
+/**
+ * bfin_wdt_keepalive - Keep the Userspace Watchdog Alive
+ *
+ * The Userspace watchdog got a KeepAlive: schedule the next timeout.
+ */
+static int bfin_wdt_keepalive(void)
+{
+ stampit();
+ bfin_write_WDOG_STAT(0);
+ return 0;
+}
+
+/**
+ * bfin_wdt_stop - Stop the Watchdog
+ *
+ * Stops the on-chip watchdog.
+ */
+static int bfin_wdt_stop(void)
+{
+ stampit();
+ bfin_write_WDOG_CTL(WDEN_DISABLE);
+ return 0;
+}
+
+/**
+ * bfin_wdt_start - Start the Watchdog
+ *
+ * Starts the on-chip watchdog. Automatically loads WDOG_CNT
+ * into WDOG_STAT for us.
+ */
+static int bfin_wdt_start(void)
+{
+ stampit();
+ bfin_write_WDOG_CTL(WDEN_ENABLE | ICTL_RESET);
+ return 0;
+}
+
+/**
+ * bfin_wdt_running - Check Watchdog status
+ *
+ * See if the watchdog is running.
+ */
+static int bfin_wdt_running(void)
+{
+ stampit();
+ return ((bfin_read_WDOG_CTL() & WDEN_MASK) != WDEN_DISABLE);
+}
+
+/**
+ * bfin_wdt_set_timeout - Set the Userspace Watchdog timeout
+ * @t: new timeout value (in seconds)
+ *
+ * Translate the specified timeout in seconds into System Clock
+ * terms which is what the on-chip Watchdog requires.
+ */
+static int bfin_wdt_set_timeout(unsigned long t)
+{
+ u32 cnt;
+ unsigned long flags;
+
+ stampit();
+
+ cnt = t * get_sclk();
+ if (cnt < get_sclk()) {
+ printk(KERN_WARNING PFX "timeout value is too large\n");
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&bfin_wdt_spinlock, flags);
+ {
+ int run = bfin_wdt_running();
+ bfin_wdt_stop();
+ bfin_write_WDOG_CNT(cnt);
+ if (run) bfin_wdt_start();
+ }
+ spin_unlock_irqrestore(&bfin_wdt_spinlock, flags);
+
+ timeout = t;
+
+ return 0;
+}
+
+/**
+ * bfin_wdt_open - Open the Device
+ * @inode: inode of device
+ * @file: file handle of device
+ *
+ * Watchdog device is opened and started.
+ */
+static int bfin_wdt_open(struct inode *inode, struct file *file)
+{
+ stampit();
+
+ if (test_and_set_bit(0, &open_check))
+ return -EBUSY;
+
+ if (nowayout)
+ __module_get(THIS_MODULE);
+
+ bfin_wdt_keepalive();
+ bfin_wdt_start();
+
+ return nonseekable_open(inode, file);
+}
+
+/**
+ * bfin_wdt_close - Close the Device
+ * @inode: inode of device
+ * @file: file handle of device
+ *
+ * Watchdog device is closed and stopped.
+ */
+static int bfin_wdt_release(struct inode *inode, struct file *file)
+{
+ stampit();
+
+ if (expect_close == 42) {
+ bfin_wdt_stop();
+ } else {
+ printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n");
+ bfin_wdt_keepalive();
+ }
+
+ expect_close = 0;
+ clear_bit(0, &open_check);
+
+ return 0;
+}
+
+/**
+ * bfin_wdt_write - Write to Device
+ * @file: file handle of device
+ * @buf: buffer to write
+ * @count: length of buffer
+ * @ppos: offset
+ *
+ * Pings the watchdog on write.
+ */
+static ssize_t bfin_wdt_write(struct file *file, const char __user *data,
+ size_t len, loff_t *ppos)
+{
+ stampit();
+
+ if (len) {
+ if (!nowayout) {
+ size_t i;
+
+ /* In case it was set long ago */
+ expect_close = 0;
+
+ for (i = 0; i != len; i++) {
+ char c;
+ if (get_user(c, data + i))
+ return -EFAULT;
+ if (c == 'V')
+ expect_close = 42;
+ }
+ }
+ bfin_wdt_keepalive();
+ }
+
+ return len;
+}
+
+/**
+ * bfin_wdt_ioctl - Query Device
+ * @inode: inode of device
+ * @file: file handle of device
+ * @cmd: watchdog command
+ * @arg: argument
+ *
+ * Query basic information from the device or ping it, as outlined by the
+ * watchdog API.
+ */
+static int bfin_wdt_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ void __user *argp = (void __user *)arg;
+ int __user *p = argp;
+
+ stampit();
+
+ switch (cmd) {
+ default:
+ return -ENOTTY;
+
+ case WDIOC_GETSUPPORT:
+ if (copy_to_user(argp, &bfin_wdt_info, sizeof(bfin_wdt_info)))
+ return -EFAULT;
+ else
+ return 0;
+
+ case WDIOC_GETSTATUS:
+ case WDIOC_GETBOOTSTATUS:
+ return put_user(!!(_bfin_swrst & SWRST_RESET_WDOG), p);
+
+ case WDIOC_KEEPALIVE:
+ bfin_wdt_keepalive();
+ return 0;
+
+ case WDIOC_SETTIMEOUT: {
+ int new_timeout;
+
+ if (get_user(new_timeout, p))
+ return -EFAULT;
+
+ if (bfin_wdt_set_timeout(new_timeout))
+ return -EINVAL;
+ }
+ /* Fall */
+ case WDIOC_GETTIMEOUT:
+ return put_user(timeout, p);
+
+ case WDIOC_SETOPTIONS: {
+ unsigned long flags;
+ int options, ret = -EINVAL;
+
+ if (get_user(options, p))
+ return -EFAULT;
+
+ spin_lock_irqsave(&bfin_wdt_spinlock, flags);
+
+ if (options & WDIOS_DISABLECARD) {
+ bfin_wdt_stop();
+ ret = 0;
+ }
+
+ if (options & WDIOS_ENABLECARD) {
+ bfin_wdt_start();
+ ret = 0;
+ }
+
+ spin_unlock_irqrestore(&bfin_wdt_spinlock, flags);
+
+ return ret;
+ }
+ }
+}
+
+/**
+ * bfin_wdt_notify_sys - Notifier Handler
+ * @this: notifier block
+ * @code: notifier event
+ * @unused: unused
+ *
+ * Handles specific events, such as turning off the watchdog during a
+ * shutdown event.
+ */
+static int bfin_wdt_notify_sys(struct notifier_block *this, unsigned long code,
+ void *unused)
+{
+ stampit();
+
+ if (code == SYS_DOWN || code == SYS_HALT)
+ bfin_wdt_stop();
+
+ return NOTIFY_DONE;
+}
+
+#ifdef CONFIG_PM
+static int state_before_suspend;
+
+/**
+ * bfin_wdt_suspend - suspend the watchdog
+ * @pdev: device being suspended
+ * @state: requested suspend state
+ *
+ * Remember if the watchdog was running and stop it.
+ * TODO: is this even right? Doesn't seem to be any
+ * standard in the watchdog world ...
+ */
+static int bfin_wdt_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ stampit();
+
+ state_before_suspend = bfin_wdt_running();
+ bfin_wdt_stop();
+
+ return 0;
+}
+
+/**
+ * bfin_wdt_resume - resume the watchdog
+ * @pdev: device being resumed
+ *
+ * If the watchdog was running, turn it back on.
+ */
+static int bfin_wdt_resume(struct platform_device *pdev)
+{
+ stampit();
+
+ if (state_before_suspend) {
+ bfin_wdt_set_timeout(timeout);
+ bfin_wdt_start();
+ }
+
+ return 0;
+}
+#else
+# define bfin_wdt_suspend NULL
+# define bfin_wdt_resume NULL
+#endif
+
+static struct platform_device bfin_wdt_device = {
+ .name = WATCHDOG_NAME,
+ .id = -1,
+};
+
+static struct platform_driver bfin_wdt_driver = {
+ .driver = {
+ .name = WATCHDOG_NAME,
+ .owner = THIS_MODULE,
+ },
+ .suspend = bfin_wdt_suspend,
+ .resume = bfin_wdt_resume,
+};
+
+static struct file_operations bfin_wdt_fops = {
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .write = bfin_wdt_write,
+ .ioctl = bfin_wdt_ioctl,
+ .open = bfin_wdt_open,
+ .release = bfin_wdt_release,
+};
+
+static struct miscdevice bfin_wdt_miscdev = {
+ .minor = WATCHDOG_MINOR,
+ .name = "watchdog",
+ .fops = &bfin_wdt_fops,
+};
+
+static struct watchdog_info bfin_wdt_info = {
+ .identity = "Blackfin Watchdog",
+ .options = WDIOF_SETTIMEOUT |
+ WDIOF_KEEPALIVEPING |
+ WDIOF_MAGICCLOSE,
+};
+
+static struct notifier_block bfin_wdt_notifier = {
+ .notifier_call = bfin_wdt_notify_sys,
+};
+
+/**
+ * bfin_wdt_init - Initialize module
+ *
+ * Registers the device and notifier handler. Actual device
+ * initialization is handled by bfin_wdt_open().
+ */
+static int __init bfin_wdt_init(void)
+{
+ int ret;
+
+ stampit();
+
+ /* Check that the timeout value is within range */
+ if (bfin_wdt_set_timeout(timeout))
+ return -EINVAL;
+
+ /* Since this is an on-chip device and needs no board-specific
+ * resources, we'll handle all the platform device stuff here.
+ */
+ ret = platform_device_register(&bfin_wdt_device);
+ if (ret)
+ return ret;
+
+ ret = platform_driver_probe(&bfin_wdt_driver, NULL);
+ if (ret)
+ return ret;
+
+ ret = register_reboot_notifier(&bfin_wdt_notifier);
+ if (ret) {
+ printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", ret);
+ return ret;
+ }
+
+ ret = misc_register(&bfin_wdt_miscdev);
+ if (ret) {
+ printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n",
+ WATCHDOG_MINOR, ret);
+ unregister_reboot_notifier(&bfin_wdt_notifier);
+ return ret;
+ }
+
+ printk(KERN_INFO PFX "initialized: timeout=%d sec (nowayout=%d)\n",
+ timeout, nowayout);
+
+ return 0;
+}
+
+/**
+ * bfin_wdt_exit - Deinitialize module
+ *
+ * Unregisters the device and notifier handler. Actual device
+ * deinitialization is handled by bfin_wdt_close().
+ */
+static void __exit bfin_wdt_exit(void)
+{
+ misc_deregister(&bfin_wdt_miscdev);
+ unregister_reboot_notifier(&bfin_wdt_notifier);
+}
+
+module_init(bfin_wdt_init);
+module_exit(bfin_wdt_exit);
+
+MODULE_AUTHOR("Michele d'Amico, Mike Frysinger <vapier@gentoo.org>");
+MODULE_DESCRIPTION("Blackfin Watchdog Device Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
+
+module_param(timeout, uint, 0);
+MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=((2^32)/SCLK), default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
+
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
booke_wdt_period);
}
- return 0;
+ return nonseekable_open(inode, file);
}
static const struct file_operations booke_wdt_fops = {
if ( copy_to_user(argp, &value, sizeof(int)) )
return -EFAULT;
break;
+ case WDIOC_GETBOOTSTATUS:
+ if ( copy_to_user(argp, &value, sizeof(int)) )
+ return -EFAULT;
+ break;
case WDIOC_GETSUPPORT:
if ( copy_to_user(argp, &ident, sizeof(ident)) )
return -EFAULT;
--- /dev/null
+/*
+ * drivers/char/watchdog/davinci_wdt.c
+ *
+ * Watchdog driver for DaVinci DM644x/DM646x processors
+ *
+ * Copyright (C) 2006 Texas Instruments.
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/init.h>
+#include <linux/bitops.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+#include <asm/hardware.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+
+#define MODULE_NAME "DAVINCI-WDT: "
+
+#define DEFAULT_HEARTBEAT 60
+#define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
+
+/* Timer register set definition */
+#define PID12 (0x0)
+#define EMUMGT (0x4)
+#define TIM12 (0x10)
+#define TIM34 (0x14)
+#define PRD12 (0x18)
+#define PRD34 (0x1C)
+#define TCR (0x20)
+#define TGCR (0x24)
+#define WDTCR (0x28)
+
+/* TCR bit definitions */
+#define ENAMODE12_DISABLED (0 << 6)
+#define ENAMODE12_ONESHOT (1 << 6)
+#define ENAMODE12_PERIODIC (2 << 6)
+
+/* TGCR bit definitions */
+#define TIM12RS_UNRESET (1 << 0)
+#define TIM34RS_UNRESET (1 << 1)
+#define TIMMODE_64BIT_WDOG (2 << 2)
+
+/* WDTCR bit definitions */
+#define WDEN (1 << 14)
+#define WDFLAG (1 << 15)
+#define WDKEY_SEQ0 (0xa5c6 << 16)
+#define WDKEY_SEQ1 (0xda7e << 16)
+
+static int heartbeat = DEFAULT_HEARTBEAT;
+
+static spinlock_t io_lock;
+static unsigned long wdt_status;
+#define WDT_IN_USE 0
+#define WDT_OK_TO_CLOSE 1
+#define WDT_REGION_INITED 2
+#define WDT_DEVICE_INITED 3
+
+static struct resource *wdt_mem;
+static void __iomem *wdt_base;
+
+static void wdt_service(void)
+{
+ spin_lock(&io_lock);
+
+ /* put watchdog in service state */
+ davinci_writel(WDKEY_SEQ0, wdt_base + WDTCR);
+ /* put watchdog in active state */
+ davinci_writel(WDKEY_SEQ1, wdt_base + WDTCR);
+
+ spin_unlock(&io_lock);
+}
+
+static void wdt_enable(void)
+{
+ u32 tgcr;
+ u32 timer_margin;
+
+ spin_lock(&io_lock);
+
+ /* disable, internal clock source */
+ davinci_writel(0, wdt_base + TCR);
+ /* reset timer, set mode to 64-bit watchdog, and unreset */
+ davinci_writel(0, wdt_base + TGCR);
+ tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
+ davinci_writel(tgcr, wdt_base + TGCR);
+ /* clear counter regs */
+ davinci_writel(0, wdt_base + TIM12);
+ davinci_writel(0, wdt_base + TIM34);
+ /* set timeout period */
+ timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) & 0xffffffff);
+ davinci_writel(timer_margin, wdt_base + PRD12);
+ timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) >> 32);
+ davinci_writel(timer_margin, wdt_base + PRD34);
+ /* enable run continuously */
+ davinci_writel(ENAMODE12_PERIODIC, wdt_base + TCR);
+ /* Once the WDT is in pre-active state write to
+ * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
+ * write protected (except for the WDKEY field)
+ */
+ /* put watchdog in pre-active state */
+ davinci_writel(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
+ /* put watchdog in active state */
+ davinci_writel(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
+
+ spin_unlock(&io_lock);
+}
+
+static int davinci_wdt_open(struct inode *inode, struct file *file)
+{
+ if (test_and_set_bit(WDT_IN_USE, &wdt_status))
+ return -EBUSY;
+
+ wdt_enable();
+
+ return nonseekable_open(inode, file);
+}
+
+static ssize_t
+davinci_wdt_write(struct file *file, const char *data, size_t len,
+ loff_t *ppos)
+{
+ if (len)
+ wdt_service();
+
+ return len;
+}
+
+static struct watchdog_info ident = {
+ .options = WDIOF_KEEPALIVEPING,
+ .identity = "DaVinci Watchdog",
+};
+
+static int
+davinci_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
+ unsigned long arg)
+{
+ int ret = -ENOTTY;
+
+ switch (cmd) {
+ case WDIOC_GETSUPPORT:
+ ret = copy_to_user((struct watchdog_info *)arg, &ident,
+ sizeof(ident)) ? -EFAULT : 0;
+ break;
+
+ case WDIOC_GETSTATUS:
+ case WDIOC_GETBOOTSTATUS:
+ ret = put_user(0, (int *)arg);
+ break;
+
+ case WDIOC_GETTIMEOUT:
+ ret = put_user(heartbeat, (int *)arg);
+ break;
+
+ case WDIOC_KEEPALIVE:
+ wdt_service();
+ ret = 0;
+ break;
+ }
+ return ret;
+}
+
+static int davinci_wdt_release(struct inode *inode, struct file *file)
+{
+ wdt_service();
+ clear_bit(WDT_IN_USE, &wdt_status);
+
+ return 0;
+}
+
+static const struct file_operations davinci_wdt_fops = {
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .write = davinci_wdt_write,
+ .ioctl = davinci_wdt_ioctl,
+ .open = davinci_wdt_open,
+ .release = davinci_wdt_release,
+};
+
+static struct miscdevice davinci_wdt_miscdev = {
+ .minor = WATCHDOG_MINOR,
+ .name = "watchdog",
+ .fops = &davinci_wdt_fops,
+};
+
+static int davinci_wdt_probe(struct platform_device *pdev)
+{
+ int ret = 0, size;
+ struct resource *res;
+
+ spin_lock_init(&io_lock);
+
+ if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
+ heartbeat = DEFAULT_HEARTBEAT;
+
+ printk(KERN_INFO MODULE_NAME
+ "DaVinci Watchdog Timer: heartbeat %d sec\n", heartbeat);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res == NULL) {
+ printk(KERN_INFO MODULE_NAME
+ "failed to get memory region resource\n");
+ return -ENOENT;
+ }
+
+ size = res->end - res->start + 1;
+ wdt_mem = request_mem_region(res->start, size, pdev->name);
+
+ if (wdt_mem == NULL) {
+ printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
+ return -ENOENT;
+ }
+ wdt_base = (void __iomem *)(res->start);
+
+ ret = misc_register(&davinci_wdt_miscdev);
+ if (ret < 0) {
+ printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
+ release_resource(wdt_mem);
+ kfree(wdt_mem);
+ } else {
+ set_bit(WDT_DEVICE_INITED, &wdt_status);
+ }
+
+ return ret;
+}
+
+static int davinci_wdt_remove(struct platform_device *pdev)
+{
+ misc_deregister(&davinci_wdt_miscdev);
+ if (wdt_mem) {
+ release_resource(wdt_mem);
+ kfree(wdt_mem);
+ wdt_mem = NULL;
+ }
+ return 0;
+}
+
+static struct platform_driver platform_wdt_driver = {
+ .driver = {
+ .name = "watchdog",
+ },
+ .probe = davinci_wdt_probe,
+ .remove = davinci_wdt_remove,
+};
+
+static int __init davinci_wdt_init(void)
+{
+ return platform_driver_register(&platform_wdt_driver);
+}
+
+static void __exit davinci_wdt_exit(void)
+{
+ return platform_driver_unregister(&platform_wdt_driver);
+}
+
+module_init(davinci_wdt_init);
+module_exit(davinci_wdt_exit);
+
+MODULE_AUTHOR("Texas Instruments");
+MODULE_DESCRIPTION("DaVinci Watchdog Driver");
+
+module_param(heartbeat, int, 0);
+MODULE_PARM_DESC(heartbeat,
+ "Watchdog heartbeat period in seconds from 1 to "
+ __MODULE_STRING(MAX_HEARTBEAT) ", default "
+ __MODULE_STRING(DEFAULT_HEARTBEAT));
+
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
* 82801HR (ICH8R) : document number 313056-002, 313057-004,
* 82801HH (ICH8DH) : document number 313056-002, 313057-004,
* 82801HO (ICH8DO) : document number 313056-002, 313057-004,
- * 6300ESB (6300ESB) : document number 300641-003
+ * 82801IB (ICH9) : document number 316972-001, 316973-001,
+ * 82801IR (ICH9R) : document number 316972-001, 316973-001,
+ * 82801IH (ICH9DH) : document number 316972-001, 316973-001,
+ * 6300ESB (6300ESB) : document number 300641-003, 300884-010,
+ * 631xESB (631xESB) : document number 313082-001, 313075-005,
+ * 632xESB (632xESB) : document number 313082-001, 313075-005
*/
/*
/* Module and version information */
#define DRV_NAME "iTCO_wdt"
-#define DRV_VERSION "1.01"
-#define DRV_RELDATE "21-Jan-2007"
+#define DRV_VERSION "1.02"
+#define DRV_RELDATE "26-Jul-2007"
#define PFX DRV_NAME ": "
/* Includes */
TCO_ICH8, /* ICH8 & ICH8R */
TCO_ICH8DH, /* ICH8DH */
TCO_ICH8DO, /* ICH8DO */
+ TCO_ICH9, /* ICH9 */
+ TCO_ICH9R, /* ICH9R */
+ TCO_ICH9DH, /* ICH9DH */
+ TCO_631XESB, /* 631xESB/632xESB */
};
static struct {
{"ICH8 or ICH8R", 2},
{"ICH8DH", 2},
{"ICH8DO", 2},
+ {"ICH9", 2},
+ {"ICH9R", 2},
+ {"ICH9DH", 2},
+ {"631xESB/632xESB", 2},
{NULL,0}
};
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH8 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH8DH },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH8DO },
+ { PCI_VENDOR_ID_INTEL, 0x2918, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH9 },
+ { PCI_VENDOR_ID_INTEL, 0x2916, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH9R },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH9DH },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x2671, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x2672, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x2673, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x2674, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x2675, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x2676, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x2677, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x2678, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x2679, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x267a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x267b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x267c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x267d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x267e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
+ { PCI_VENDOR_ID_INTEL, 0x267f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
{ 0, }, /* End of list */
};
MODULE_DEVICE_TABLE (pci, iTCO_wdt_pci_tbl);
break;
case WDIOC_GETSTATUS:
+ case WDIOC_GETBOOTSTATUS:
return put_user(0, p);
case WDIOC_KEEPALIVE:
return -EFAULT;
}
break;
+ case WDIOC_GETBOOTSTATUS:
+ if (copy_to_user(p, &status, sizeof(int))) {
+ return -EFAULT;
+ }
+ break;
case WDIOC_GETSUPPORT:
if (copy_to_user(argp, &ident, sizeof(ident))) {
return -EFAULT;
--- /dev/null
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <asm/of_platform.h>
+#include <asm/uaccess.h>
+#include <asm/mpc52xx.h>
+
+
+#define GPT_MODE_WDT (1<<15)
+#define GPT_MODE_CE (1<<12)
+#define GPT_MODE_MS_TIMER (0x4)
+
+
+struct mpc5200_wdt {
+ unsigned count; /* timer ticks before watchdog kicks in */
+ long ipb_freq;
+ struct miscdevice miscdev;
+ struct resource mem;
+ struct mpc52xx_gpt __iomem *regs;
+ spinlock_t io_lock;
+};
+
+/* is_active stores wether or not the /dev/watchdog device is opened */
+static unsigned long is_active;
+
+/* misc devices don't provide a way, to get back to 'dev' or 'miscdev' from
+ * file operations, which sucks. But there can be max 1 watchdog anyway, so...
+ */
+static struct mpc5200_wdt *wdt_global;
+
+
+/* helper to calculate timeout in timer counts */
+static void mpc5200_wdt_set_timeout(struct mpc5200_wdt *wdt, int timeout)
+{
+ /* use biggest prescaler of 64k */
+ wdt->count = (wdt->ipb_freq + 0xffff) / 0x10000 * timeout;
+
+ if (wdt->count > 0xffff)
+ wdt->count = 0xffff;
+}
+/* return timeout in seconds (calculated from timer count) */
+static int mpc5200_wdt_get_timeout(struct mpc5200_wdt *wdt)
+{
+ return wdt->count * 0x10000 / wdt->ipb_freq;
+}
+
+
+/* watchdog operations */
+static int mpc5200_wdt_start(struct mpc5200_wdt *wdt)
+{
+ spin_lock(&wdt->io_lock);
+ /* disable */
+ out_be32(&wdt->regs->mode, 0);
+ /* set timeout, with maximum prescaler */
+ out_be32(&wdt->regs->count, 0x0 | wdt->count);
+ /* enable watchdog */
+ out_be32(&wdt->regs->mode, GPT_MODE_CE | GPT_MODE_WDT | GPT_MODE_MS_TIMER);
+ spin_unlock(&wdt->io_lock);
+
+ return 0;
+}
+static int mpc5200_wdt_ping(struct mpc5200_wdt *wdt)
+{
+ spin_lock(&wdt->io_lock);
+ /* writing A5 to OCPW resets the watchdog */
+ out_be32(&wdt->regs->mode, 0xA5000000 | (0xffffff & in_be32(&wdt->regs->mode)));
+ spin_unlock(&wdt->io_lock);
+ return 0;
+}
+static int mpc5200_wdt_stop(struct mpc5200_wdt *wdt)
+{
+ spin_lock(&wdt->io_lock);
+ /* disable */
+ out_be32(&wdt->regs->mode, 0);
+ spin_unlock(&wdt->io_lock);
+ return 0;
+}
+
+
+/* file operations */
+static ssize_t mpc5200_wdt_write(struct file *file, const char *data,
+ size_t len, loff_t *ppos)
+{
+ struct mpc5200_wdt *wdt = file->private_data;
+ mpc5200_wdt_ping(wdt);
+ return 0;
+}
+static struct watchdog_info mpc5200_wdt_info = {
+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
+ .identity = "mpc5200 watchdog on GPT0",
+};
+static int mpc5200_wdt_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ struct mpc5200_wdt *wdt = file->private_data;
+ int __user *data = (int __user *)arg;
+ int timeout;
+ int ret = 0;
+
+ switch (cmd) {
+ case WDIOC_GETSUPPORT:
+ ret = copy_to_user(data, &mpc5200_wdt_info,
+ sizeof(mpc5200_wdt_info));
+ if (ret)
+ ret = -EFAULT;
+ break;
+
+ case WDIOC_GETSTATUS:
+ case WDIOC_GETBOOTSTATUS:
+ ret = put_user(0, data);
+ break;
+
+ case WDIOC_KEEPALIVE:
+ mpc5200_wdt_ping(wdt);
+ break;
+
+ case WDIOC_SETTIMEOUT:
+ ret = get_user(timeout, data);
+ if (ret)
+ break;
+ mpc5200_wdt_set_timeout(wdt, timeout);
+ mpc5200_wdt_start(wdt);
+ /* fall through and return the timeout */
+
+ case WDIOC_GETTIMEOUT:
+ timeout = mpc5200_wdt_get_timeout(wdt);
+ ret = put_user(timeout, data);
+ break;
+
+ default:
+ ret = -ENOTTY;
+ }
+ return ret;
+}
+static int mpc5200_wdt_open(struct inode *inode, struct file *file)
+{
+ /* /dev/watchdog can only be opened once */
+ if (test_and_set_bit(0, &is_active))
+ return -EBUSY;
+
+ /* Set and activate the watchdog */
+ mpc5200_wdt_set_timeout(wdt_global, 30);
+ mpc5200_wdt_start(wdt_global);
+ file->private_data = wdt_global;
+ return nonseekable_open(inode, file);
+}
+static int mpc5200_wdt_release(struct inode *inode, struct file *file)
+{
+#if WATCHDOG_NOWAYOUT == 0
+ struct mpc5200_wdt *wdt = file->private_data;
+ mpc5200_wdt_stop(wdt);
+ wdt->count = 0; /* == disabled */
+#endif
+ clear_bit(0, &is_active);
+ return 0;
+}
+
+static struct file_operations mpc5200_wdt_fops = {
+ .owner = THIS_MODULE,
+ .write = mpc5200_wdt_write,
+ .ioctl = mpc5200_wdt_ioctl,
+ .open = mpc5200_wdt_open,
+ .release = mpc5200_wdt_release,
+};
+
+/* module operations */
+static int mpc5200_wdt_probe(struct of_device *op, const struct of_device_id *match)
+{
+ struct mpc5200_wdt *wdt;
+ int err;
+ const void *has_wdt;
+ int size;
+
+ has_wdt = of_get_property(op->node, "has-wdt", NULL);
+ if (!has_wdt)
+ return -ENODEV;
+
+ wdt = kzalloc(sizeof(*wdt), GFP_KERNEL);
+ if (!wdt)
+ return -ENOMEM;
+
+ wdt->ipb_freq = mpc52xx_find_ipb_freq(op->node);
+
+ err = of_address_to_resource(op->node, 0, &wdt->mem);
+ if (err)
+ goto out_free;
+ size = wdt->mem.end - wdt->mem.start + 1;
+ if (!request_mem_region(wdt->mem.start, size, "mpc5200_wdt")) {
+ err = -ENODEV;
+ goto out_free;
+ }
+ wdt->regs = ioremap(wdt->mem.start, size);
+ if (!wdt->regs) {
+ err = -ENODEV;
+ goto out_release;
+ }
+
+ dev_set_drvdata(&op->dev, wdt);
+ spin_lock_init(&wdt->io_lock);
+
+ wdt->miscdev = (struct miscdevice) {
+ .minor = WATCHDOG_MINOR,
+ .name = "watchdog",
+ .fops = &mpc5200_wdt_fops,
+ .parent = &op->dev,
+ };
+ wdt_global = wdt;
+ err = misc_register(&wdt->miscdev);
+ if (!err)
+ return 0;
+
+ iounmap(wdt->regs);
+ out_release:
+ release_mem_region(wdt->mem.start, size);
+ out_free:
+ kfree(wdt);
+ return err;
+}
+
+static int mpc5200_wdt_remove(struct of_device *op)
+{
+ struct mpc5200_wdt *wdt = dev_get_drvdata(&op->dev);
+
+ mpc5200_wdt_stop(wdt);
+ misc_deregister(&wdt->miscdev);
+ iounmap(wdt->regs);
+ release_mem_region(wdt->mem.start, wdt->mem.end - wdt->mem.start + 1);
+ kfree(wdt);
+
+ return 0;
+}
+static int mpc5200_wdt_suspend(struct of_device *op, pm_message_t state)
+{
+ struct mpc5200_wdt *wdt = dev_get_drvdata(&op->dev);
+ mpc5200_wdt_stop(wdt);
+ return 0;
+}
+static int mpc5200_wdt_resume(struct of_device *op)
+{
+ struct mpc5200_wdt *wdt = dev_get_drvdata(&op->dev);
+ if (wdt->count)
+ mpc5200_wdt_start(wdt);
+ return 0;
+}
+static int mpc5200_wdt_shutdown(struct of_device *op)
+{
+ struct mpc5200_wdt *wdt = dev_get_drvdata(&op->dev);
+ mpc5200_wdt_stop(wdt);
+ return 0;
+}
+
+static struct of_device_id mpc5200_wdt_match[] = {
+ { .compatible = "mpc5200-gpt", },
+ {},
+};
+static struct of_platform_driver mpc5200_wdt_driver = {
+ .owner = THIS_MODULE,
+ .name = "mpc5200-gpt-wdt",
+ .match_table = mpc5200_wdt_match,
+ .probe = mpc5200_wdt_probe,
+ .remove = mpc5200_wdt_remove,
+ .suspend = mpc5200_wdt_suspend,
+ .resume = mpc5200_wdt_resume,
+ .shutdown = mpc5200_wdt_shutdown,
+};
+
+
+static int __init mpc5200_wdt_init(void)
+{
+ return of_register_platform_driver(&mpc5200_wdt_driver);
+}
+
+static void __exit mpc5200_wdt_exit(void)
+{
+ of_unregister_platform_driver(&mpc5200_wdt_driver);
+}
+
+module_init(mpc5200_wdt_init);
+module_exit(mpc5200_wdt_exit);
+
+MODULE_AUTHOR("Domen Puncer <domen.puncer@telargo.com>");
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
+ case WDIOC_GETSTATUS:
+ case WDIOC_GETBOOTSTATUS:
+ return put_user(0, p);
case WDIOC_KEEPALIVE:
mpc83xx_wdt_keepalive();
return 0;
m8xx_wdt_reset();
mpc8xx_wdt_handler_disable();
- return 0;
+ return nonseekable_open(inode, file);
}
static int mpc8xx_wdt_release(struct inode *inode, struct file *file)
mtx1_wdt_reset();
break;
case WDIOC_GETSTATUS:
+ case WDIOC_GETBOOTSTATUS:
if ( copy_to_user(argp, &value, sizeof(int)) )
return -EFAULT;
break;
#include <linux/watchdog.h>
#include <linux/platform_device.h>
-#include <asm/mv64x60.h>
+#include <linux/mv643xx.h>
#include <asm/uaccess.h>
#include <asm/io.h>
-/* MV64x60 WDC (config) register access definitions */
-#define MV64x60_WDC_CTL1_MASK (3 << 24)
-#define MV64x60_WDC_CTL1(val) ((val & 3) << 24)
-#define MV64x60_WDC_CTL2_MASK (3 << 26)
-#define MV64x60_WDC_CTL2(val) ((val & 3) << 26)
+#define MV64x60_WDT_WDC_OFFSET 0
+
+/*
+ * The watchdog configuration register contains a pair of 2-bit fields,
+ * 1. a reload field, bits 27-26, which triggers a reload of
+ * the countdown register, and
+ * 2. an enable field, bits 25-24, which toggles between
+ * enabling and disabling the watchdog timer.
+ * Bit 31 is a read-only field which indicates whether the
+ * watchdog timer is currently enabled.
+ *
+ * The low 24 bits contain the timer reload value.
+ */
+#define MV64x60_WDC_ENABLE_SHIFT 24
+#define MV64x60_WDC_SERVICE_SHIFT 26
+#define MV64x60_WDC_ENABLED_SHIFT 31
+
+#define MV64x60_WDC_ENABLED_TRUE 1
+#define MV64x60_WDC_ENABLED_FALSE 0
/* Flags bits */
#define MV64x60_WDOG_FLAG_OPENED 0
-#define MV64x60_WDOG_FLAG_ENABLED 1
static unsigned long wdt_flags;
static int wdt_status;
-static void __iomem *mv64x60_regs;
+static void __iomem *mv64x60_wdt_regs;
static int mv64x60_wdt_timeout;
+static int mv64x60_wdt_count;
+static unsigned int bus_clk;
+static char expect_close;
+static DEFINE_SPINLOCK(mv64x60_wdt_spinlock);
+
+static int nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-static void mv64x60_wdt_reg_write(u32 val)
+static int mv64x60_wdt_toggle_wdc(int enabled_predicate, int field_shift)
{
- /* Allow write only to CTL1 / CTL2 fields, retaining values in
- * other fields.
- */
- u32 data = readl(mv64x60_regs + MV64x60_WDT_WDC);
- data &= ~(MV64x60_WDC_CTL1_MASK | MV64x60_WDC_CTL2_MASK);
- data |= val;
- writel(data, mv64x60_regs + MV64x60_WDT_WDC);
+ u32 data;
+ u32 enabled;
+ int ret = 0;
+
+ spin_lock(&mv64x60_wdt_spinlock);
+ data = readl(mv64x60_wdt_regs + MV64x60_WDT_WDC_OFFSET);
+ enabled = (data >> MV64x60_WDC_ENABLED_SHIFT) & 1;
+
+ /* only toggle the requested field if enabled state matches predicate */
+ if ((enabled ^ enabled_predicate) == 0) {
+ /* We write a 1, then a 2 -- to the appropriate field */
+ data = (1 << field_shift) | mv64x60_wdt_count;
+ writel(data, mv64x60_wdt_regs + MV64x60_WDT_WDC_OFFSET);
+
+ data = (2 << field_shift) | mv64x60_wdt_count;
+ writel(data, mv64x60_wdt_regs + MV64x60_WDT_WDC_OFFSET);
+ ret = 1;
+ }
+ spin_unlock(&mv64x60_wdt_spinlock);
+
+ return ret;
}
static void mv64x60_wdt_service(void)
{
- /* Write 01 followed by 10 to CTL2 */
- mv64x60_wdt_reg_write(MV64x60_WDC_CTL2(0x01));
- mv64x60_wdt_reg_write(MV64x60_WDC_CTL2(0x02));
+ mv64x60_wdt_toggle_wdc(MV64x60_WDC_ENABLED_TRUE,
+ MV64x60_WDC_SERVICE_SHIFT);
+}
+
+static void mv64x60_wdt_handler_enable(void)
+{
+ if (mv64x60_wdt_toggle_wdc(MV64x60_WDC_ENABLED_FALSE,
+ MV64x60_WDC_ENABLE_SHIFT)) {
+ mv64x60_wdt_service();
+ printk(KERN_NOTICE "mv64x60_wdt: watchdog activated\n");
+ }
}
static void mv64x60_wdt_handler_disable(void)
{
- if (test_and_clear_bit(MV64x60_WDOG_FLAG_ENABLED, &wdt_flags)) {
- /* Write 01 followed by 10 to CTL1 */
- mv64x60_wdt_reg_write(MV64x60_WDC_CTL1(0x01));
- mv64x60_wdt_reg_write(MV64x60_WDC_CTL1(0x02));
+ if (mv64x60_wdt_toggle_wdc(MV64x60_WDC_ENABLED_TRUE,
+ MV64x60_WDC_ENABLE_SHIFT))
printk(KERN_NOTICE "mv64x60_wdt: watchdog deactivated\n");
- }
}
-static void mv64x60_wdt_handler_enable(void)
+static void mv64x60_wdt_set_timeout(unsigned int timeout)
{
- if (!test_and_set_bit(MV64x60_WDOG_FLAG_ENABLED, &wdt_flags)) {
- /* Write 01 followed by 10 to CTL1 */
- mv64x60_wdt_reg_write(MV64x60_WDC_CTL1(0x01));
- mv64x60_wdt_reg_write(MV64x60_WDC_CTL1(0x02));
- printk(KERN_NOTICE "mv64x60_wdt: watchdog activated\n");
- }
+ /* maximum bus cycle count is 0xFFFFFFFF */
+ if (timeout > 0xFFFFFFFF / bus_clk)
+ timeout = 0xFFFFFFFF / bus_clk;
+
+ mv64x60_wdt_count = timeout * bus_clk >> 8;
+ mv64x60_wdt_timeout = timeout;
}
static int mv64x60_wdt_open(struct inode *inode, struct file *file)
if (test_and_set_bit(MV64x60_WDOG_FLAG_OPENED, &wdt_flags))
return -EBUSY;
- mv64x60_wdt_service();
- mv64x60_wdt_handler_enable();
+ if (nowayout)
+ __module_get(THIS_MODULE);
- nonseekable_open(inode, file);
+ mv64x60_wdt_handler_enable();
- return 0;
+ return nonseekable_open(inode, file);
}
static int mv64x60_wdt_release(struct inode *inode, struct file *file)
{
- mv64x60_wdt_service();
-
-#if !defined(CONFIG_WATCHDOG_NOWAYOUT)
- mv64x60_wdt_handler_disable();
-#endif
+ if (expect_close == 42)
+ mv64x60_wdt_handler_disable();
+ else {
+ printk(KERN_CRIT
+ "mv64x60_wdt: unexpected close, not stopping timer!\n");
+ mv64x60_wdt_service();
+ }
+ expect_close = 0;
clear_bit(MV64x60_WDOG_FLAG_OPENED, &wdt_flags);
static ssize_t mv64x60_wdt_write(struct file *file, const char __user *data,
size_t len, loff_t * ppos)
{
- if (len)
+ if (len) {
+ if (!nowayout) {
+ size_t i;
+
+ expect_close = 0;
+
+ for (i = 0; i != len; i++) {
+ char c;
+ if(get_user(c, data + i))
+ return -EFAULT;
+ if (c == 'V')
+ expect_close = 42;
+ }
+ }
mv64x60_wdt_service();
+ }
return len;
}
unsigned int cmd, unsigned long arg)
{
int timeout;
+ int options;
void __user *argp = (void __user *)arg;
static struct watchdog_info info = {
- .options = WDIOF_KEEPALIVEPING,
+ .options = WDIOF_SETTIMEOUT |
+ WDIOF_MAGICCLOSE |
+ WDIOF_KEEPALIVEPING,
.firmware_version = 0,
.identity = "MV64x60 watchdog",
};
return -EOPNOTSUPP;
case WDIOC_SETOPTIONS:
- return -EOPNOTSUPP;
+ if (get_user(options, (int __user *)argp))
+ return -EFAULT;
+
+ if (options & WDIOS_DISABLECARD)
+ mv64x60_wdt_handler_disable();
+
+ if (options & WDIOS_ENABLECARD)
+ mv64x60_wdt_handler_enable();
+ break;
case WDIOC_KEEPALIVE:
mv64x60_wdt_service();
break;
case WDIOC_SETTIMEOUT:
- return -EOPNOTSUPP;
+ if (get_user(timeout, (int __user *)argp))
+ return -EFAULT;
+ mv64x60_wdt_set_timeout(timeout);
+ /* Fall through */
case WDIOC_GETTIMEOUT:
- timeout = mv64x60_wdt_timeout * HZ;
- if (put_user(timeout, (int __user *)argp))
+ if (put_user(mv64x60_wdt_timeout, (int __user *)argp))
return -EFAULT;
break;
static int __devinit mv64x60_wdt_probe(struct platform_device *dev)
{
struct mv64x60_wdt_pdata *pdata = dev->dev.platform_data;
- int bus_clk = 133;
+ struct resource *r;
+ int timeout = 10;
- mv64x60_wdt_timeout = 10;
+ bus_clk = 133; /* in MHz */
if (pdata) {
- mv64x60_wdt_timeout = pdata->timeout;
+ timeout = pdata->timeout;
bus_clk = pdata->bus_clk;
}
- mv64x60_regs = mv64x60_get_bridge_vbase();
+ /* Since bus_clk is truncated MHz, actual frequency could be
+ * up to 1MHz higher. Round up, since it's better to time out
+ * too late than too soon.
+ */
+ bus_clk++;
+ bus_clk *= 1000000; /* convert to Hz */
+
+ r = platform_get_resource(dev, IORESOURCE_MEM, 0);
+ if (!r)
+ return -ENODEV;
- writel((mv64x60_wdt_timeout * (bus_clk * 1000000)) >> 8,
- mv64x60_regs + MV64x60_WDT_WDC);
+ mv64x60_wdt_regs = ioremap(r->start, r->end - r->start + 1);
+ if (mv64x60_wdt_regs == NULL)
+ return -ENOMEM;
+
+ mv64x60_wdt_set_timeout(timeout);
+
+ mv64x60_wdt_handler_disable(); /* in case timer was already running */
return misc_register(&mv64x60_wdt_miscdev);
}
{
misc_deregister(&mv64x60_wdt_miscdev);
- mv64x60_wdt_service();
mv64x60_wdt_handler_disable();
+ iounmap(mv64x60_wdt_regs);
+
return 0;
}
},
};
-static struct platform_device *mv64x60_wdt_dev;
-
static int __init mv64x60_wdt_init(void)
{
- int ret;
-
printk(KERN_INFO "MV64x60 watchdog driver\n");
- mv64x60_wdt_dev = platform_device_alloc(MV64x60_WDT_NAME, -1);
- if (!mv64x60_wdt_dev) {
- ret = -ENOMEM;
- goto out;
- }
-
- ret = platform_device_add(mv64x60_wdt_dev);
- if (ret) {
- platform_device_put(mv64x60_wdt_dev);
- goto out;
- }
-
- ret = platform_driver_register(&mv64x60_wdt_driver);
- if (ret) {
- platform_device_unregister(mv64x60_wdt_dev);
- goto out;
- }
-
- out:
- return ret;
+ return platform_driver_register(&mv64x60_wdt_driver);
}
static void __exit mv64x60_wdt_exit(void)
{
platform_driver_unregister(&mv64x60_wdt_driver);
- platform_device_unregister(mv64x60_wdt_dev);
}
module_init(mv64x60_wdt_init);
omap_wdt_set_timeout();
omap_wdt_enable();
- return 0;
+ return nonseekable_open(inode, file);
}
static int omap_wdt_release(struct inode *inode, struct file *file)
switch (cmd) {
default:
- return -ENOIOCTLCMD;
+ return -ENOTTY;
case WDIOC_GETSUPPORT:
return copy_to_user((struct watchdog_info __user *)arg, &ident,
sizeof(ident));
#include <asm/arch/map.h>
-#undef S3C24XX_VA_WATCHDOG
-#define S3C24XX_VA_WATCHDOG (0)
+#undef S3C_VA_WATCHDOG
+#define S3C_VA_WATCHDOG (0)
-#include <asm/arch/regs-watchdog.h>
+#include <asm/plat-s3c/regs-watchdog.h>
#define PFX "s3c2410-wdt: "
*/
static int sa1100dog_open(struct inode *inode, struct file *file)
{
- nonseekable_open(inode, file);
if (test_and_set_bit(1,&sa1100wdt_users))
return -EBUSY;
OSSR = OSSR_M3;
OWER = OWER_WME;
OIER |= OIER_E3;
- return 0;
+ return nonseekable_open(inode, file);
}
/*
static int fop_open(struct inode * inode, struct file * file)
{
- nonseekable_open(inode, file);
-
/* Just in case we're already talking to someone... */
if(test_and_set_bit(0, &wdt_is_open))
return -EBUSY;
/* Good, fire up the show */
wdt_startup();
- return 0;
+ return nonseekable_open(inode, file);
}
static int fop_close(struct inode * inode, struct file * file)
static int sc1200wdt_open(struct inode *inode, struct file *file)
{
- nonseekable_open(inode, file);
-
/* allow one at a time */
if (down_trylock(&open_sem))
return -EBUSY;
sc1200wdt_start();
printk(KERN_INFO PFX "Watchdog enabled, timeout = %d min(s)", timeout);
- return 0;
+ return nonseekable_open(inode, file);
}
static int fop_open(struct inode * inode, struct file * file)
{
- nonseekable_open(inode, file);
-
/* Just in case we're already talking to someone... */
if(test_and_set_bit(0, &wdt_is_open))
return -EBUSY;
/* Good, fire up the show */
wdt_startup();
- return 0;
+ return nonseekable_open(inode, file);
}
static int fop_close(struct inode * inode, struct file * file)
* (c) Copyright 2007 Vlad Drukker <vlad@storewiz.com>
* added support for W83627THF.
*
- * (c) Copyright 2003 Pádraig Brady <P@draigBrady.com>
+ * (c) Copyright 2003
,2007 Pádraig Brady <P@draigBrady.com>
*
* Based on advantechwdt.c which is based on wdt.c.
* Original copyright messages:
#include <asm/uaccess.h>
#include <asm/system.h>
-#define WATCHDOG_NAME "w83627hf/thf WDT"
+#define WATCHDOG_NAME "w83627hf/thf/hg WDT"
#define PFX WATCHDOG_NAME ": "
#define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */
static int timeout = WATCHDOG_TIMEOUT; /* in seconds */
module_param(timeout, int, 0);
-MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=63, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ".");
+MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=255, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ".");
static int nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, int, 0);
outb_p(0x87, WDT_EFER); /* Enter extended function mode */
outb_p(0x87, WDT_EFER); /* Again according to manual */
- outb(0x20, WDT_EFER); /* check chip version */
+ outb(0x20, WDT_EFER); /* check chip version */
c = inb(WDT_EFDR);
- if (c == 0x82) { /* W83627THF */
+ if (c == 0x82) { /* W83627THF */
outb_p(0x2b, WDT_EFER); /* select GPIO3 */
c = ((inb_p(WDT_EFDR) & 0xf7) | 0x04); /* select WDT0 */
outb_p(0x2b, WDT_EFER);
printk (KERN_INFO PFX "Watchdog already running. Resetting timeout to %d sec\n", timeout);
outb_p(timeout, WDT_EFDR); /* Write back to CRF6 */
}
+
outb_p(0xF5, WDT_EFER); /* Select CRF5 */
t=inb_p(WDT_EFDR); /* read CRF5 */
t&=~0x0C; /* set second mode & disable keyboard turning off watchdog */
outb_p(t, WDT_EFDR); /* Write back to CRF5 */
+ outb_p(0xF7, WDT_EFER); /* Select CRF7 */
+ t=inb_p(WDT_EFDR); /* read CRF7 */
+ t&=~0xC0; /* disable keyboard & mouse turning off watchdog */
+ outb_p(t, WDT_EFDR); /* Write back to CRF7 */
+
w83627hf_unselect_wd_register();
}
wdt_ctrl(int timeout)
{
spin_lock(&io_lock);
-
+
w83627hf_select_wd_register();
outb_p(0xF6, WDT_EFER); /* Select CRF6 */
static int
wdt_set_heartbeat(int t)
{
- if ((t < 1) || (t > 63))
+ if ((t < 1) || (t > 255))
return -EINVAL;
timeout = t;
spin_lock_init(&io_lock);
- printk(KERN_INFO "WDT driver for the Winbond(TM) W83627HF/THF Super I/O chip initialising.\n");
+ printk(KERN_INFO "WDT driver for the Winbond(TM) W83627HF/THF/HG Super I/O chip initialising.\n");
if (wdt_set_heartbeat(timeout)) {
wdt_set_heartbeat(WATCHDOG_TIMEOUT);
- printk (KERN_INFO PFX "timeout value must be 1<=timeout<=63, using %d\n",
+ printk (KERN_INFO PFX "timeout value must be 1<=timeout<=255, using %d\n",
WATCHDOG_TIMEOUT);
}
hid->quirks = quirks;
if (!(usbhid = kzalloc(sizeof(struct usbhid_device), GFP_KERNEL)))
- goto fail;
+ goto fail_no_usbhid;
hid->driver_data = usbhid;
usbhid->hid = hid;
usb_free_urb(usbhid->urbout);
usb_free_urb(usbhid->urbctrl);
hid_free_buffers(dev, hid);
+ kfree(usbhid);
+fail_no_usbhid:
hid_free_device(hid);
return NULL;
usb_free_urb(usbhid->urbout);
hid_free_buffers(hid_to_usb_dev(hid), hid);
+ kfree(usbhid);
hid_free_device(hid);
}
#define USB_DEVICE_ID_APPLE_GEYSER4_JIS 0x021c
#define USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY 0x030a
#define USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY 0x030b
-#define USB_DEVICE_ID_APPLE_IR 0x8240
+
+#define USB_VENDOR_ID_ASUS 0x0b05
+#define USB_DEVICE_ID_ASUS_LCM 0x1726
#define USB_VENDOR_ID_ATEN 0x0557
#define USB_DEVICE_ID_ATEN_UC100KM 0x2004
#define USB_VENDOR_ID_LOGITECH 0x046d
#define USB_DEVICE_ID_LOGITECH_RECEIVER 0xc101
+#define USB_DEVICE_ID_LOGITECH_HARMONY 0xc110
+#define USB_DEVICE_ID_LOGITECH_HARMONY_2 0xc111
+#define USB_DEVICE_ID_LOGITECH_HARMONY_3 0xc112
+#define USB_DEVICE_ID_LOGITECH_HARMONY_4 0xc113
+#define USB_DEVICE_ID_LOGITECH_HARMONY_5 0xc114
+#define USB_DEVICE_ID_LOGITECH_HARMONY_6 0xc115
+#define USB_DEVICE_ID_LOGITECH_HARMONY_7 0xc116
+#define USB_DEVICE_ID_LOGITECH_HARMONY_8 0xc117
+#define USB_DEVICE_ID_LOGITECH_HARMONY_9 0xc118
+#define USB_DEVICE_ID_LOGITECH_HARMONY_10 0xc119
+#define USB_DEVICE_ID_LOGITECH_HARMONY_11 0xc11a
+#define USB_DEVICE_ID_LOGITECH_HARMONY_12 0xc11b
+#define USB_DEVICE_ID_LOGITECH_HARMONY_13 0xc11c
+#define USB_DEVICE_ID_LOGITECH_HARMONY_14 0xc11d
+#define USB_DEVICE_ID_LOGITECH_HARMONY_15 0xc11e
+#define USB_DEVICE_ID_LOGITECH_HARMONY_16 0xc11f
+#define USB_DEVICE_ID_LOGITECH_HARMONY_17 0xc120
+#define USB_DEVICE_ID_LOGITECH_HARMONY_18 0xc121
+#define USB_DEVICE_ID_LOGITECH_HARMONY_19 0xc122
+#define USB_DEVICE_ID_LOGITECH_HARMONY_20 0xc123
+#define USB_DEVICE_ID_LOGITECH_HARMONY_21 0xc124
+#define USB_DEVICE_ID_LOGITECH_HARMONY_22 0xc125
+#define USB_DEVICE_ID_LOGITECH_HARMONY_23 0xc126
+#define USB_DEVICE_ID_LOGITECH_HARMONY_24 0xc127
+#define USB_DEVICE_ID_LOGITECH_HARMONY_25 0xc128
+#define USB_DEVICE_ID_LOGITECH_HARMONY_26 0xc129
+#define USB_DEVICE_ID_LOGITECH_HARMONY_27 0xc12a
+#define USB_DEVICE_ID_LOGITECH_HARMONY_28 0xc12b
+#define USB_DEVICE_ID_LOGITECH_HARMONY_29 0xc12c
+#define USB_DEVICE_ID_LOGITECH_HARMONY_30 0xc12d
+#define USB_DEVICE_ID_LOGITECH_HARMONY_31 0xc12e
+#define USB_DEVICE_ID_LOGITECH_HARMONY_32 0xc12f
+#define USB_DEVICE_ID_LOGITECH_HARMONY_33 0xc130
+#define USB_DEVICE_ID_LOGITECH_HARMONY_34 0xc131
+#define USB_DEVICE_ID_LOGITECH_HARMONY_35 0xc132
+#define USB_DEVICE_ID_LOGITECH_HARMONY_36 0xc133
+#define USB_DEVICE_ID_LOGITECH_HARMONY_37 0xc134
+#define USB_DEVICE_ID_LOGITECH_HARMONY_38 0xc135
+#define USB_DEVICE_ID_LOGITECH_HARMONY_39 0xc136
+#define USB_DEVICE_ID_LOGITECH_HARMONY_40 0xc137
+#define USB_DEVICE_ID_LOGITECH_HARMONY_41 0xc138
+#define USB_DEVICE_ID_LOGITECH_HARMONY_42 0xc139
+#define USB_DEVICE_ID_LOGITECH_HARMONY_43 0xc13a
+#define USB_DEVICE_ID_LOGITECH_HARMONY_44 0xc13b
+#define USB_DEVICE_ID_LOGITECH_HARMONY_45 0xc13c
+#define USB_DEVICE_ID_LOGITECH_HARMONY_46 0xc13d
+#define USB_DEVICE_ID_LOGITECH_HARMONY_47 0xc13e
+#define USB_DEVICE_ID_LOGITECH_HARMONY_48 0xc13f
+#define USB_DEVICE_ID_LOGITECH_HARMONY_49 0xc140
+#define USB_DEVICE_ID_LOGITECH_HARMONY_50 0xc141
+#define USB_DEVICE_ID_LOGITECH_HARMONY_51 0xc142
+#define USB_DEVICE_ID_LOGITECH_HARMONY_52 0xc143
+#define USB_DEVICE_ID_LOGITECH_HARMONY_53 0xc144
+#define USB_DEVICE_ID_LOGITECH_HARMONY_54 0xc145
+#define USB_DEVICE_ID_LOGITECH_HARMONY_55 0xc146
+#define USB_DEVICE_ID_LOGITECH_HARMONY_56 0xc147
+#define USB_DEVICE_ID_LOGITECH_HARMONY_57 0xc148
+#define USB_DEVICE_ID_LOGITECH_HARMONY_58 0xc149
+#define USB_DEVICE_ID_LOGITECH_HARMONY_59 0xc14a
+#define USB_DEVICE_ID_LOGITECH_HARMONY_60 0xc14b
+#define USB_DEVICE_ID_LOGITECH_HARMONY_61 0xc14c
+#define USB_DEVICE_ID_LOGITECH_HARMONY_62 0xc14d
+#define USB_DEVICE_ID_LOGITECH_HARMONY_63 0xc14e
+#define USB_DEVICE_ID_LOGITECH_HARMONY_64 0xc14f
#define USB_DEVICE_ID_LOGITECH_WHEEL 0xc294
#define USB_DEVICE_ID_LOGITECH_KBD 0xc311
#define USB_DEVICE_ID_S510_RECEIVER 0xc50c
#define USB_DEVICE_ID_NCR_FIRST 0x0300
#define USB_DEVICE_ID_NCR_LAST 0x03ff
+#define USB_VENDOR_ID_NATIONAL_SEMICONDUCTOR 0x0400
+#define USB_DEVICE_ID_N_S_HARMONY 0xc359
+
#define USB_VENDOR_ID_NEC 0x073e
#define USB_DEVICE_ID_NEC_USB_GAME_PAD 0x0301
{ USB_VENDOR_ID_AIPTEK, USB_DEVICE_ID_AIPTEK_24, HID_QUIRK_IGNORE },
{ USB_VENDOR_ID_AIRCABLE, USB_DEVICE_ID_AIRCABLE1, HID_QUIRK_IGNORE },
{ USB_VENDOR_ID_ALCOR, USB_DEVICE_ID_ALCOR_USBRS232, HID_QUIRK_IGNORE },
- { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_IR, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_ASUS, USB_DEVICE_ID_ASUS_LCM, HID_QUIRK_IGNORE},
{ USB_VENDOR_ID_BERKSHIRE, USB_DEVICE_ID_BERKSHIRE_PCWD, HID_QUIRK_IGNORE },
{ USB_VENDOR_ID_CIDC, 0x0103, HID_QUIRK_IGNORE },
{ USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_HIDCOM, HID_QUIRK_IGNORE },
{ USB_VENDOR_ID_DELL, USB_DEVICE_ID_DELL_W7658, HID_QUIRK_RESET_LEDS },
{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_KBD, HID_QUIRK_RESET_LEDS },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_2, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_3, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_4, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_5, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_6, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_7, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_8, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_9, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_10, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_11, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_12, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_13, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_14, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_15, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_16, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_17, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_18, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_19, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_20, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_21, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_22, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_23, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_24, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_25, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_26, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_27, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_28, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_29, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_30, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_31, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_32, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_33, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_34, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_35, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_36, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_37, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_38, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_39, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_40, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_41, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_42, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_43, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_44, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_45, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_46, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_47, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_48, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_49, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_50, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_51, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_52, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_53, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_54, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_55, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_56, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_57, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_58, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_59, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_60, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_61, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_62, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_63, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_64, HID_QUIRK_IGNORE },
+ { USB_VENDOR_ID_NATIONAL_SEMICONDUCTOR, USB_DEVICE_ID_N_S_HARMONY, HID_QUIRK_IGNORE },
{ 0, 0 }
};
This driver can also be built as a module. If so, the module
will be called smsc47b397.
+config SENSORS_THMC50
+ tristate "Texas Instruments THMC50 / Analog Devices ADM1022"
+ depends on I2C && EXPERIMENTAL
+ help
+ If you say yes here you get support for Texas Instruments THMC50
+ sensor chips and clones: the Analog Devices ADM1022.
+
+ This driver can also be built as a module. If so, the module
+ will be called thmc50.
+
config SENSORS_VIA686A
tristate "VIA686A"
depends on PCI
obj-$(CONFIG_SENSORS_SMSC47B397)+= smsc47b397.o
obj-$(CONFIG_SENSORS_SMSC47M1) += smsc47m1.o
obj-$(CONFIG_SENSORS_SMSC47M192)+= smsc47m192.o
+obj-$(CONFIG_SENSORS_THMC50) += thmc50.o
obj-$(CONFIG_SENSORS_VIA686A) += via686a.o
obj-$(CONFIG_SENSORS_VT1211) += vt1211.o
obj-$(CONFIG_SENSORS_VT8231) += vt8231.o
/* Sensor settings are stored 1 byte per offset with the bytes
placed add consecutive offsets. */
-int abituguru3_read_increment_offset(struct abituguru3_data *data, u8 bank,
- u8 offset, u8 count, u8 *buf, int offset_count)
+static int abituguru3_read_increment_offset(struct abituguru3_data *data,
+ u8 bank, u8 offset, u8 count,
+ u8 *buf, int offset_count)
{
int i, x;
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/init.h>
-#include <linux/module.h>
#include <asm/pmac_pfunc.h>
#include <asm/of_platform.h>
/*
* Temperature sensors keys (sp78 - 2 bytes).
- * First set for Macbook(Pro), second for Macmini.
*/
static const char* temperature_sensors_sets[][13] = {
+/* Set 0: Macbook Pro */
{ "TA0P", "TB0T", "TC0D", "TC0P", "TG0H", "TG0P", "TG0T", "Th0H",
"Th1H", "Tm0P", "Ts0P", "Ts1P", NULL },
+/* Set 1: Macbook set */
+ { "TB0T", "TC0D", "TC0P", "TM0P", "TN0P", "TN1P", "Th0H", "Th0S",
+ "Th1H", "Ts0P", NULL },
+/* Set 2: Macmini set */
{ "TC0D", "TC0P", NULL }
};
static __initdata struct dmi_match_data applesmc_dmi_data[] = {
/* MacBook Pro: accelerometer, backlight and temperature set 0 */
{ .accelerometer = 1, .light = 1, .temperature_set = 0 },
-/* MacBook: accelerometer and temperature set 0 */
- { .accelerometer = 1, .light = 0, .temperature_set = 0 },
-/* MacBook: temperature set 1 */
- { .accelerometer = 0, .light = 0, .temperature_set = 1 }
+/* MacBook: accelerometer and temperature set 1 */
+ { .accelerometer = 1, .light = 0, .temperature_set = 1 },
+/* MacMini: temperature set 2 */
+ { .accelerometer = 0, .light = 0, .temperature_set = 2 },
};
/* Note that DMI_MATCH(...,"MacBook") will match "MacBookPro1,1".
res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01;
break;
case SYS_TEMP_FAULT:
- res = (data->temp[ix] == 0x0800);
+ res = (((u16)data->temp[ix] & 0xff00) == 0x8000);
break;
default:
res = 0;
data->watchdog[2] = fscher_read_value(client, FSCHER_REG_WDOG_CONTROL);
data->global_event = fscher_read_value(client, FSCHER_REG_EVENT_STATE);
+ data->global_control = fscher_read_value(client,
+ FSCHER_REG_CONTROL);
data->last_updated = jiffies;
data->valid = 1;
unsigned long v = simple_strtoul(buf, NULL, 10) & 0x01;
mutex_lock(&data->update_lock);
- data->global_control &= ~v;
+ data->global_control = v;
fscher_write_value(client, reg, v);
mutex_unlock(&data->update_lock);
return count;
static int it87_probe(struct platform_device *pdev);
-static int it87_remove(struct platform_device *pdev);
+static int __devexit it87_remove(struct platform_device *pdev);
static int it87_read_value(struct it87_data *data, u8 reg);
static void it87_write_value(struct it87_data *data, u8 reg, u8 value);
/* Determine the chip type */
outb_p(LM78_REG_CHIPID, address + LM78_ADDR_REG_OFFSET);
val = inb_p(address + LM78_DATA_REG_OFFSET);
- if (val == 0x00 /* LM78 */
+ if (val == 0x00 || val == 0x20 /* LM78 */
|| val == 0x40 /* LM78-J */
|| (val & 0xfe) == 0xc0) /* LM79 */
found = 1;
* those of the man_id register.
*/
if (chip_id == man_id
- && (address == 0x4F || address == 0x4D)
+ && (address == 0x4C || address == 0x4D)
&& (reg_config1 & 0x1F) == (man_id & 0x0F)
&& reg_convrate <= 0x09) {
kind = max6657;
struct {
u8 min;
u8 max;
- } temp_lim[3];
+ } temp_lim[4];
/* vin1 - vin16: low and high limits */
struct {
*/
static int pc87360_probe(struct platform_device *pdev);
-static int pc87360_remove(struct platform_device *pdev);
+static int __devexit pc87360_remove(struct platform_device *pdev);
static int pc87360_read_value(struct pc87360_data *data, u8 ldi, u8 bank,
u8 reg);
static struct pci_dev *s_bridge; /* pointer to the (only) sis5595 */
static int sis5595_probe(struct platform_device *pdev);
-static int sis5595_remove(struct platform_device *pdev);
+static int __devexit sis5595_remove(struct platform_device *pdev);
static int sis5595_read_value(struct sis5595_data *data, u8 reg);
static void sis5595_write_value(struct sis5595_data *data, u8 reg, u8 value);
static int smsc47m1_probe(struct platform_device *pdev);
-static int smsc47m1_remove(struct platform_device *pdev);
+static int __devexit smsc47m1_remove(struct platform_device *pdev);
static struct smsc47m1_data *smsc47m1_update_device(struct device *dev,
int init);
--- /dev/null
+/*
+ thmc50.c - Part of lm_sensors, Linux kernel modules for hardware
+ monitoring
+ Copyright (C) 2007 Krzysztof Helt <krzysztof.h1@wp.pl>
+ Based on 2.4 driver by Frodo Looijaard <frodol@dds.nl> and
+ Philip Edelbrock <phil@netroedge.com>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/err.h>
+#include <linux/mutex.h>
+
+MODULE_LICENSE("GPL");
+
+/* Addresses to scan */
+static unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, I2C_CLIENT_END };
+
+/* Insmod parameters */
+I2C_CLIENT_INSMOD_2(thmc50, adm1022);
+I2C_CLIENT_MODULE_PARM(adm1022_temp3, "List of adapter,address pairs "
+ "to enable 3rd temperature (ADM1022 only)");
+
+/* Many THMC50 constants specified below */
+
+/* The THMC50 registers */
+#define THMC50_REG_CONF 0x40
+#define THMC50_REG_COMPANY_ID 0x3E
+#define THMC50_REG_DIE_CODE 0x3F
+#define THMC50_REG_ANALOG_OUT 0x19
+
+const static u8 THMC50_REG_TEMP[] = { 0x27, 0x26, 0x20 };
+const static u8 THMC50_REG_TEMP_MIN[] = { 0x3A, 0x38, 0x2C };
+const static u8 THMC50_REG_TEMP_MAX[] = { 0x39, 0x37, 0x2B };
+
+#define THMC50_REG_CONF_nFANOFF 0x20
+
+/* Each client has this additional data */
+struct thmc50_data {
+ struct i2c_client client;
+ struct class_device *class_dev;
+
+ struct mutex update_lock;
+ enum chips type;
+ unsigned long last_updated; /* In jiffies */
+ char has_temp3; /* !=0 if it is ADM1022 in temp3 mode */
+ char valid; /* !=0 if following fields are valid */
+
+ /* Register values */
+ s8 temp_input[3];
+ s8 temp_max[3];
+ s8 temp_min[3];
+ u8 analog_out;
+};
+
+static int thmc50_attach_adapter(struct i2c_adapter *adapter);
+static int thmc50_detach_client(struct i2c_client *client);
+static void thmc50_init_client(struct i2c_client *client);
+static struct thmc50_data *thmc50_update_device(struct device *dev);
+
+static struct i2c_driver thmc50_driver = {
+ .driver = {
+ .name = "thmc50",
+ },
+ .attach_adapter = thmc50_attach_adapter,
+ .detach_client = thmc50_detach_client,
+};
+
+static ssize_t show_analog_out(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct thmc50_data *data = thmc50_update_device(dev);
+ return sprintf(buf, "%d\n", data->analog_out);
+}
+
+static ssize_t set_analog_out(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct thmc50_data *data = i2c_get_clientdata(client);
+ int tmp = simple_strtoul(buf, NULL, 10);
+ int config;
+
+ mutex_lock(&data->update_lock);
+ data->analog_out = SENSORS_LIMIT(tmp, 0, 255);
+ i2c_smbus_write_byte_data(client, THMC50_REG_ANALOG_OUT,
+ data->analog_out);
+
+ config = i2c_smbus_read_byte_data(client, THMC50_REG_CONF);
+ if (data->analog_out == 0)
+ config &= ~THMC50_REG_CONF_nFANOFF;
+ else
+ config |= THMC50_REG_CONF_nFANOFF;
+ i2c_smbus_write_byte_data(client, THMC50_REG_CONF, config);
+
+ mutex_unlock(&data->update_lock);
+ return count;
+}
+
+/* There is only one PWM mode = DC */
+static ssize_t show_pwm_mode(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "0\n");
+}
+
+/* Temperatures */
+static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ int nr = to_sensor_dev_attr(attr)->index;
+ struct thmc50_data *data = thmc50_update_device(dev);
+ return sprintf(buf, "%d\n", data->temp_input[nr] * 1000);
+}
+
+static ssize_t show_temp_min(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ int nr = to_sensor_dev_attr(attr)->index;
+ struct thmc50_data *data = thmc50_update_device(dev);
+ return sprintf(buf, "%d\n", data->temp_min[nr] * 1000);
+}
+
+static ssize_t set_temp_min(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ int nr = to_sensor_dev_attr(attr)->index;
+ struct i2c_client *client = to_i2c_client(dev);
+ struct thmc50_data *data = i2c_get_clientdata(client);
+ int val = simple_strtol(buf, NULL, 10);
+
+ mutex_lock(&data->update_lock);
+ data->temp_min[nr] = SENSORS_LIMIT(val / 1000, -128, 127);
+ i2c_smbus_write_byte_data(client, THMC50_REG_TEMP_MIN[nr],
+ data->temp_min[nr]);
+ mutex_unlock(&data->update_lock);
+ return count;
+}
+
+static ssize_t show_temp_max(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ int nr = to_sensor_dev_attr(attr)->index;
+ struct thmc50_data *data = thmc50_update_device(dev);
+ return sprintf(buf, "%d\n", data->temp_max[nr] * 1000);
+}
+
+static ssize_t set_temp_max(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ int nr = to_sensor_dev_attr(attr)->index;
+ struct i2c_client *client = to_i2c_client(dev);
+ struct thmc50_data *data = i2c_get_clientdata(client);
+ int val = simple_strtol(buf, NULL, 10);
+
+ mutex_lock(&data->update_lock);
+ data->temp_max[nr] = SENSORS_LIMIT(val / 1000, -128, 127);
+ i2c_smbus_write_byte_data(client, THMC50_REG_TEMP_MAX[nr],
+ data->temp_max[nr]);
+ mutex_unlock(&data->update_lock);
+ return count;
+}
+
+#define temp_reg(offset) \
+static SENSOR_DEVICE_ATTR(temp##offset##_input, S_IRUGO, show_temp, \
+ NULL, offset - 1); \
+static SENSOR_DEVICE_ATTR(temp##offset##_min, S_IRUGO | S_IWUSR, \
+ show_temp_min, set_temp_min, offset - 1); \
+static SENSOR_DEVICE_ATTR(temp##offset##_max, S_IRUGO | S_IWUSR, \
+ show_temp_max, set_temp_max, offset - 1);
+
+temp_reg(1);
+temp_reg(2);
+temp_reg(3);
+
+static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_analog_out,
+ set_analog_out, 0);
+static SENSOR_DEVICE_ATTR(pwm1_mode, S_IRUGO, show_pwm_mode, NULL, 0);
+
+static struct attribute *thmc50_attributes[] = {
+ &sensor_dev_attr_temp1_max.dev_attr.attr,
+ &sensor_dev_attr_temp1_min.dev_attr.attr,
+ &sensor_dev_attr_temp1_input.dev_attr.attr,
+ &sensor_dev_attr_temp2_max.dev_attr.attr,
+ &sensor_dev_attr_temp2_min.dev_attr.attr,
+ &sensor_dev_attr_temp2_input.dev_attr.attr,
+ &sensor_dev_attr_pwm1.dev_attr.attr,
+ &sensor_dev_attr_pwm1_mode.dev_attr.attr,
+ NULL
+};
+
+static const struct attribute_group thmc50_group = {
+ .attrs = thmc50_attributes,
+};
+
+/* for ADM1022 3rd temperature mode */
+static struct attribute *adm1022_attributes[] = {
+ &sensor_dev_attr_temp3_max.dev_attr.attr,
+ &sensor_dev_attr_temp3_min.dev_attr.attr,
+ &sensor_dev_attr_temp3_input.dev_attr.attr,
+ NULL
+};
+
+static const struct attribute_group adm1022_group = {
+ .attrs = adm1022_attributes,
+};
+
+static int thmc50_detect(struct i2c_adapter *adapter, int address, int kind)
+{
+ unsigned company;
+ unsigned revision;
+ unsigned config;
+ struct i2c_client *client;
+ struct thmc50_data *data;
+ struct device *dev;
+ int err = 0;
+ const char *type_name = "";
+
+ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
+ pr_debug("thmc50: detect failed, "
+ "smbus byte data not supported!\n");
+ goto exit;
+ }
+
+ /* OK. For now, we presume we have a valid client. We now create the
+ client structure, even though we cannot fill it completely yet.
+ But it allows us to access thmc50 registers. */
+ if (!(data = kzalloc(sizeof(struct thmc50_data), GFP_KERNEL))) {
+ pr_debug("thmc50: detect failed, kzalloc failed!\n");
+ err = -ENOMEM;
+ goto exit;
+ }
+
+ client = &data->client;
+ i2c_set_clientdata(client, data);
+ client->addr = address;
+ client->adapter = adapter;
+ client->driver = &thmc50_driver;
+ dev = &client->dev;
+
+ pr_debug("thmc50: Probing for THMC50 at 0x%2X on bus %d\n",
+ client->addr, i2c_adapter_id(client->adapter));
+
+ /* Now, we do the remaining detection. */
+ company = i2c_smbus_read_byte_data(client, THMC50_REG_COMPANY_ID);
+ revision = i2c_smbus_read_byte_data(client, THMC50_REG_DIE_CODE);
+ config = i2c_smbus_read_byte_data(client, THMC50_REG_CONF);
+
+ if (kind == 0)
+ kind = thmc50;
+ else if (kind < 0) {
+ err = -ENODEV;
+ if (revision >= 0xc0 && ((config & 0x10) == 0)) {
+ if (company == 0x49) {
+ kind = thmc50;
+ err = 0;
+ } else if (company == 0x41) {
+ kind = adm1022;
+ err = 0;
+ }
+ }
+ }
+ if (err == -ENODEV) {
+ pr_debug("thmc50: Detection of THMC50/ADM1022 failed\n");
+ goto exit_free;
+ }
+ pr_debug("thmc50: Detected %s (version %x, revision %x)\n",
+ type_name, (revision >> 4) - 0xc, revision & 0xf);
+ data->type = kind;
+
+ if (kind == thmc50)
+ type_name = "thmc50";
+ else if (kind == adm1022) {
+ int id = i2c_adapter_id(client->adapter);
+ int i;
+
+ type_name = "adm1022";
+ data->has_temp3 = (config >> 7) & 1; /* config MSB */
+ for (i = 0; i + 1 < adm1022_temp3_num; i += 2)
+ if (adm1022_temp3[i] == id &&
+ adm1022_temp3[i + 1] == address) {
+ /* enable 2nd remote temp */
+ data->has_temp3 = 1;
+ break;
+ }
+ }
+
+ /* Fill in the remaining client fields & put it into the global list */
+ strlcpy(client->name, type_name, I2C_NAME_SIZE);
+ mutex_init(&data->update_lock);
+
+ /* Tell the I2C layer a new client has arrived */
+ if ((err = i2c_attach_client(client)))
+ goto exit_free;
+
+ thmc50_init_client(client);
+
+ /* Register sysfs hooks */
+ if ((err = sysfs_create_group(&client->dev.kobj, &thmc50_group)))
+ goto exit_detach;
+
+ /* Register ADM1022 sysfs hooks */
+ if (data->type == adm1022)
+ if ((err = sysfs_create_group(&client->dev.kobj,
+ &adm1022_group)))
+ goto exit_remove_sysfs_thmc50;
+
+ /* Register a new directory entry with module sensors */
+ data->class_dev = hwmon_device_register(&client->dev);
+ if (IS_ERR(data->class_dev)) {
+ err = PTR_ERR(data->class_dev);
+ goto exit_remove_sysfs;
+ }
+
+ return 0;
+
+exit_remove_sysfs:
+ if (data->type == adm1022)
+ sysfs_remove_group(&client->dev.kobj, &adm1022_group);
+exit_remove_sysfs_thmc50:
+ sysfs_remove_group(&client->dev.kobj, &thmc50_group);
+exit_detach:
+ i2c_detach_client(client);
+exit_free:
+ kfree(data);
+exit:
+ return err;
+}
+
+static int thmc50_attach_adapter(struct i2c_adapter *adapter)
+{
+ if (!(adapter->class & I2C_CLASS_HWMON))
+ return 0;
+ return i2c_probe(adapter, &addr_data, thmc50_detect);
+}
+
+static int thmc50_detach_client(struct i2c_client *client)
+{
+ struct thmc50_data *data = i2c_get_clientdata(client);
+ int err;
+
+ hwmon_device_unregister(data->class_dev);
+ sysfs_remove_group(&client->dev.kobj, &thmc50_group);
+ if (data->type == adm1022)
+ sysfs_remove_group(&client->dev.kobj, &adm1022_group);
+
+ if ((err = i2c_detach_client(client)))
+ return err;
+
+ kfree(data);
+
+ return 0;
+}
+
+static void thmc50_init_client(struct i2c_client *client)
+{
+ struct thmc50_data *data = i2c_get_clientdata(client);
+ int config;
+
+ data->analog_out = i2c_smbus_read_byte_data(client,
+ THMC50_REG_ANALOG_OUT);
+ /* set up to at least 1 */
+ if (data->analog_out == 0) {
+ data->analog_out = 1;
+ i2c_smbus_write_byte_data(client, THMC50_REG_ANALOG_OUT,
+ data->analog_out);
+ }
+ config = i2c_smbus_read_byte_data(client, THMC50_REG_CONF);
+ config |= 0x1; /* start the chip if it is in standby mode */
+ if (data->has_temp3)
+ config |= 0x80; /* enable 2nd remote temp */
+ i2c_smbus_write_byte_data(client, THMC50_REG_CONF, config);
+}
+
+static struct thmc50_data *thmc50_update_device(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct thmc50_data *data = i2c_get_clientdata(client);
+ int timeout = HZ / 5 + (data->type == thmc50 ? HZ : 0);
+
+ mutex_lock(&data->update_lock);
+
+ if (time_after(jiffies, data->last_updated + timeout)
+ || !data->valid) {
+
+ int temps = data->has_temp3 ? 3 : 2;
+ int i;
+ for (i = 0; i < temps; i++) {
+ data->temp_input[i] = i2c_smbus_read_byte_data(client,
+ THMC50_REG_TEMP[i]);
+ data->temp_max[i] = i2c_smbus_read_byte_data(client,
+ THMC50_REG_TEMP_MAX[i]);
+ data->temp_min[i] = i2c_smbus_read_byte_data(client,
+ THMC50_REG_TEMP_MIN[i]);
+ }
+ data->analog_out =
+ i2c_smbus_read_byte_data(client, THMC50_REG_ANALOG_OUT);
+ data->last_updated = jiffies;
+ data->valid = 1;
+ }
+
+ mutex_unlock(&data->update_lock);
+
+ return data;
+}
+
+static int __init sm_thmc50_init(void)
+{
+ return i2c_add_driver(&thmc50_driver);
+}
+
+static void __exit sm_thmc50_exit(void)
+{
+ i2c_del_driver(&thmc50_driver);
+}
+
+MODULE_AUTHOR("Krzysztof Helt <krzysztof.h1@wp.pl>");
+MODULE_DESCRIPTION("THMC50 driver");
+
+module_init(sm_thmc50_init);
+module_exit(sm_thmc50_exit);
static struct pci_dev *s_bridge; /* pointer to the (only) via686a */
static int via686a_probe(struct platform_device *pdev);
-static int via686a_remove(struct platform_device *pdev);
+static int __devexit via686a_remove(struct platform_device *pdev);
static inline int via686a_read_value(struct via686a_data *data, u8 reg)
{
static struct pci_dev *s_bridge;
static int vt8231_probe(struct platform_device *pdev);
-static int vt8231_remove(struct platform_device *pdev);
+static int __devexit vt8231_remove(struct platform_device *pdev);
static struct vt8231_data *vt8231_update_device(struct device *dev);
static void vt8231_init_device(struct vt8231_data *data);
return err;
}
-static int vt8231_remove(struct platform_device *pdev)
+static int __devexit vt8231_remove(struct platform_device *pdev)
{
struct vt8231_data *data = platform_get_drvdata(pdev);
int i;
static int w83627hf_probe(struct platform_device *pdev);
-static int w83627hf_remove(struct platform_device *pdev);
+static int __devexit w83627hf_remove(struct platform_device *pdev);
static int w83627hf_read_value(struct w83627hf_data *data, u16 reg);
static int w83627hf_write_value(struct w83627hf_data *data, u16 reg, u16 value);
if (ret)
goto out;
- state = kmalloc(sizeof(struct icside_state), GFP_KERNEL);
+ state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
if (!state) {
ret = -ENOMEM;
goto release;
}
- memset(state, 0, sizeof(state));
state->type = ICS_TYPE_NOTYPE;
state->dev = &ec->dev;
} idetape_chrdev_direction_t;
struct idetape_bh {
- unsigned short b_size;
+ u32 b_size;
atomic_t b_count;
struct idetape_bh *b_reqnext;
char *b_data;
.ident = "HP Pavilion N5430",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
- DMI_MATCH(DMI_BOARD_NAME, "OmniBook N32N-736"),
+ DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
},
},
{ }
switch (rev) {
case 0x07:
case 0x05:
- printk("%s: UltraDMA capable", name);
+ printk("%s: UltraDMA capable\n", name);
break;
case 0x03:
default:
- printk("%s: MultiWord DMA force limited", name);
+ printk("%s: MultiWord DMA force limited\n", name);
break;
case 0x01:
printk("%s: MultiWord DMA limited, "
static int cs5520_config_drive_xfer_rate(ide_drive_t *drive)
{
/* Tune the drive for PIO modes up to PIO 4 */
- cs5520_tune_drive(drive, 4);
+ cs5520_tune_drive(drive, 255);
/* Then tell the core to use DMA operations */
return 0;
* linux/drivers/ide/pci/cs5535.c
*
* Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
+ * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
*
* History:
* 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
/* Set the PIO timings */
if ((speed & XFER_MODE) == XFER_PIO) {
- u8 pioa;
- u8 piob;
- u8 cmd;
+ ide_drive_t *pair = &drive->hwif->drives[drive->dn ^ 1];
+ u8 cmd, pioa;
- pioa = speed - XFER_PIO_0;
- piob = ide_get_best_pio_mode(&(drive->hwif->drives[!unit]),
- 255, 4);
- cmd = pioa < piob ? pioa : piob;
+ cmd = pioa = speed - XFER_PIO_0;
+
+ if (pair->present) {
+ u8 piob = ide_get_best_pio_mode(pair, 255, 4);
+
+ if (piob < cmd)
+ cmd = piob;
+ }
/* Write the speed of the current drive */
reg = (cs5535_pio_cmd_timings[cmd] << 16) |
reg &= 0x80000000UL; /* Preserve the PIO format bit */
- if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_7)
+ if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
*
* A callback from the upper layers for PIO-only tuning.
*/
-static void cs5535_tuneproc(ide_drive_t *drive, u8 xferspeed)
+static void cs5535_tuneproc(ide_drive_t *drive, u8 pio)
{
- u8 modes[] = { XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3,
- XFER_PIO_4 };
-
- /* cs5535 max pio is pio 4, best_pio will check the blacklist.
- i think we don't need to rate_filter the incoming xferspeed
- since we know we're only going to choose pio */
- xferspeed = ide_get_best_pio_mode(drive, xferspeed, 4);
- ide_config_drive_speed(drive, modes[xferspeed]);
- cs5535_set_speed(drive, xferspeed);
+ pio = ide_get_best_pio_mode(drive, pio, 4);
+ ide_config_drive_speed(drive, XFER_PIO_0 + pio);
+ cs5535_set_speed(drive, XFER_PIO_0 + pio);
}
static int cs5535_dma_check(ide_drive_t *drive)
{
- u8 speed;
-
drive->init_speed = 0;
if (ide_tune_dma(drive))
return 0;
- if (ide_use_fast_pio(drive)) {
- speed = ide_get_best_pio_mode(drive, 255, 4);
- cs5535_set_drive(drive, speed);
- }
+ if (ide_use_fast_pio(drive))
+ cs5535_tuneproc(drive, 255);
return -1;
}
* it8213_dma_2_pio - return the PIO mode matching DMA
* @xfer_rate: transfer speed
*
- * Returns the nearest equivalent PIO timing for the PIO or DMA
+ * Returns the nearest equivalent PIO timing for the DMA
* mode requested by the controller.
*/
case XFER_UDMA_1:
case XFER_UDMA_0:
case XFER_MW_DMA_2:
- case XFER_PIO_4:
return 4;
case XFER_MW_DMA_1:
- case XFER_PIO_3:
return 3;
case XFER_SW_DMA_2:
- case XFER_PIO_2:
return 2;
case XFER_MW_DMA_0:
case XFER_SW_DMA_1:
case XFER_SW_DMA_0:
- case XFER_PIO_1:
- case XFER_PIO_0:
- case XFER_PIO_SLOW:
default:
return 0;
}
}
/*
- * it8213_tuneproc - tune a drive
+ * it8213_tune_pio - tune a drive
* @drive: drive to tune
* @pio: desired PIO mode
*
* Set the interface PIO mode.
*/
-static void it8213_tuneproc (ide_drive_t *drive, u8 pio)
+static void it8213_tune_pio(ide_drive_t *drive, const u8 pio)
{
ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = hwif->pci_dev;
{ 2, 1 },
{ 2, 3 }, };
- pio = ide_get_best_pio_mode(drive, pio, 4);
-
spin_lock_irqsave(&tune_lock, flags);
pci_read_config_word(dev, master_port, &master_data);
spin_unlock_irqrestore(&tune_lock, flags);
}
+static void it8213_tuneproc(ide_drive_t *drive, u8 pio)
+{
+ pio = ide_get_best_pio_mode(drive, pio, 4);
+ it8213_tune_pio(drive, pio);
+ ide_config_drive_speed(drive, XFER_PIO_0 + pio);
+}
+
/**
* it8213_tune_chipset - set controller timings
* @drive: Drive to set up
if (reg55 & w_flag)
pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
}
- it8213_tuneproc(drive, it8213_dma_2_pio(speed));
+
+ if (speed > XFER_PIO_4)
+ it8213_tune_pio(drive, it8213_dma_2_pio(speed));
+ else
+ it8213_tune_pio(drive, speed - XFER_PIO_0);
+
return ide_config_drive_speed(drive, speed);
}
static int it8213_config_drive_for_dma (ide_drive_t *drive)
{
- u8 pio;
-
if (ide_tune_dma(drive))
return 0;
- pio = ide_get_best_pio_mode(drive, 255, 4);
- it8213_tune_chipset(drive, XFER_PIO_0 + pio);
+ it8213_tuneproc(drive, 255);
return -1;
}
return ATA_CBL_PATA80;
}
-static void jmicron_tuneproc (ide_drive_t *drive, byte mode_wanted)
+static void jmicron_tuneproc(ide_drive_t *drive, u8 pio)
{
- return;
-}
-
-/**
- * config_jmicron_chipset_for_pio - set drive timings
- * @drive: drive to tune
- * @speed we want
- *
- */
-
-static void config_jmicron_chipset_for_pio (ide_drive_t *drive, byte set_speed)
-{
- u8 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5);
- if (set_speed)
- (void) ide_config_drive_speed(drive, speed);
+ pio = ide_get_best_pio_mode(drive, pio, 5);
+ ide_config_drive_speed(drive, XFER_PIO_0 + pio);
}
/**
if (ide_tune_dma(drive))
return 0;
- config_jmicron_chipset_for_pio(drive, 1);
+ jmicron_tuneproc(drive, 255);
return -1;
}
/*
- * linux/drivers/ide/pci/piix.c Version 0.50 Jun 10, 2007
+ * linux/drivers/ide/pci/piix.c Version 0.51 Jul 6, 2007
*
* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
* piix_dma_2_pio - return the PIO mode matching DMA
* @xfer_rate: transfer speed
*
- * Returns the nearest equivalent PIO timing for the PIO or DMA
+ * Returns the nearest equivalent PIO timing for the DMA
* mode requested by the controller.
*/
case XFER_UDMA_1:
case XFER_UDMA_0:
case XFER_MW_DMA_2:
- case XFER_PIO_4:
return 4;
case XFER_MW_DMA_1:
- case XFER_PIO_3:
return 3;
case XFER_SW_DMA_2:
- case XFER_PIO_2:
return 2;
case XFER_MW_DMA_0:
case XFER_SW_DMA_1:
case XFER_SW_DMA_0:
- case XFER_PIO_1:
- case XFER_PIO_0:
- case XFER_PIO_SLOW:
default:
return 0;
}
case XFER_PIO_4:
case XFER_PIO_3:
case XFER_PIO_2:
+ case XFER_PIO_1:
case XFER_PIO_0: break;
default: return -1;
}
pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
}
- piix_tune_pio(drive, piix_dma_2_pio(speed));
+ if (speed > XFER_PIO_4)
+ piix_tune_pio(drive, piix_dma_2_pio(speed));
+ else
+ piix_tune_pio(drive, speed - XFER_PIO_0);
+
return ide_config_drive_speed(drive, speed);
}
}
/**
- * scc_tuneproc - tune a drive PIO mode
+ * scc_tune_pio - tune a drive PIO mode
* @drive: drive to tune
* @mode_wanted: the target operating mode
*
* controller.
*/
-static void scc_tuneproc(ide_drive_t *drive, byte mode_wanted)
+static void scc_tune_pio(ide_drive_t *drive, const u8 pio)
{
ide_hwif_t *hwif = HWIF(drive);
struct scc_ports *ports = ide_get_hwifdata(hwif);
unsigned long piosht_port = ctl_base + 0x000;
unsigned long pioct_port = ctl_base + 0x004;
unsigned long reg;
- unsigned char speed = XFER_PIO_0;
int offset;
- mode_wanted = ide_get_best_pio_mode(drive, mode_wanted, 4);
- switch (mode_wanted) {
- case 4:
- speed = XFER_PIO_4;
- break;
- case 3:
- speed = XFER_PIO_3;
- break;
- case 2:
- speed = XFER_PIO_2;
- break;
- case 1:
- speed = XFER_PIO_1;
- break;
- case 0:
- default:
- speed = XFER_PIO_0;
- break;
- }
-
reg = in_be32((void __iomem *)cckctrl_port);
if (reg & CCKCTRL_ATACLKOEN) {
offset = 1; /* 133MHz */
} else {
offset = 0; /* 100MHz */
}
- reg = JCHSTtbl[offset][mode_wanted] << 16 | JCHHTtbl[offset][mode_wanted];
+ reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
out_be32((void __iomem *)piosht_port, reg);
- reg = JCHCTtbl[offset][mode_wanted];
+ reg = JCHCTtbl[offset][pio];
out_be32((void __iomem *)pioct_port, reg);
+}
- ide_config_drive_speed(drive, speed);
+static void scc_tuneproc(ide_drive_t *drive, u8 pio)
+{
+ pio = ide_get_best_pio_mode(drive, pio, 4);
+ scc_tune_pio(drive, pio);
+ ide_config_drive_speed(drive, XFER_PIO_0 + pio);
}
/**
switch (speed) {
case XFER_UDMA_6:
- idx = 6;
- break;
case XFER_UDMA_5:
- idx = 5;
- break;
case XFER_UDMA_4:
- idx = 4;
- break;
case XFER_UDMA_3:
- idx = 3;
- break;
case XFER_UDMA_2:
- idx = 2;
- break;
case XFER_UDMA_1:
- idx = 1;
- break;
case XFER_UDMA_0:
- idx = 0;
+ idx = speed - XFER_UDMA_0;
break;
+ case XFER_PIO_4:
+ case XFER_PIO_3:
+ case XFER_PIO_2:
+ case XFER_PIO_1:
+ case XFER_PIO_0:
+ scc_tune_pio(drive, speed - XFER_PIO_0);
+ return ide_config_drive_speed(drive, speed);
default:
return 1;
}
* required.
* If the drive isn't suitable for DMA or we hit other problems
* then we will drop down to PIO and set up PIO appropriately.
- * (return 1)
+ * (return -1)
*/
static int scc_config_drive_for_dma(ide_drive_t *drive)
return 0;
if (ide_use_fast_pio(drive))
- scc_tuneproc(drive, 4);
+ scc_tuneproc(drive, 255);
return -1;
}
static const struct sis_laptop sis_laptop[] = {
/* devid, subvendor, subdev */
{ 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
+ { 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */
/* end marker */
{ 0, }
};
/*
- * linux/drivers/ide/pci/slc90e66.c Version 0.14 February 8, 2007
+ * linux/drivers/ide/pci/slc90e66.c Version 0.15 Jul 6, 2007
*
* Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
case XFER_UDMA_1:
case XFER_UDMA_0:
case XFER_MW_DMA_2:
- case XFER_PIO_4:
return 4;
case XFER_MW_DMA_1:
- case XFER_PIO_3:
return 3;
case XFER_SW_DMA_2:
- case XFER_PIO_2:
return 2;
case XFER_MW_DMA_0:
case XFER_SW_DMA_1:
case XFER_SW_DMA_0:
- case XFER_PIO_1:
- case XFER_PIO_0:
- case XFER_PIO_SLOW:
default:
return 0;
}
case XFER_PIO_4:
case XFER_PIO_3:
case XFER_PIO_2:
+ case XFER_PIO_1:
case XFER_PIO_0: break;
default: return -1;
}
pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
}
- slc90e66_tune_pio(drive, slc90e66_dma_2_pio(speed));
+ if (speed > XFER_PIO_4)
+ slc90e66_tune_pio(drive, slc90e66_dma_2_pio(speed));
+ else
+ slc90e66_tune_pio(drive, speed - XFER_PIO_0);
+
return ide_config_drive_speed(drive, speed);
}
#elif defined(CONFIG_S390)
# define COMPAT_TEST test_thread_flag(TIF_31BIT)
#elif defined(CONFIG_MIPS)
-# define COMPAT_TEST (current->thread.mflags & MF_32BIT_ADDR)
+# define COMPAT_TEST test_thread_flag(TIF_32BIT_ADDR)
#else
# define COMPAT_TEST test_thread_flag(TIF_32BIT)
#endif
#endif /* CONFIG_MTD_DOCPROBE_HIGH */
#elif defined(__PPC__)
0xe4000000,
-#elif defined(CONFIG_MOMENCO_OCELOT)
- 0x2f000000,
- 0xff000000,
#elif defined(CONFIG_MOMENCO_OCELOT_G)
0xff000000,
##else
nand_chip->IO_ADDR_R = host->io_base;
nand_chip->IO_ADDR_W = host->io_base;
nand_chip->cmd_ctrl = at91_nand_cmd_ctrl;
- nand_chip->dev_ready = at91_nand_device_ready;
+
+ if (host->board->rdy_pin)
+ nand_chip->dev_ready = at91_nand_device_ready;
+
nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
nand_chip->chip_delay = 20; /* 20us command delay time */
#endif /* CONFIG_MTD_DOCPROBE_HIGH */
#elif defined(__PPC__)
0xe4000000,
-#elif defined(CONFIG_MOMENCO_OCELOT)
- 0x2f000000,
- 0xff000000,
#elif defined(CONFIG_MOMENCO_OCELOT_G)
0xff000000,
#else
/*
* hardware specific access to control-lines
*
- * NAND_NCE: bit 0 -> bit 7
+ * NAND_NCE: bit 0 -> bit 6 (bit 7 = 1)
* NAND_CLE: bit 1 -> bit 4
* NAND_ALE: bit 2 -> bit 5
*/
struct nand_chip *chip = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
- unsigned char bits;
+ unsigned char bits = 0x80;
- bits = (ctrl & (NAND_CLE | NAND_ALE)) << 3;
- bits = (ctrl & NAND_NCE) << 7;
+ bits |= (ctrl & (NAND_CLE | NAND_ALE)) << 3;
+ bits |= (ctrl & NAND_NCE) ? 0x00 : 0x40;
- clps_writeb((clps_readb(ep7312_pxdr) & 0xB0) | 0x10,
+ clps_writeb((clps_readb(ep7312_pxdr) & 0xF0) | bits,
ep7312_pxdr);
}
if (cmd != NAND_CMD_NONE)
* if we have HW ecc support.
* The AG-AND chips have nice features for speed improvement,
* which are not supported yet. Read / program 4 pages in one go.
+ * BBT table is not serialized, has to be fixed
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
/* We write two bytes, so we dont have to mess with 16 bit
* access
*/
+ nand_get_device(chip, mtd, FL_WRITING);
ofs += mtd->oobsize;
chip->ops.len = chip->ops.ooblen = 2;
chip->ops.datbuf = NULL;
chip->ops.ooboffs = chip->badblockpos & ~0x01;
ret = nand_do_write_oob(mtd, ofs, &chip->ops);
+ nand_release_device(mtd);
}
if (!ret)
mtd->ecc_stats.badblocks++;
+
return ret;
}
uint8_t *p = buf;
uint8_t *ecc_calc = chip->buffers->ecccalc;
uint8_t *ecc_code = chip->buffers->ecccode;
- int *eccpos = chip->ecc.layout->eccpos;
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
chip->ecc.read_page_raw(mtd, chip, buf);
uint8_t *p = buf;
uint8_t *ecc_calc = chip->buffers->ecccalc;
uint8_t *ecc_code = chip->buffers->ecccode;
- int *eccpos = chip->ecc.layout->eccpos;
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
chip->ecc.hwctl(mtd, NAND_ECC_READ);
int eccsteps = chip->ecc.steps;
uint8_t *ecc_calc = chip->buffers->ecccalc;
const uint8_t *p = buf;
- int *eccpos = chip->ecc.layout->eccpos;
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
/* Software ecc calculation */
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
int eccsteps = chip->ecc.steps;
uint8_t *ecc_calc = chip->buffers->ecccalc;
const uint8_t *p = buf;
- int *eccpos = chip->ecc.layout->eccpos;
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
else {
if (!mtd->erasesize) {
printk(KERN_WARNING PREFIX "please provide block_size");
+ kfree(part);
return;
}
else
/* restore the PCI config space */
pci_restore_state(pci_dev);
/* if the device was enabled before suspend, reenable */
- retval = __pci_reenable_device(pci_dev);
+ retval = pci_reenable_device(pci_dev);
/* if the device was busmaster before the suspend, make it busmaster again */
if (pci_dev->is_busmaster)
pci_set_master(pci_dev);
}
/**
- * __pci_reenable_device - Resume abandoned device
+ * pci_reenable_device - Resume abandoned device
* @dev: PCI device to be resumed
*
* Note this function is a backend of pci_default_resume and is not supposed
* to be called by normal code, write proper resume handler and use it instead.
*/
-int
-__pci_reenable_device(struct pci_dev *dev)
+int pci_reenable_device(struct pci_dev *dev)
{
if (atomic_read(&dev->enable_cnt))
return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
device_initcall(pci_init);
EXPORT_SYMBOL_GPL(pci_restore_bars);
-EXPORT_SYMBOL(__pci_reenable_device);
+EXPORT_SYMBOL(pci_reenable_device);
EXPORT_SYMBOL(pci_enable_device_bars);
EXPORT_SYMBOL(pci_enable_device);
EXPORT_SYMBOL(pcim_enable_device);
u8 *buf;
/* stuff a sense request in front of our current request */
- pc = kmalloc (sizeof (idescsi_pc_t), GFP_ATOMIC);
- rq = kmalloc (sizeof (struct request), GFP_ATOMIC);
- buf = kmalloc(SCSI_SENSE_BUFFERSIZE, GFP_ATOMIC);
- if (pc == NULL || rq == NULL || buf == NULL) {
+ pc = kzalloc(sizeof(idescsi_pc_t), GFP_ATOMIC);
+ rq = kmalloc(sizeof(struct request), GFP_ATOMIC);
+ buf = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_ATOMIC);
+ if (!pc || !rq || !buf) {
kfree(buf);
kfree(rq);
kfree(pc);
return -ENOMEM;
}
- memset (pc, 0, sizeof (idescsi_pc_t));
- memset (buf, 0, SCSI_SENSE_BUFFERSIZE);
ide_init_drive_cmd(rq);
rq->special = (char *) pc;
pc->rq = rq;
set_freezable();
for (;;) {
allow_signal(SIGHUP);
-
+ again:
if (!jffs2_thread_should_wake(c)) {
set_current_state (TASK_INTERRUPTIBLE);
D1(printk(KERN_DEBUG "jffs2_garbage_collect_thread sleeping...\n"));
schedule();
}
- if (try_to_freeze())
- continue;
-
/* This thread is purely an optimisation. But if it runs when
other things could be running, it actually makes things a
lot worse. Use yield() and put it at the back of the runqueue
siginfo_t info;
unsigned long signr;
+ if (try_to_freeze())
+ goto again;
+
signr = dequeue_signal_lock(current, ¤t->blocked, &info);
switch(signr) {
#define ref_obsolete(ref) (((ref)->flash_offset & 3) == REF_OBSOLETE)
#define mark_ref_normal(ref) do { (ref)->flash_offset = ref_offset(ref) | REF_NORMAL; } while(0)
+/* Dirent nodes should be REF_PRISTINE only if they are not a deletion
+ dirent. Deletion dirents should be REF_NORMAL so that GC gets to
+ throw them away when appropriate */
+#define dirent_node_state(rd) ( (je32_to_cpu((rd)->ino)?REF_PRISTINE:REF_NORMAL) )
+
/* NB: REF_PRISTINE for an inode-less node (ref->next_in_ino == NULL) indicates
it is an unknown node of type JFFS2_NODETYPE_RWCOMPAT_COPY, so it'll get
copied. If you need to do anything different to GC inode-less nodes, then
if (crc != tn->data_crc) {
JFFS2_NOTICE("wrong data CRC in data node at 0x%08x: read %#08x, calculated %#08x.\n",
- ofs, tn->data_crc, crc);
+ ref_offset(ref), tn->data_crc, crc);
return 1;
}
jeb->unchecked_size -= len;
c->used_size += len;
c->unchecked_size -= len;
- ref->flash_offset = ref_offset(ref) | REF_PRISTINE;
+ ref->flash_offset = ref_offset(ref) | dirent_node_state(rd);
spin_unlock(&c->erase_completion_lock);
}
return -ENOMEM;
}
- fd->raw = jffs2_link_node_ref(c, jeb, ofs | REF_PRISTINE, PAD(je32_to_cpu(rd->totlen)), ic);
+ fd->raw = jffs2_link_node_ref(c, jeb, ofs | dirent_node_state(rd),
+ PAD(je32_to_cpu(rd->totlen)), ic);
fd->next = NULL;
fd->version = je32_to_cpu(rd->version);
flash_ofs |= REF_NORMAL;
}
fn->raw = jffs2_add_physical_node_ref(c, flash_ofs, PAD(sizeof(*ri)+datalen), f->inocache);
+ if (IS_ERR(fn->raw)) {
+ void *hold_err = fn->raw;
+ /* Release the full_dnode which is now useless, and return */
+ jffs2_free_full_dnode(fn);
+ return ERR_PTR(PTR_ERR(hold_err));
+ }
fn->ofs = je32_to_cpu(ri->offset);
fn->size = je32_to_cpu(ri->dsize);
fn->frags = 0;
return ERR_PTR(ret?ret:-EIO);
}
/* Mark the space used */
- fd->raw = jffs2_add_physical_node_ref(c, flash_ofs | REF_PRISTINE, PAD(sizeof(*rd)+namelen), f->inocache);
+ fd->raw = jffs2_add_physical_node_ref(c, flash_ofs | dirent_node_state(rd),
+ PAD(sizeof(*rd)+namelen), f->inocache);
+ if (IS_ERR(fd->raw)) {
+ void *hold_err = fd->raw;
+ /* Release the full_dirent which is now useless, and return */
+ jffs2_free_full_dirent(fd);
+ return ERR_PTR(PTR_ERR(hold_err));
+ }
if (retried) {
jffs2_dbg_acct_sanity_check(c,NULL);
#define WARN_ON(condition) \
({ \
- typeof(condition) __ret_warn_on = (condition); \
+ int __ret_warn_on = !!(condition); \
if (unlikely(__ret_warn_on)) \
_BUG_OR_WARN(BUGFLAG_WARNING); \
unlikely(__ret_warn_on); \
#define __reg_MB86943_pci_sl_io_base *(volatile uint32_t *) (__region_CS1 + 0x70)
#define __reg_MB86943_pci_sl_mem_base *(volatile uint32_t *) (__region_CS1 + 0x78)
+#define __reg_MB86943_pci_arbiter *(volatile uint32_t *) (__region_CS2 + 0x01300014)
+#define MB86943_PCIARB_EN 0x00000001
+
#endif /* _ASM_MB86943A_H */
#ifndef HAVE_ARCH_WARN_ON
#define WARN_ON(condition) ({ \
- typeof(condition) __ret_warn_on = (condition); \
+ int __ret_warn_on = !!(condition); \
if (unlikely(__ret_warn_on)) { \
printk("WARNING: at %s:%d %s()\n", __FILE__, \
__LINE__, __FUNCTION__); \
#ifndef HAVE_ARCH_WARN_ON
#define WARN_ON(condition) ({ \
- typeof(condition) __ret_warn_on = (condition); \
+ int __ret_warn_on = !!(condition); \
unlikely(__ret_warn_on); \
})
#endif
#define WARN_ON_ONCE(condition) ({ \
static int __warned; \
- typeof(condition) __ret_warn_once = (condition); \
+ int __ret_warn_once = !!(condition); \
\
if (unlikely(__ret_warn_once)) \
if (WARN_ON(!__warned)) \
#define STACK_TOP TASK_SIZE
#endif
#ifdef CONFIG_64BIT
-#define STACK_TOP (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE)
+#define STACK_TOP \
+ (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
#endif
#define STACK_TOP_MAX TASK_SIZE
#define MACH_GROUP_COBALT 7 /* Cobalt servers */
#define MACH_COBALT_27 0 /* Proto "27" hardware */
-/*
- * Valid machtype for group NEC DDB
- */
-#define MACH_GROUP_NEC_DDB 8 /* NEC DDB */
-#define MACH_NEC_DDB5074 0 /* NEC DDB Vrc-5074 */
-#define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */
-#define MACH_NEC_DDB5477 2 /* NEC DDB Vrc-5477 */
-#define MACH_NEC_ROCKHOPPER 3 /* Rockhopper base board */
-#define MACH_NEC_ROCKHOPPERII 4 /* Rockhopper II base board */
-
/*
* Valid machtype for group BAGET
*/
#define MACH_TOSHIBA_RBTX4937 5
#define MACH_TOSHIBA_RBTX4938 6
-#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \
- "RBTX4927", "RBTX4937" }
-
/*
* Valid machtype for group Alchemy
*/
+++ /dev/null
-/***********************************************************************
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * include/asm-mips/ddb5xxx/ddb5477.h
- * DDB 5477 specific definitions and macros.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- ***********************************************************************
- */
-
-#ifndef __ASM_DDB5XXX_DDB5477_H
-#define __ASM_DDB5XXX_DDB5477_H
-
-#include <irq.h>
-
-/*
- * This contains macros that are specific to DDB5477 or renamed from
- * DDB5476.
- */
-
-/*
- * renamed PADRs
- */
-#define DDB_LCS0 DDB_DCS2
-#define DDB_LCS1 DDB_DCS3
-#define DDB_LCS2 DDB_DCS4
-#define DDB_VRC5477 DDB_INTCS
-
-/*
- * New CPU interface registers
- */
-#define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */
-#define DDB_INTCTRL1 0x0404 /* Interrupt Control 1 */
-#define DDB_INTCTRL2 0x0408 /* Interrupt Control 2 */
-#define DDB_INTCTRL3 0x040c /* Interrupt Control 3 */
-
-#define DDB_INT0STAT 0x0420 /* INT0 Status [R] */
-#define DDB_INT1STAT 0x0428 /* INT1 Status [R] */
-#define DDB_INT2STAT 0x0430 /* INT2 Status [R] */
-#define DDB_INT3STAT 0x0438 /* INT3 Status [R] */
-#define DDB_INT4STAT 0x0440 /* INT4 Status [R] */
-#define DDB_NMISTAT 0x0450 /* NMI Status [R] */
-
-#define DDB_INTCLR32 0x0468 /* Interrupt Clear */
-
-#define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */
-#define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */
-
-#undef DDB_CPUSTAT /* duplicate in Vrc-5477 */
-#define DDB_CPUSTAT 0x0480 /* CPU Status [R] */
-#define DDB_BUSCTRL 0x0488 /* Internal Bus Control */
-
-
-/*
- * Timer registers
- */
-#define DDB_REFCTRL_L DDB_T0CTRL
-#define DDB_REFCTRL_H (DDB_T0CTRL+4)
-#define DDB_REFCNTR DDB_T0CNTR
-#define DDB_SPT0CTRL_L DDB_T1CTRL
-#define DDB_SPT0CTRL_H (DDB_T1CTRL+4)
-#define DDB_SPT1CTRL_L DDB_T2CTRL
-#define DDB_SPT1CTRL_H (DDB_T2CTRL+4)
-#define DDB_SPT1CNTR DDB_T1CTRL
-#define DDB_WDTCTRL_L DDB_T3CTRL
-#define DDB_WDTCTRL_H (DDB_T3CTRL+4)
-#define DDB_WDTCNTR DDB_T3CNTR
-
-/*
- * DMA registers are moved. We don't care about it for now. TODO.
- */
-
-/*
- * BARs for ext PCI (PCI0)
- */
-#undef DDB_BARC
-#undef DDB_BARB
-
-#define DDB_BARC0 0x0210 /* PCI0 Control */
-#define DDB_BARM010 0x0218 /* PCI0 SDRAM bank01 */
-#define DDB_BARM230 0x0220 /* PCI0 SDRAM bank23 */
-#define DDB_BAR00 0x0240 /* PCI0 LDCS0 */
-#define DDB_BAR10 0x0248 /* PCI0 LDCS1 */
-#define DDB_BAR20 0x0250 /* PCI0 LDCS2 */
-#define DDB_BAR30 0x0258 /* PCI0 LDCS3 */
-#define DDB_BAR40 0x0260 /* PCI0 LDCS4 */
-#define DDB_BAR50 0x0268 /* PCI0 LDCS5 */
-#define DDB_BARB0 0x0280 /* PCI0 BOOT */
-#define DDB_BARP00 0x0290 /* PCI0 for IOPCI Window0 */
-#define DDB_BARP10 0x0298 /* PCI0 for IOPCI Window1 */
-
-/*
- * BARs for IOPIC (PCI1)
- */
-#define DDB_BARC1 0x0610 /* PCI1 Control */
-#define DDB_BARM011 0x0618 /* PCI1 SDRAM bank01 */
-#define DDB_BARM231 0x0620 /* PCI1 SDRAM bank23 */
-#define DDB_BAR01 0x0640 /* PCI1 LDCS0 */
-#define DDB_BAR11 0x0648 /* PCI1 LDCS1 */
-#define DDB_BAR21 0x0650 /* PCI1 LDCS2 */
-#define DDB_BAR31 0x0658 /* PCI1 LDCS3 */
-#define DDB_BAR41 0x0660 /* PCI1 LDCS4 */
-#define DDB_BAR51 0x0668 /* PCI1 LDCS5 */
-#define DDB_BARB1 0x0680 /* PCI1 BOOT */
-#define DDB_BARP01 0x0690 /* PCI1 for ext PCI Window0 */
-#define DDB_BARP11 0x0698 /* PCI1 for ext PCI Window1 */
-
-/*
- * Other registers for ext PCI (PCI0)
- */
-#define DDB_PCIINIT00 0x02f0 /* PCI0 Initiator 0 */
-#define DDB_PCIINIT10 0x02f8 /* PCI0 Initiator 1 */
-
-#define DDB_PCISWP0 0x02b0 /* PCI0 Swap */
-#define DDB_PCIERR0 0x02b8 /* PCI0 Error */
-
-#define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */
-#define DDB_PCICTL0_H 0x02e4 /* PCI0 Control-H */
-#define DDB_PCIARB0_L 0x02e8 /* PCI0 Arbitration-L */
-#define DDB_PCIARB0_H 0x02ec /* PCI0 Arbitration-H */
-
-/*
- * Other registers for IOPCI (PCI1)
- */
-#define DDB_IOPCIW0 0x00d0 /* PCI Address Window 0 [R/W] */
-#define DDB_IOPCIW1 0x00d8 /* PCI Address Window 1 [R/W] */
-
-#define DDB_PCIINIT01 0x06f0 /* PCI1 Initiator 0 */
-#define DDB_PCIINIT11 0x06f8 /* PCI1 Initiator 1 */
-
-#define DDB_PCISWP1 0x06b0 /* PCI1 Swap */
-#define DDB_PCIERR1 0x06b8 /* PCI1 Error */
-
-#define DDB_PCICTL1_L 0x06e0 /* PCI1 Control-L */
-#define DDB_PCICTL1_H 0x06e4 /* PCI1 Control-H */
-#define DDB_PCIARB1_L 0x06e8 /* PCI1 Arbitration-L */
-#define DDB_PCIARB1_H 0x06ec /* PCI1 Arbitration-H */
-
-/*
- * Local Bus
- */
-#define DDB_LCST0 0x0110 /* LB Chip Select Timing 0 */
-#define DDB_LCST1 0x0118 /* LB Chip Select Timing 1 */
-#undef DDB_LCST2
-#define DDB_LCST2 0x0120 /* LB Chip Select Timing 2 */
-#undef DDB_LCST3
-#undef DDB_LCST4
-#undef DDB_LCST5
-#undef DDB_LCST6
-#undef DDB_LCST7
-#undef DDB_LCST8
-#define DDB_ERRADR 0x0150 /* Error Address Register */
-#define DDB_ERRCS 0x0160
-#define DDB_BTM 0x0170 /* Boot Time Mode value */
-
-/*
- * MISC registers
- */
-#define DDB_GIUFUNSEL 0x4040 /* select dual-func pins */
-#define DDB_PIBMISC 0x0750 /* USB buffer enable / power saving */
-
-/*
- * Memory map (physical address)
- *
- * Note most of the following address must be properly aligned by the
- * corresponding size. For example, if PCI_IO_SIZE is 16MB, then
- * PCI_IO_BASE must be aligned along 16MB boundary.
- */
-
-/* the actual ram size is detected at run-time */
-#define DDB_SDRAM_BASE 0x00000000
-#define DDB_MAX_SDRAM_SIZE 0x08000000 /* less than 128MB */
-
-#define DDB_PCI0_MEM_BASE 0x08000000
-#define DDB_PCI0_MEM_SIZE 0x08000000 /* 128 MB */
-
-#define DDB_PCI1_MEM_BASE 0x10000000
-#define DDB_PCI1_MEM_SIZE 0x08000000 /* 128 MB */
-
-#define DDB_PCI0_CONFIG_BASE 0x18000000
-#define DDB_PCI0_CONFIG_SIZE 0x01000000 /* 16 MB */
-
-#define DDB_PCI1_CONFIG_BASE 0x19000000
-#define DDB_PCI1_CONFIG_SIZE 0x01000000 /* 16 MB */
-
-#define DDB_PCI_IO_BASE 0x1a000000 /* we concatenate two IOs */
-#define DDB_PCI0_IO_BASE 0x1a000000
-#define DDB_PCI0_IO_SIZE 0x01000000 /* 16 MB */
-#define DDB_PCI1_IO_BASE 0x1b000000
-#define DDB_PCI1_IO_SIZE 0x01000000 /* 16 MB */
-
-#define DDB_LCS0_BASE 0x1c000000 /* flash memory */
-#define DDB_LCS0_SIZE 0x01000000 /* 16 MB */
-
-#define DDB_LCS1_BASE 0x1d000000 /* misc */
-#define DDB_LCS1_SIZE 0x01000000 /* 16 MB */
-
-#define DDB_LCS2_BASE 0x1e000000 /* Mezzanine */
-#define DDB_LCS2_SIZE 0x01000000 /* 16 MB */
-
-#define DDB_VRC5477_BASE 0x1fa00000 /* VRC5477 control regs */
-#define DDB_VRC5477_SIZE 0x00200000 /* 2MB */
-
-#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
-#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
-
-#define DDB_LED DDB_LCS1_BASE + 0x10000
-
-
-/*
- * DDB5477 specific functions
- */
-#ifndef __ASSEMBLY__
-extern void ddb5477_irq_setup(void);
-
-/* route irq to cpu int pin */
-extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip);
-
-/* low-level routine for enabling vrc5477 irq, bypassing high-level */
-extern void ll_vrc5477_irq_enable(int vrc5477_irq);
-extern void ll_vrc5477_irq_disable(int vrc5477_irq);
-#endif /* !__ASSEMBLY__ */
-
-/* PCI intr ack share PCIW0 with PCI IO */
-#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
-
-/*
- * Interrupt mapping
- *
- * We have three interrupt controllers:
- *
- * . CPU itself - 8 sources
- * . i8259 - 16 sources
- * . vrc5477 - 32 sources
- *
- * They connected as follows:
- * all vrc5477 interrupts are routed to cpu IP2 (by software setting)
- * all i8359 are routed to INTC in vrc5477 (by hardware connection)
- *
- * All VRC5477 PCI interrupts are level-triggered (no ack needed).
- * All PCI irq but INTC are active low.
- */
-
-/*
- * irq number block assignment
- */
-
-#define NUM_CPU_IRQ 8
-#define NUM_VRC5477_IRQ 32
-
-#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE
-#define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ)
-
-/*
- * vrc5477 irq defs
- */
-
-#define VRC5477_IRQ_CPCE (0 + VRC5477_IRQ_BASE) /* cpu parity error */
-#define VRC5477_IRQ_CNTD (1 + VRC5477_IRQ_BASE) /* cpu no target */
-#define VRC5477_IRQ_I2C (2 + VRC5477_IRQ_BASE) /* I2C */
-#define VRC5477_IRQ_DMA (3 + VRC5477_IRQ_BASE) /* DMA */
-#define VRC5477_IRQ_UART0 (4 + VRC5477_IRQ_BASE)
-#define VRC5477_IRQ_WDOG (5 + VRC5477_IRQ_BASE) /* watchdog timer */
-#define VRC5477_IRQ_SPT1 (6 + VRC5477_IRQ_BASE) /* special purpose timer 1 */
-#define VRC5477_IRQ_LBRT (7 + VRC5477_IRQ_BASE) /* local bus read timeout */
-#define VRC5477_IRQ_INTA (8 + VRC5477_IRQ_BASE) /* PCI INT #A */
-#define VRC5477_IRQ_INTB (9 + VRC5477_IRQ_BASE) /* PCI INT #B */
-#define VRC5477_IRQ_INTC (10 + VRC5477_IRQ_BASE) /* PCI INT #C */
-#define VRC5477_IRQ_INTD (11 + VRC5477_IRQ_BASE) /* PCI INT #D */
-#define VRC5477_IRQ_INTE (12 + VRC5477_IRQ_BASE) /* PCI INT #E */
-#define VRC5477_IRQ_RESERVED_13 (13 + VRC5477_IRQ_BASE) /* reserved */
-#define VRC5477_IRQ_PCIS (14 + VRC5477_IRQ_BASE) /* PCI SERR # */
-#define VRC5477_IRQ_PCI (15 + VRC5477_IRQ_BASE) /* PCI internal error */
-#define VRC5477_IRQ_IOPCI_INTA (16 + VRC5477_IRQ_BASE) /* USB-H */
-#define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */
-#define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */
-#define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */
-#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE)
-#define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */
-#define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */
-#define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */
-#define VRC5477_IRQ_GPT2 (24 + VRC5477_IRQ_BASE) /* general purpose timer 2 */
-#define VRC5477_IRQ_GPT3 (25 + VRC5477_IRQ_BASE) /* general purpose timer 3 */
-#define VRC5477_IRQ_GPIO (26 + VRC5477_IRQ_BASE)
-#define VRC5477_IRQ_SIO0 (27 + VRC5477_IRQ_BASE)
-#define VRC5477_IRQ_SIO1 (28 + VRC5477_IRQ_BASE)
-#define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE) /* reserved */
-#define VRC5477_IRQ_IOPCISERR (30 + VRC5477_IRQ_BASE) /* IO PCI SERR # */
-#define VRC5477_IRQ_IOPCI (31 + VRC5477_IRQ_BASE)
-
-/*
- * i2859 irq assignment
- */
-#define I8259_IRQ_RESERVED_0 (0 + I8259A_IRQ_BASE)
-#define I8259_IRQ_KEYBOARD (1 + I8259A_IRQ_BASE) /* M1543 default */
-#define I8259_IRQ_CASCADE (2 + I8259A_IRQ_BASE)
-#define I8259_IRQ_UART_B (3 + I8259A_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */
-#define I8259_IRQ_UART_A (4 + I8259A_IRQ_BASE) /* M1543 default */
-#define I8259_IRQ_PARALLEL (5 + I8259A_IRQ_BASE) /* M1543 default */
-#define I8259_IRQ_RESERVED_6 (6 + I8259A_IRQ_BASE)
-#define I8259_IRQ_RESERVED_7 (7 + I8259A_IRQ_BASE)
-#define I8259_IRQ_RTC (8 + I8259A_IRQ_BASE) /* who set this? */
-#define I8259_IRQ_USB (9 + I8259A_IRQ_BASE) /* ddb_setup */
-#define I8259_IRQ_PMU (10 + I8259A_IRQ_BASE) /* ddb_setup */
-#define I8259_IRQ_RESERVED_11 (11 + I8259A_IRQ_BASE)
-#define I8259_IRQ_RESERVED_12 (12 + I8259A_IRQ_BASE) /* m1543_irq_setup */
-#define I8259_IRQ_RESERVED_13 (13 + I8259A_IRQ_BASE)
-#define I8259_IRQ_HDC1 (14 + I8259A_IRQ_BASE) /* default and ddb_setup */
-#define I8259_IRQ_HDC2 (15 + I8259A_IRQ_BASE) /* default */
-
-
-/*
- * misc
- */
-#define VRC5477_I8259_CASCADE (VRC5477_IRQ_INTC - VRC5477_IRQ_BASE)
-#define CPU_VRC5477_CASCADE 2
-
-/*
- * debug routines
- */
-#ifndef __ASSEMBLY__
-#if defined(CONFIG_RUNTIME_DEBUG)
-extern void vrc5477_show_pdar_regs(void);
-extern void vrc5477_show_pci_regs(void);
-extern void vrc5477_show_bar_regs(void);
-extern void vrc5477_show_int_regs(void);
-extern void vrc5477_show_all_regs(void);
-#endif
-
-/*
- * RAM size
- */
-extern int board_ram_size;
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __ASM_DDB5XXX_DDB5477_H */
+++ /dev/null
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
- * Sony Software Development Center Europe (SDCE), Brussels
- *
- * include/asm-mips/ddb5xxx/ddb5xxx.h
- * Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifndef __ASM_DDB5XXX_DDB5XXX_H
-#define __ASM_DDB5XXX_DDB5XXX_H
-
-#include <linux/types.h>
-
-/*
- * This file is based on the following documentation:
- *
- * NEC Vrc 5074 System Controller Data Sheet, June 1998
- *
- * [jsun] It is modified so that this file only contains the macros
- * that are true for all DDB 5xxx boards. The modification is based on
- *
- * uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke)
- * Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000
- *
- */
-
-
-#define DDB_BASE 0xbfa00000
-#define DDB_SIZE 0x00200000 /* 2 MB */
-
-
-/*
- * Physical Device Address Registers (PDARs)
- */
-
-#define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
-#define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
-#define DDB_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */
-#define DDB_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */
-#define DDB_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */
-#define DDB_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */
-#define DDB_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */
-#define DDB_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */
-#define DDB_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */
-#define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
-#define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
-#define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */
- /* [R/W] */
-#define DDB_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */
-/* Vrc5477 has two more, IOPCIW0, IOPCIW1 */
-
-/*
- * CPU Interface Registers
- */
-#define DDB_CPUSTAT 0x0080 /* CPU Status [R/W] */
-#define DDB_INTCTRL 0x0088 /* Interrupt Control [R/W] */
-#define DDB_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */
-#define DDB_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */
- /* Enable [R/W] */
-#define DDB_INTCLR 0x00A0 /* Interrupt Clear [R/W] */
-#define DDB_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
-
-
-/*
- * Memory-Interface Registers
- */
-#define DDB_MEMCTRL 0x00C0 /* Memory Control */
-#define DDB_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
-#define DDB_CHKERR 0x00D0 /* Memory Check Error Status [R] */
-
-
-/*
- * PCI-Bus Registers
- */
-#define DDB_PCICTRL 0x00E0 /* PCI Control [R/W] */
-#define DDB_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
-#define DDB_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
-#define DDB_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
-#define DDB_PCIERR 0x00B8 /* PCI Error [R/W] */
-
-
-/*
- * Local-Bus Registers
- */
-#define DDB_LCNFG 0x0100 /* Local Bus Configuration [R/W] */
-#define DDB_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */
-#define DDB_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */
-#define DDB_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */
-#define DDB_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */
-#define DDB_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */
-#define DDB_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */
-#define DDB_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */
-#define DDB_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */
- /* Enables [R/W] */
-#define DDB_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */
-#define DDB_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */
-
-
-/*
- * DMA Registers
- */
-#define DDB_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */
-#define DDB_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */
-#define DDB_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */
-#define DDB_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */
-#define DDB_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */
-#define DDB_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */
-
-
-/*
- * Timer Registers
- */
-#define DDB_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */
-#define DDB_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */
-#define DDB_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */
-#define DDB_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */
-#define DDB_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */
-#define DDB_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */
-#define DDB_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */
-#define DDB_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */
-
-
-/*
- * PCI Configuration Space Registers
- */
-#define DDB_PCI_BASE 0x0200
-
-#define DDB_VID 0x0200 /* PCI Vendor ID [R] */
-#define DDB_DID 0x0202 /* PCI Device ID [R] */
-#define DDB_PCICMD 0x0204 /* PCI Command [R/W] */
-#define DDB_PCISTS 0x0206 /* PCI Status [R/W] */
-#define DDB_REVID 0x0208 /* PCI Revision ID [R] */
-#define DDB_CLASS 0x0209 /* PCI Class Code [R] */
-#define DDB_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
-#define DDB_MLTIM 0x020D /* PCI Latency Timer [R/W] */
-#define DDB_HTYPE 0x020E /* PCI Header Type [R] */
-#define DDB_BIST 0x020F /* BIST [R] (unimplemented) */
-#define DDB_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
-#define DDB_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
-#define DDB_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
-#define DDB_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
- /* (unimplemented) */
-#define DDB_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
-#define DDB_SSID 0x022E /* PCI Sub-System ID [R/W] */
-#define DDB_ROM 0x0230 /* Expansion ROM Base Address [R] */
- /* (unimplemented) */
-#define DDB_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
-#define DDB_INTPIN 0x023D /* PCI Interrupt Pin [R] */
-#define DDB_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
-#define DDB_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
-#define DDB_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
-#define DDB_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
-#define DDB_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
-#define DDB_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
-#define DDB_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
-#define DDB_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
-#define DDB_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
-#define DDB_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
-
-
-/*
- * Nile 4 Register Access
- */
-
-static inline void ddb_sync(void)
-{
- volatile u32 *p = (volatile u32 *)0xbfc00000;
- (void)(*p);
-}
-
-static inline void ddb_out32(u32 offset, u32 val)
-{
- *(volatile u32 *)(DDB_BASE+offset) = val;
- ddb_sync();
-}
-
-static inline u32 ddb_in32(u32 offset)
-{
- u32 val = *(volatile u32 *)(DDB_BASE+offset);
- ddb_sync();
- return val;
-}
-
-static inline void ddb_out16(u32 offset, u16 val)
-{
- *(volatile u16 *)(DDB_BASE+offset) = val;
- ddb_sync();
-}
-
-static inline u16 ddb_in16(u32 offset)
-{
- u16 val = *(volatile u16 *)(DDB_BASE+offset);
- ddb_sync();
- return val;
-}
-
-static inline void ddb_out8(u32 offset, u8 val)
-{
- *(volatile u8 *)(DDB_BASE+offset) = val;
- ddb_sync();
-}
-
-static inline u8 ddb_in8(u32 offset)
-{
- u8 val = *(volatile u8 *)(DDB_BASE+offset);
- ddb_sync();
- return val;
-}
-
-
-/*
- * Physical Device Address Registers
- */
-
-extern u32
-ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible);
-extern void
-ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
- int on_memory_bus, int pci_visible);
-
-/*
- * PCI Master Registers
- */
-
-#define DDB_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
-#define DDB_PCICMD_IO 1 /* PCI I/O Space */
-#define DDB_PCICMD_MEM 3 /* PCI Memory Space */
-#define DDB_PCICMD_CFG 5 /* PCI Configuration Space */
-
-/*
- * additional options for pci init reg (no shifting needed)
- */
-#define DDB_PCI_CFGTYPE1 0x200 /* for pci init0/1 regs */
-#define DDB_PCI_ACCESS_32 0x10 /* for pci init0/1 regs */
-
-
-extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options);
-
-/*
- * we need to reset pci bus when we start up and shutdown
- */
-extern void ddb_pci_reset_bus(void);
-
-
-/*
- * include the board dependent part
- */
-#if defined(CONFIG_DDB5477)
-#include <asm/ddb5xxx/ddb5477.h>
-#else
-#error "Unknown DDB board!"
-#endif
-
-#endif /* __ASM_DDB5XXX_DDB5XXX_H */
#ifdef CONFIG_MIPS32_N32
#define __SET_PERSONALITY32_N32() \
do { \
- current->thread.mflags |= MF_N32; \
+ set_thread_flag(TIF_32BIT_ADDR); \
current->thread.abi = &mips_abi_n32; \
} while (0)
#else
#ifdef CONFIG_MIPS32_O32
#define __SET_PERSONALITY32_O32() \
do { \
- current->thread.mflags |= MF_O32; \
+ set_thread_flag(TIF_32BIT_REGS); \
+ set_thread_flag(TIF_32BIT_ADDR); \
current->thread.abi = &mips_abi_32; \
} while (0)
#else
#define SET_PERSONALITY(ex, ibcs2) \
do { \
- current->thread.mflags &= ~MF_ABI_MASK; \
+ clear_thread_flag(TIF_32BIT_REGS); \
+ clear_thread_flag(TIF_32BIT_ADDR); \
+ \
if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
__SET_PERSONALITY32(ex); \
- else { \
- current->thread.mflags |= MF_N64; \
+ else \
current->thread.abi = &mips_abi; \
- } \
\
if (ibcs2) \
set_personality(PER_SVR4); \
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
* Copyright (C) MIPS Technologies, Inc.
* written by Ralf Baechle <ralf@linux-mips.org>
*/
__asm__ __volatile__ (#name); \
}
+/*
+ * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
+ */
+extern void mips_ihb(void);
+
#endif
ASMMACRO(_ssnop,
--- /dev/null
+#ifndef __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_llsc 1
+#define cpu_has_64bits 1
+#define cpu_has_inclusive_pcaches 0
+
+#define cpu_has_mips16 0
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+#define cpu_has_vtag_icache 0
+#define cpu_has_ic_fills_f_dc 0
+#define cpu_has_dsp 0
+#define cpu_has_mipsmt 0
+#define cpu_has_userlocal 0
+
+#define cpu_has_mips32r1 0
+#define cpu_has_mips32r2 0
+#define cpu_has_mips64r1 0
+#define cpu_has_mips64r2 0
+
+#endif /* __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H */
--- /dev/null
+#ifndef __ASM_MACH_TX49XX_KMALLOC_H
+#define __ASM_MACH_TX49XX_KMALLOC_H
+
+/*
+ * All happy, no need to define ARCH_KMALLOC_MINALIGN
+ */
+
+#endif /* __ASM_MACH_TX49XX_KMALLOC_H */
#define MIPS_REVISION_CORID_CORE_FPGAR2 8
#define MIPS_REVISION_CORID_CORE_FPGA3 9
#define MIPS_REVISION_CORID_CORE_24K 10
+#define MIPS_REVISION_CORID_CORE_FPGA4 11
/**** Artificial corid defines ****/
/*
#include <linux/cpumask.h>
+/*
+ * How many VPEs and TCs is Linux allowed to use? 0 means no limit.
+ */
+extern int tclimit;
+extern int vpelimit;
+
extern cpumask_t mt_fpu_cpumask;
extern unsigned long mt_fpemul_threshold;
char* (*gets) (char*);
union {
int (*smpfork) (unsigned long cp, char *sp);
- int (*cpustart) (long, long, long, long);
+ int (*cpustart) (long, void (*)(void), void *, long);
} _s;
int (*semlock) (int sem);
void (*semunlock) (int sem);
* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
-#define TASK_UNMAPPED_BASE ((current->thread.mflags & MF_32BIT_ADDR) ? \
- PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
+#define TASK_UNMAPPED_BASE \
+ (test_thread_flag(TIF_32BIT_ADDR) ? \
+ PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
#endif
#define NUM_FPU_REGS 32
unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
unsigned long error_code;
unsigned long trap_no;
-#define MF_FIXADE 1 /* Fix address errors in software */
-#define MF_LOGADE 2 /* Log address errors to syslog */
-#define MF_32BIT_REGS 4 /* also implies 16/32 fprs */
-#define MF_32BIT_ADDR 8 /* 32-bit address space (o32/n32) */
-#define MF_FPUBOUND 0x10 /* thread bound to FPU-full CPU set */
- unsigned long mflags;
unsigned long irix_trampoline; /* Wheee... */
unsigned long irix_oldctx;
struct mips_abi *abi;
};
-#define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR)
-#define MF_O32 (MF_32BIT_REGS | MF_32BIT_ADDR)
-#define MF_N32 MF_32BIT_ADDR
-#define MF_N64 0
-
#ifdef CONFIG_MIPS_MT_FPAFF
#define FPAFF_INIT \
.emulated_fp = 0, \
.cp0_baduaddr = 0, \
.error_code = 0, \
.trap_no = 0, \
- /* \
- * For now the default is to fix address errors \
- */ \
- .mflags = MF_FIXADE, \
.irix_trampoline = 0, \
.irix_oldctx = 0, \
}
--- /dev/null
+#ifndef __ASM_SECCOMP_H
+
+#include <linux/thread_info.h>
+#include <linux/unistd.h>
+
+#define __NR_seccomp_read __NR_read
+#define __NR_seccomp_write __NR_write
+#define __NR_seccomp_exit __NR_exit
+#define __NR_seccomp_sigreturn __NR_rt_sigreturn
+
+/*
+ * Kludge alert:
+ *
+ * The generic seccomp code currently allows only a single compat ABI. Until
+ * this is fixed we priorize O32 as the compat ABI over N32.
+ */
+#ifdef CONFIG_MIPS32_O32
+
+#define TIF_32BIT TIF_32BIT_REGS
+
+#define __NR_seccomp_read_32 4003
+#define __NR_seccomp_write_32 4004
+#define __NR_seccomp_exit_32 4001
+#define __NR_seccomp_sigreturn_32 4193 /* rt_sigreturn */
+
+#elif defined(CONFIG_MIPS32_N32)
+
+#define TIF_32BIT _TIF_32BIT_ADDR
+
+#define __NR_seccomp_read_32 6000
+#define __NR_seccomp_write_32 6001
+#define __NR_seccomp_exit_32 6058
+#define __NR_seccomp_sigreturn_32 6211 /* rt_sigreturn */
+
+#endif /* CONFIG_MIPS32_O32 */
+
+#endif /* __ASM_SECCOMP_H */
#define __mips_mt_fpaff_switch_to(prev) \
do { \
+ struct thread_info *__prev_ti = task_thread_info(prev); \
+ \
if (cpu_has_fpu && \
- (prev->thread.mflags & MF_FPUBOUND) && \
- (!(KSTK_STATUS(prev) & ST0_CU1))) { \
- prev->thread.mflags &= ~MF_FPUBOUND; \
+ test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
+ (!(KSTK_STATUS(prev) & ST0_CU1))) { \
+ clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
prev->cpus_allowed = prev->thread.user_cpus_allowed; \
} \
next->thread.emulated_fp = 0; \
{ \
.task = &tsk, \
.exec_domain = &default_exec_domain, \
- .flags = 0, \
+ .flags = _TIF_FIXADE, \
.cpu = 0, \
.preempt_count = 1, \
.addr_limit = KERNEL_DS, \
({ \
struct thread_info *ret; \
\
- ret = kmalloc(THREAD_SIZE, GFP_KERNEL); \
- if (ret) \
- memset(ret, 0, THREAD_SIZE); \
+ ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \
+ \
ret; \
})
#else
#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */
#define TIF_MEMDIE 18
#define TIF_FREEZE 19
+#define TIF_FIXADE 20 /* Fix address errors in software */
+#define TIF_LOGADE 21 /* Log address errors to syslog */
+#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */
+#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */
+#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */
#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
#define _TIF_USEDFPU (1<<TIF_USEDFPU)
#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
#define _TIF_FREEZE (1<<TIF_FREEZE)
+#define _TIF_FIXADE (1<<TIF_FIXADE)
+#define _TIF_LOGADE (1<<TIF_LOGADE)
+#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS)
+#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR)
+#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
/* work to do on interrupt/exception return */
#define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP)
#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
#define RBTX4927_RTL_8019_IRQ (29)
+int toshiba_rbtx4927_irq_nested(int sw_irq);
+
#endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */
#define __NR_signalfd (__NR_Linux + 317)
#define __NR_timerfd (__NR_Linux + 318)
#define __NR_eventfd (__NR_Linux + 319)
+#define __NR_fallocate (__NR_Linux + 320)
/*
* Offset of the last Linux o32 flavoured syscall
*/
-#define __NR_Linux_syscalls 319
+#define __NR_Linux_syscalls 320
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#define __NR_O32_Linux 4000
-#define __NR_O32_Linux_syscalls 319
+#define __NR_O32_Linux_syscalls 320
#if _MIPS_SIM == _MIPS_SIM_ABI64
#define __NR_signalfd (__NR_Linux + 276)
#define __NR_timerfd (__NR_Linux + 277)
#define __NR_eventfd (__NR_Linux + 278)
+#define __NR_fallocate (__NR_Linux + 279)
/*
* Offset of the last Linux 64-bit flavoured syscall
*/
-#define __NR_Linux_syscalls 278
+#define __NR_Linux_syscalls 279
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
#define __NR_64_Linux 5000
-#define __NR_64_Linux_syscalls 278
+#define __NR_64_Linux_syscalls 279
#if _MIPS_SIM == _MIPS_SIM_NABI32
#define __NR_signalfd (__NR_Linux + 280)
#define __NR_timerfd (__NR_Linux + 281)
#define __NR_eventfd (__NR_Linux + 282)
+#define __NR_fallocate (__NR_Linux + 283)
/*
* Offset of the last N32 flavoured syscall
*/
-#define __NR_Linux_syscalls 282
+#define __NR_Linux_syscalls 283
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
#define __NR_N32_Linux 6000
-#define __NR_N32_Linux_syscalls 282
+#define __NR_N32_Linux_syscalls 283
#ifdef __KERNEL__
* exceptions.
*/
#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \
- defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MOMENCO_OCELOT) || \
- defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_SGI_IP32) || \
- defined(CONFIG_WR_PPMC)
+ defined(CONFIG_MIPS_MALTA) || defined(CONFIG_PMC_YOSEMITE) || \
+ defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC)
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#endif
#define WARN_ON(x) ({ \
- typeof(x) __ret_warn_on = (x); \
+ int __ret_warn_on = !!(x); \
if (__builtin_constant_p(__ret_warn_on)) { \
if (__ret_warn_on) \
__WARN(); \
} while (0)
#define WARN_ON(x) ({ \
- typeof(x) __ret_warn_on = (x); \
+ int __ret_warn_on = !!(x); \
if (__builtin_constant_p(__ret_warn_on)) { \
if (__ret_warn_on) \
__WARN(); \
#define MV64x60_64BIT_WIN_COUNT 24
-/* Watchdog Platform Device, Driver Data */
-#define MV64x60_WDT_NAME "wdt"
-
-struct mv64x60_wdt_pdata {
- int timeout; /* watchdog expiry in seconds, default 10 */
- int bus_clk; /* bus clock in MHz, default 133 */
-};
-
/*
* Define a structure that's used to pass in config information to the
* core routines.
#define BUG() __EMIT_BUG(0)
#define WARN_ON(x) ({ \
- typeof(x) __ret_warn_on = (x); \
+ int __ret_warn_on = !!(x); \
if (__builtin_constant_p(__ret_warn_on)) { \
if (__ret_warn_on) \
__EMIT_BUG(BUGFLAG_WARNING); \
} while (0)
#define WARN_ON(x) ({ \
- typeof(x) __ret_warn_on = (x); \
+ int __ret_warn_on = !!(x); \
if (__builtin_constant_p(__ret_warn_on)) { \
if (__ret_warn_on) \
__WARN(); \
u8 mac_addr[6]; /* mac address if non-zero*/
};
+/* Watchdog Platform Device, Driver Data */
+#define MV64x60_WDT_NAME "mv64x60_wdt"
+
+struct mv64x60_wdt_pdata {
+ int timeout; /* watchdog expiry in seconds, default 10 */
+ int bus_clk; /* bus clock in MHz, default 133 */
+};
+
#endif /* __ASM_MV643XX_H */
int __must_check pci_enable_device(struct pci_dev *dev);
int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask);
-int __must_check __pci_reenable_device(struct pci_dev *);
+int __must_check pci_reenable_device(struct pci_dev *);
int __must_check pcim_enable_device(struct pci_dev *pdev);
void pcim_pin_device(struct pci_dev *pdev);
unsigned long max_interval; /* Maximum balance interval ms */
unsigned int busy_factor; /* less balancing by factor if busy */
unsigned int imbalance_pct; /* No balance until over watermark */
- unsigned long long cache_hot_time; /* Task considered cache hot (ns) */
unsigned int cache_nice_tries; /* Leave cache hot tasks for # tries */
unsigned int busy_idx;
unsigned int idle_idx;
void (*set_curr_task) (struct rq *rq);
void (*task_tick) (struct rq *rq, struct task_struct *p);
- void (*task_new) (struct rq *rq, struct task_struct *p);
+ void (*task_new) (struct rq *rq, struct task_struct *p, u64 now);
};
struct load_weight {
struct rb_node run_node;
unsigned int on_rq;
+ u64 exec_start;
+ u64 sum_exec_runtime;
u64 wait_start_fair;
+ u64 sleep_start_fair;
+
+#ifdef CONFIG_SCHEDSTATS
u64 wait_start;
- u64 exec_start;
+ u64 wait_max;
+ s64 sum_wait_runtime;
+
u64 sleep_start;
- u64 sleep_start_fair;
- u64 block_start;
u64 sleep_max;
+ s64 sum_sleep_runtime;
+
+ u64 block_start;
u64 block_max;
u64 exec_max;
- u64 wait_max;
- u64 last_ran;
- u64 sum_exec_runtime;
- s64 sum_wait_runtime;
- s64 sum_sleep_runtime;
unsigned long wait_runtime_overruns;
unsigned long wait_runtime_underruns;
+#endif
+
#ifdef CONFIG_FAIR_GROUP_SCHED
struct sched_entity *parent;
/* rq on which this entity is (to be) queued: */
.max_interval = 64*num_online_cpus(), \
.busy_factor = 128, \
.imbalance_pct = 133, \
- .cache_hot_time = (10*1000000), \
.cache_nice_tries = 1, \
.busy_idx = 3, \
.idle_idx = 3, \
#define NETLBL_SECATTR_CACHE 0x00000002
#define NETLBL_SECATTR_MLS_LVL 0x00000004
#define NETLBL_SECATTR_MLS_CAT 0x00000008
+#define NETLBL_SECATTR_CACHEABLE (NETLBL_SECATTR_MLS_LVL | \
+ NETLBL_SECATTR_MLS_CAT)
struct netlbl_lsm_secattr {
u32 flags;
extern int tcp_v4_tw_remember_stamp(struct inet_timewait_sock *tw);
-extern int tcp_sendmsg(struct kiocb *iocb, struct sock *sk,
+extern int tcp_sendmsg(struct kiocb *iocb, struct socket *sock,
struct msghdr *msg, size_t size);
extern ssize_t tcp_sendpage(struct socket *sock, struct page *page, int offset, size_t size, int flags);
*/
desc->chip->enable(irq);
+ /*
+ * Temporary hack to figure out more about the problem, which
+ * is causing the ancient network cards to die.
+ */
+ if (desc->handle_irq != handle_edge_irq) {
+ WARN_ON_ONCE(1);
+ return;
+ }
+
if ((status & (IRQ_PENDING | IRQ_REPLAY)) == IRQ_PENDING) {
desc->status = (status & ~IRQ_PENDING) | IRQ_REPLAY;
#define WMULT_SHIFT 32
-static inline unsigned long
+static unsigned long
calc_delta_mine(unsigned long delta_exec, unsigned long weight,
struct load_weight *lw)
{
tmp = (tmp * lw->inv_weight) >> WMULT_SHIFT;
}
- return (unsigned long)min(tmp, (u64)sysctl_sched_runtime_limit);
+ return (unsigned long)min(tmp, (u64)(unsigned long)LONG_MAX);
}
static inline unsigned long
lw->inv_weight = 0;
}
-static void __update_curr_load(struct rq *rq, struct load_stat *ls)
-{
- if (rq->curr != rq->idle && ls->load.weight) {
- ls->delta_exec += ls->delta_stat;
- ls->delta_fair += calc_delta_fair(ls->delta_stat, &ls->load);
- ls->delta_stat = 0;
- }
-}
-
-/*
- * Update delta_exec, delta_fair fields for rq.
- *
- * delta_fair clock advances at a rate inversely proportional to
- * total load (rq->ls.load.weight) on the runqueue, while
- * delta_exec advances at the same rate as wall-clock (provided
- * cpu is not idle).
- *
- * delta_exec / delta_fair is a measure of the (smoothened) load on this
- * runqueue over any given interval. This (smoothened) load is used
- * during load balance.
- *
- * This function is called /before/ updating rq->ls.load
- * and when switching tasks.
- */
-static void update_curr_load(struct rq *rq, u64 now)
-{
- struct load_stat *ls = &rq->ls;
- u64 start;
-
- start = ls->load_update_start;
- ls->load_update_start = now;
- ls->delta_stat += now - start;
- /*
- * Stagger updates to ls->delta_fair. Very frequent updates
- * can be expensive.
- */
- if (ls->delta_stat >= sysctl_sched_stat_granularity)
- __update_curr_load(rq, ls);
-}
-
/*
* To aid in avoiding the subversion of "niceness" due to uneven distribution
* of tasks with abnormal "nice" values across CPUs the contribution that
* slice expiry etc.
*/
-/*
- * Assume: static_prio_timeslice(NICE_TO_PRIO(0)) == DEF_TIMESLICE
- * If static_prio_timeslice() is ever changed to break this assumption then
- * this code will need modification
- */
-#define TIME_SLICE_NICE_ZERO DEF_TIMESLICE
-#define load_weight(lp) \
- (((lp) * SCHED_LOAD_SCALE) / TIME_SLICE_NICE_ZERO)
-#define PRIO_TO_LOAD_WEIGHT(prio) \
- load_weight(static_prio_timeslice(prio))
-#define RTPRIO_TO_LOAD_WEIGHT(rp) \
- (PRIO_TO_LOAD_WEIGHT(MAX_RT_PRIO) + load_weight(rp))
-
#define WEIGHT_IDLEPRIO 2
#define WMULT_IDLEPRIO (1 << 31)
/* 15 */ 119304647, 148102320, 186737708, 238609294, 286331153,
};
-static inline void
-inc_load(struct rq *rq, const struct task_struct *p, u64 now)
-{
- update_curr_load(rq, now);
- update_load_add(&rq->ls.load, p->se.load.weight);
-}
-
-static inline void
-dec_load(struct rq *rq, const struct task_struct *p, u64 now)
-{
- update_curr_load(rq, now);
- update_load_sub(&rq->ls.load, p->se.load.weight);
-}
-
-static inline void inc_nr_running(struct task_struct *p, struct rq *rq, u64 now)
-{
- rq->nr_running++;
- inc_load(rq, p, now);
-}
-
-static inline void dec_nr_running(struct task_struct *p, struct rq *rq, u64 now)
-{
- rq->nr_running--;
- dec_load(rq, p, now);
-}
-
static void activate_task(struct rq *rq, struct task_struct *p, int wakeup);
/*
#define sched_class_highest (&rt_sched_class)
+static void __update_curr_load(struct rq *rq, struct load_stat *ls)
+{
+ if (rq->curr != rq->idle && ls->load.weight) {
+ ls->delta_exec += ls->delta_stat;
+ ls->delta_fair += calc_delta_fair(ls->delta_stat, &ls->load);
+ ls->delta_stat = 0;
+ }
+}
+
+/*
+ * Update delta_exec, delta_fair fields for rq.
+ *
+ * delta_fair clock advances at a rate inversely proportional to
+ * total load (rq->ls.load.weight) on the runqueue, while
+ * delta_exec advances at the same rate as wall-clock (provided
+ * cpu is not idle).
+ *
+ * delta_exec / delta_fair is a measure of the (smoothened) load on this
+ * runqueue over any given interval. This (smoothened) load is used
+ * during load balance.
+ *
+ * This function is called /before/ updating rq->ls.load
+ * and when switching tasks.
+ */
+static void update_curr_load(struct rq *rq, u64 now)
+{
+ struct load_stat *ls = &rq->ls;
+ u64 start;
+
+ start = ls->load_update_start;
+ ls->load_update_start = now;
+ ls->delta_stat += now - start;
+ /*
+ * Stagger updates to ls->delta_fair. Very frequent updates
+ * can be expensive.
+ */
+ if (ls->delta_stat >= sysctl_sched_stat_granularity)
+ __update_curr_load(rq, ls);
+}
+
+static inline void
+inc_load(struct rq *rq, const struct task_struct *p, u64 now)
+{
+ update_curr_load(rq, now);
+ update_load_add(&rq->ls.load, p->se.load.weight);
+}
+
+static inline void
+dec_load(struct rq *rq, const struct task_struct *p, u64 now)
+{
+ update_curr_load(rq, now);
+ update_load_sub(&rq->ls.load, p->se.load.weight);
+}
+
+static void inc_nr_running(struct task_struct *p, struct rq *rq, u64 now)
+{
+ rq->nr_running++;
+ inc_load(rq, p, now);
+}
+
+static void dec_nr_running(struct task_struct *p, struct rq *rq, u64 now)
+{
+ rq->nr_running--;
+ dec_load(rq, p, now);
+}
+
static void set_load_weight(struct task_struct *p)
{
task_rq(p)->cfs.wait_runtime -= p->se.wait_runtime;
u64 clock_offset, fair_clock_offset;
clock_offset = old_rq->clock - new_rq->clock;
- fair_clock_offset = old_rq->cfs.fair_clock -
- new_rq->cfs.fair_clock;
- if (p->se.wait_start)
- p->se.wait_start -= clock_offset;
+ fair_clock_offset = old_rq->cfs.fair_clock - new_rq->cfs.fair_clock;
+
if (p->se.wait_start_fair)
p->se.wait_start_fair -= fair_clock_offset;
+ if (p->se.sleep_start_fair)
+ p->se.sleep_start_fair -= fair_clock_offset;
+
+#ifdef CONFIG_SCHEDSTATS
+ if (p->se.wait_start)
+ p->se.wait_start -= clock_offset;
if (p->se.sleep_start)
p->se.sleep_start -= clock_offset;
if (p->se.block_start)
p->se.block_start -= clock_offset;
- if (p->se.sleep_start_fair)
- p->se.sleep_start_fair -= fair_clock_offset;
+#endif
__set_task_cpu(p, new_cpu);
}
static void __sched_fork(struct task_struct *p)
{
p->se.wait_start_fair = 0;
- p->se.wait_start = 0;
p->se.exec_start = 0;
p->se.sum_exec_runtime = 0;
p->se.delta_exec = 0;
p->se.delta_fair_run = 0;
p->se.delta_fair_sleep = 0;
p->se.wait_runtime = 0;
+ p->se.sleep_start_fair = 0;
+
+#ifdef CONFIG_SCHEDSTATS
+ p->se.wait_start = 0;
p->se.sum_wait_runtime = 0;
p->se.sum_sleep_runtime = 0;
p->se.sleep_start = 0;
- p->se.sleep_start_fair = 0;
p->se.block_start = 0;
p->se.sleep_max = 0;
p->se.block_max = 0;
p->se.wait_max = 0;
p->se.wait_runtime_overruns = 0;
p->se.wait_runtime_underruns = 0;
+#endif
INIT_LIST_HEAD(&p->run_list);
p->se.on_rq = 0;
unsigned long flags;
struct rq *rq;
int this_cpu;
+ u64 now;
rq = task_rq_lock(p, &flags);
BUG_ON(p->state != TASK_RUNNING);
this_cpu = smp_processor_id(); /* parent's CPU */
+ now = rq_clock(rq);
p->prio = effective_prio(p);
- if (!sysctl_sched_child_runs_first || (clone_flags & CLONE_VM) ||
- task_cpu(p) != this_cpu || !current->se.on_rq) {
+ if (!p->sched_class->task_new || !sysctl_sched_child_runs_first ||
+ (clone_flags & CLONE_VM) || task_cpu(p) != this_cpu ||
+ !current->se.on_rq) {
+
activate_task(rq, p, 0);
} else {
/*
* Let the scheduling class do new task startup
* management (if any):
*/
- p->sched_class->task_new(rq, p);
+ p->sched_class->task_new(rq, p, now);
+ inc_nr_running(p, rq, now);
}
check_preempt_curr(rq, p);
task_rq_unlock(rq, &flags);
schedstat_inc(sd, alb_cnt);
if (move_tasks(target_rq, target_cpu, busiest_rq, 1,
- RTPRIO_TO_LOAD_WEIGHT(100), sd, CPU_IDLE,
- NULL))
+ ULONG_MAX, sd, CPU_IDLE, NULL))
schedstat_inc(sd, alb_pushed);
else
schedstat_inc(sd, alb_failed);
sizeof(int), 0644, proc_dointvec_minmax);
set_table_entry(&table[8], 9, "imbalance_pct", &sd->imbalance_pct,
sizeof(int), 0644, proc_dointvec_minmax);
- set_table_entry(&table[9], 10, "cache_hot_time", &sd->cache_hot_time,
- sizeof(long long), 0644, proc_doulongvec_minmax);
set_table_entry(&table[10], 11, "cache_nice_tries",
&sd->cache_nice_tries,
sizeof(int), 0644, proc_dointvec_minmax);
do_each_thread(g, p) {
p->se.fair_key = 0;
p->se.wait_runtime = 0;
+ p->se.exec_start = 0;
p->se.wait_start_fair = 0;
+ p->se.sleep_start_fair = 0;
+#ifdef CONFIG_SCHEDSTATS
p->se.wait_start = 0;
- p->se.exec_start = 0;
p->se.sleep_start = 0;
- p->se.sleep_start_fair = 0;
p->se.block_start = 0;
+#endif
task_rq(p)->cfs.fair_clock = 0;
task_rq(p)->clock = 0;
(long long)p->se.wait_runtime,
(long long)(p->nvcsw + p->nivcsw),
p->prio,
+#ifdef CONFIG_SCHEDSTATS
(long long)p->se.sum_exec_runtime,
(long long)p->se.sum_wait_runtime,
(long long)p->se.sum_sleep_runtime,
(long long)p->se.wait_runtime_overruns,
- (long long)p->se.wait_runtime_underruns);
+ (long long)p->se.wait_runtime_underruns
+#else
+ 0LL, 0LL, 0LL, 0LL, 0LL
+#endif
+ );
}
static void print_rq(struct seq_file *m, struct rq *rq, int rq_cpu, u64 now)
u64 now = ktime_to_ns(ktime_get());
int cpu;
- SEQ_printf(m, "Sched Debug Version: v0.05, %s %.*s\n",
+ SEQ_printf(m, "Sched Debug Version: v0.05-v20, %s %.*s\n",
init_utsname()->release,
(int)strcspn(init_utsname()->version, " "),
init_utsname()->version);
#define P(F) \
SEQ_printf(m, "%-25s:%20Ld\n", #F, (long long)p->F)
- P(se.wait_start);
+ P(se.wait_runtime);
P(se.wait_start_fair);
P(se.exec_start);
- P(se.sleep_start);
P(se.sleep_start_fair);
+ P(se.sum_exec_runtime);
+
+#ifdef CONFIG_SCHEDSTATS
+ P(se.wait_start);
+ P(se.sleep_start);
P(se.block_start);
P(se.sleep_max);
P(se.block_max);
P(se.exec_max);
P(se.wait_max);
- P(se.wait_runtime);
P(se.wait_runtime_overruns);
P(se.wait_runtime_underruns);
P(se.sum_wait_runtime);
- P(se.sum_exec_runtime);
+#endif
SEQ_printf(m, "%-25s:%20Ld\n",
"nr_switches", (long long)(p->nvcsw + p->nivcsw));
P(se.load.weight);
void proc_sched_set_task(struct task_struct *p)
{
+#ifdef CONFIG_SCHEDSTATS
p->se.sleep_max = p->se.block_max = p->se.exec_max = p->se.wait_max = 0;
p->se.wait_runtime_overruns = p->se.wait_runtime_underruns = 0;
+#endif
p->se.sum_exec_runtime = 0;
}
return;
delta_exec = curr->delta_exec;
-#ifdef CONFIG_SCHEDSTATS
- if (unlikely(delta_exec > curr->exec_max))
- curr->exec_max = delta_exec;
-#endif
+ schedstat_set(curr->exec_max, max((u64)delta_exec, curr->exec_max));
curr->sum_exec_runtime += delta_exec;
cfs_rq->exec_clock += delta_exec;
update_stats_wait_start(struct cfs_rq *cfs_rq, struct sched_entity *se, u64 now)
{
se->wait_start_fair = cfs_rq->fair_clock;
- se->wait_start = now;
+ schedstat_set(se->wait_start, now);
}
/*
{
unsigned long delta_fair = se->delta_fair_run;
-#ifdef CONFIG_SCHEDSTATS
- {
- s64 delta_wait = now - se->wait_start;
- if (unlikely(delta_wait > se->wait_max))
- se->wait_max = delta_wait;
- }
-#endif
+ schedstat_set(se->wait_max, max(se->wait_max, now - se->wait_start));
if (unlikely(se->load.weight != NICE_0_LOAD))
delta_fair = calc_weighted(delta_fair, se->load.weight,
}
se->wait_start_fair = 0;
- se->wait_start = 0;
+ schedstat_set(se->wait_start, 0);
}
static inline void
* monopolize the CPU. Note: the parent runqueue is locked,
* the child is not running yet.
*/
-static void task_new_fair(struct rq *rq, struct task_struct *p)
+static void task_new_fair(struct rq *rq, struct task_struct *p, u64 now)
{
struct cfs_rq *cfs_rq = task_cfs_rq(p);
struct sched_entity *se = &p->se;
- u64 now = rq_clock(rq);
sched_info_queued(p);
p->se.wait_runtime = -(sysctl_sched_granularity / 2);
__enqueue_entity(cfs_rq, se);
- inc_nr_running(p, rq, now);
}
#ifdef CONFIG_FAIR_GROUP_SCHED
delta_exec = now - curr->se.exec_start;
if (unlikely((s64)delta_exec < 0))
delta_exec = 0;
- if (unlikely(delta_exec > curr->se.exec_max))
- curr->se.exec_max = delta_exec;
+
+ schedstat_set(curr->se.exec_max, max(curr->se.exec_max, delta_exec));
curr->se.sum_exec_runtime += delta_exec;
curr->se.exec_start = now;
requeue_task_rt(rq, p);
}
-/*
- * No parent/child timeslice management necessary for RT tasks,
- * just activate them:
- */
-static void task_new_rt(struct rq *rq, struct task_struct *p)
-{
- activate_task(rq, p, 1);
-}
-
static struct sched_class rt_sched_class __read_mostly = {
.enqueue_task = enqueue_task_rt,
.dequeue_task = dequeue_task_rt,
.load_balance = load_balance_rt,
.task_tick = task_tick_rt,
- .task_new = task_new_rt,
};
}
# define schedstat_inc(rq, field) do { (rq)->field++; } while (0)
# define schedstat_add(rq, field, amt) do { (rq)->field += (amt); } while (0)
+# define schedstat_set(var, val) do { var = (val); } while (0)
#else /* !CONFIG_SCHEDSTATS */
static inline void
rq_sched_info_arrive(struct rq *rq, unsigned long long delta)
{}
# define schedstat_inc(rq, field) do { } while (0)
# define schedstat_add(rq, field, amt) do { } while (0)
+# define schedstat_set(var, val) do { } while (0)
#endif
#if defined(CONFIG_SCHEDSTATS) || defined(CONFIG_TASK_DELAY_ACCT)
.shutdown = inet_shutdown,
.setsockopt = sock_common_setsockopt,
.getsockopt = sock_common_getsockopt,
- .sendmsg = inet_sendmsg,
+ .sendmsg = tcp_sendmsg,
.recvmsg = sock_common_recvmsg,
.mmap = sock_no_mmap,
.sendpage = tcp_sendpage,
struct ct_expect_iter_state *st;
int ret;
- st = kmalloc(sizeof(struct ct_expect_iter_state), GFP_KERNEL);
- if (st == NULL)
+ st = kzalloc(sizeof(struct ct_expect_iter_state), GFP_KERNEL);
+ if (!st)
return -ENOMEM;
ret = seq_open(file, &exp_seq_ops);
if (ret)
goto out_free;
seq = file->private_data;
seq->private = st;
- memset(st, 0, sizeof(struct ct_expect_iter_state));
return ret;
out_free:
kfree(st);
{
struct seq_file *seq;
int rc = -ENOMEM;
- struct raw_iter_state *s = kmalloc(sizeof(*s), GFP_KERNEL);
+ struct raw_iter_state *s;
+ s = kzalloc(sizeof(*s), GFP_KERNEL);
if (!s)
goto out;
rc = seq_open(file, &raw_seq_ops);
seq = file->private_data;
seq->private = s;
- memset(s, 0, sizeof(*s));
out:
return rc;
out_kfree:
{
struct seq_file *seq;
int rc = -ENOMEM;
- struct rt_cache_iter_state *s = kmalloc(sizeof(*s), GFP_KERNEL);
+ struct rt_cache_iter_state *s;
+ s = kzalloc(sizeof(*s), GFP_KERNEL);
if (!s)
goto out;
rc = seq_open(file, &rt_cache_seq_ops);
goto out_kfree;
seq = file->private_data;
seq->private = s;
- memset(s, 0, sizeof(*s));
out:
return rc;
out_kfree:
return tmp;
}
-int tcp_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg,
+int tcp_sendmsg(struct kiocb *iocb, struct socket *sock, struct msghdr *msg,
size_t size)
{
+ struct sock *sk = sock->sk;
struct iovec *iov;
struct tcp_sock *tp = tcp_sk(sk);
struct sk_buff *skb;
.shutdown = tcp_shutdown,
.setsockopt = tcp_setsockopt,
.getsockopt = tcp_getsockopt,
- .sendmsg = tcp_sendmsg,
.recvmsg = tcp_recvmsg,
.backlog_rcv = tcp_v4_do_rcv,
.hash = tcp_v4_hash,
.shutdown = inet_shutdown, /* ok */
.setsockopt = sock_common_setsockopt, /* ok */
.getsockopt = sock_common_getsockopt, /* ok */
- .sendmsg = inet_sendmsg, /* ok */
+ .sendmsg = tcp_sendmsg, /* ok */
.recvmsg = sock_common_recvmsg, /* ok */
.mmap = sock_no_mmap,
.sendpage = tcp_sendpage,
.shutdown = tcp_shutdown,
.setsockopt = tcp_setsockopt,
.getsockopt = tcp_getsockopt,
- .sendmsg = tcp_sendmsg,
.recvmsg = tcp_recvmsg,
.backlog_rcv = tcp_v6_do_rcv,
.hash = tcp_v6_hash,
x->sel.prefixlen_s = addr->sadb_address_prefixlen;
}
+ if (!x->sel.family)
+ x->sel.family = x->props.family;
+
if (ext_hdrs[SADB_X_EXT_NAT_T_TYPE-1]) {
struct sadb_x_nat_t_type* n_type;
struct xfrm_encap_tmpl *natt;
struct ct_expect_iter_state *st;
int ret;
- st = kmalloc(sizeof(struct ct_expect_iter_state), GFP_KERNEL);
- if (st == NULL)
+ st = kzalloc(sizeof(struct ct_expect_iter_state), GFP_KERNEL);
+ if (!st)
return -ENOMEM;
ret = seq_open(file, &exp_seq_ops);
if (ret)
goto out_free;
seq = file->private_data;
seq->private = st;
- memset(st, 0, sizeof(struct ct_expect_iter_state));
return ret;
out_free:
kfree(st);
if (audit_info->secid != 0 &&
security_secid_to_secctx(audit_info->secid,
&secctx,
- &secctx_len) == 0)
+ &secctx_len) == 0) {
audit_log_format(audit_buf, " subj=%s", secctx);
+ security_release_secctx(secctx, secctx_len);
+ }
return audit_buf;
}
struct tipc_msg *msg = buf_msg(crs);
if ((msg_user(msg) == MSG_BUNDLER) && split_bundles) {
- u32 msgcount = msg_msgcnt(msg);
struct tipc_msg *m = msg_get_wrapped(msg);
unchar* pos = (unchar*)m;
+ msgcount = msg_msgcnt(msg);
while (msgcount--) {
msg_set_seqno(m,msg_seqno(msg));
tipc_link_tunnel(l_ptr, &tunnel_hdr, m,
* sequence overlapping with the requested sequence
*/
-void tipc_nameseq_subscribe(struct name_seq *nseq, struct subscription *s)
+static void tipc_nameseq_subscribe(struct name_seq *nseq, struct subscription *s)
{
struct sub_seq *sseq = nseq->sseqs;
char addr_string[16];
if (n_ptr->link_cnt >= 2) {
- char addr_string[16];
-
err("Attempt to create third link to %s\n",
addr_string_fill(addr_string, n_ptr->addr));
return NULL;
#include <linux/capability.h>
#include <linux/errno.h> /* return codes */
#include <linux/kernel.h>
-#include <linux/init.h>
#include <linux/module.h> /* support for loadable modules */
#include <linux/slab.h> /* kmalloc(), kfree() */
#include <linux/mm.h>
}
if (sid != 0 &&
- security_secid_to_secctx(sid, &secctx, &secctx_len) == 0)
+ security_secid_to_secctx(sid, &secctx, &secctx_len) == 0) {
audit_log_format(audit_buf, " subj=%s", secctx);
- else
+ security_release_secctx(secctx, secctx_len);
+ } else
audit_log_task_context(audit_buf);
if (xp) {
static void selinux_release_secctx(char *secdata, u32 seclen)
{
- if (secdata)
- kfree(secdata);
+ kfree(secdata);
}
#ifdef CONFIG_KEYS
netlbl_secattr_init(&secattr);
rc = netlbl_skbuff_getattr(skb, &secattr);
- if (rc == 0 && secattr.flags != NETLBL_SECATTR_NONE)
+ if (rc == 0 && secattr.flags != NETLBL_SECATTR_NONE) {
rc = security_netlbl_secattr_to_sid(&secattr, base_sid, sid);
- else
+ if (rc == 0 &&
+ (secattr.flags & NETLBL_SECATTR_CACHEABLE) &&
+ (secattr.flags & NETLBL_SECATTR_CACHE))
+ netlbl_cache_add(skb, &secattr);
+ } else
*sid = SECSID_NULL;
netlbl_secattr_destroy(&secattr);
netlbl_secattr_init(&secattr);
rc = netlbl_skbuff_getattr(skb, &secattr);
- if (rc == 0 && secattr.flags != NETLBL_SECATTR_NONE)
+ if (rc == 0 && secattr.flags != NETLBL_SECATTR_NONE) {
rc = security_netlbl_secattr_to_sid(&secattr,
SECINITSID_NETMSG,
&nlbl_sid);
- else
+ if (rc == 0 &&
+ (secattr.flags & NETLBL_SECATTR_CACHEABLE) &&
+ (secattr.flags & NETLBL_SECATTR_CACHE))
+ netlbl_cache_add(skb, &secattr);
+ } else
nlbl_sid = SECINITSID_UNLABELED;
netlbl_secattr_destroy(&secattr);
if (rc != 0)
projects / firefly-linux-kernel-4.4.55.git / commitdiff