[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRB instructions.

The ARM ARM prohibits STRB instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRB instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213750 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 5e074c4e429f60d7ae6d443328163ef91dae9ce0..ccef6c3b6cbf0d94c9f5d8b5c47baa4e7aa2303e 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5731,7 +5731,11 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
   case ARM::STR_PRE_IMM:
   case ARM::STR_PRE_REG:
   case ARM::STR_POST_IMM:
-  case ARM::STR_POST_REG: {
+  case ARM::STR_POST_REG:
+  case ARM::STRB_PRE_IMM:
+  case ARM::STRB_PRE_REG:
+  case ARM::STRB_POST_IMM:
+  case ARM::STRB_POST_REG: {
     // Rt must be different from Rn.
     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());

diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s
index e26566df8eea51e90f213b36af33b5927913c853..25eb6f227a63f3e952600de46717ccb975fd2024 100644 (file)
--- a/test/MC/ARM/diagnostics.s
+++ b/test/MC/ARM/diagnostics.s
@@ -496,6 +496,10 @@ foo2:
         str r0, [r0, r1]!
         str r0, [r0], #4
         str r0, [r0], r1
+        strb r0, [r0, #1]!
+        strb r0, [r0, r1]!
+        strb r0, [r0], #1
+        strb r0, [r0], r1
 @ CHECK-ERRORS: error: source register and base register can't be identical
 @ CHECK-ERRORS: str r0, [r0, #4]!
 @ CHECK-ERRORS:         ^
@@ -508,3 +512,15 @@ foo2:
 @ CHECK-ERRORS: error: source register and base register can't be identical
 @ CHECK-ERRORS: str r0, [r0], r1
 @ CHECK-ERRORS:         ^
+@ CHECK-ERRORS: error: source register and base register can't be identical
+@ CHECK-ERRORS: strb r0, [r0, #1]!
+@ CHECK-ERRORS:          ^
+@ CHECK-ERRORS: error: source register and base register can't be identical
+@ CHECK-ERRORS: strb r0, [r0, r1]!
+@ CHECK-ERRORS:          ^
+@ CHECK-ERRORS: error: source register and base register can't be identical
+@ CHECK-ERRORS: strb r0, [r0], #1
+@ CHECK-ERRORS:          ^
+@ CHECK-ERRORS: error: source register and base register can't be identical
+@ CHECK-ERRORS: strb r0, [r0], r1
+@ CHECK-ERRORS:          ^