clk: rockchip: fix rk3288 pll settings

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 19e006ef7c188ebb99714ca72f928a2dfc7728f3..0b3a7cc802e2eab3a48c3da352a6f730b58fada3 100755 (executable)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -287,7 +287,7 @@
                        <&clk_i2s_pll &clk_cpll>;
                rockchip,clocks-init-rate =
                        <&clk_core 792000000>,  <&clk_gpll 594000000>,
-                       <&clk_cpll 393216000>,  <&clk_npll 500000000>,
+                       <&clk_cpll 384000000>,  <&clk_npll 500000000>,
                        <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
                        <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
                        <&clk_crypto 150000000>,        <&aclk_peri 300000000>,

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 428d9edf6fa994509c7ddcfff65b5a990270e74b..df21324825eee1af1fe652cfb6948e54e9e11cd1 100644 (file)
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -11,7 +11,9 @@ static const struct pll_clk_set pll_com_table[] = {
        _RK3188_PLL_SET_CLKS(891000,    8,      594,    2),
        _RK3188_PLL_SET_CLKS(768000,    1,      64,     2),
        _RK3188_PLL_SET_CLKS(594000,    2,      198,    4),
+       _RK3188_PLL_SET_CLKS(500000,    3,      250,    4),
        _RK3188_PLL_SET_CLKS(408000,    1,      68,     4),
+       _RK3188_PLL_SET_CLKS(396000,    1,      66,     4),
        _RK3188_PLL_SET_CLKS(384000,    2,      128,    4),
        _RK3188_PLL_SET_CLKS(360000,    1,      60,     4),
        _RK3188_PLL_SET_CLKS(300000,    1,      50,     4),