rk3288: enable camera isp clocks
authorzyh <zyh@rock-chips.com>
Wed, 2 Apr 2014 03:50:33 +0000 (11:50 +0800)
committerzyh <zyh@rock-chips.com>
Wed, 2 Apr 2014 03:50:33 +0000 (11:50 +0800)
arch/arm/boot/dts/rk3288.dtsi
drivers/media/video/rk_camsys/camsys_marvin.c
drivers/media/video/rk_camsys/camsys_marvin.h

index 7f88f7343cac48c658aacd7b410eecc3ca5dbab2..fa5bc949b08e5d554817aedb0ac2cab946a5e191 100755 (executable)
                compatible = "rockchip,isp";
                reg = <0xff910000 0x10000>;
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&dummy>, <&clk_cif_out>;
-                       clock_names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_vipout";
+               clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>,<&clk_gates5 15>;
+                       clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_vipout","clk_mipi_24m";
                        pinctrl-names = "default", "isp_dvp8bit","isp_dvp10bit","isp_dvp12bit";
                        pinctrl-0 = <&isp_mipi>;
                        pinctrl-1 = <&isp_mipi &isp_dvp_sync_d2d9>;
index 0a7a0282dc5e8a0805859886626f3c3723f4f31f..041a3a562d604f9e6e4e52bbe18cf7985019c31d 100755 (executable)
@@ -133,8 +133,8 @@ static int camsys_mrv_clkin_cb(void *ptr, unsigned int on)
         clk_prepare_enable(clk->aclk_isp);
         clk_prepare_enable(clk->hclk_isp);
         clk_prepare_enable(clk->isp);
-        clk_prepare_enable( clk->isp_jpe);
-        
+        clk_prepare_enable(clk->isp_jpe);
+        clk_prepare_enable(clk->clk_mipi_24m); 
 
  //       clk_enable(clk->pd_isp);
   //      clk_enable(clk->aclk_isp);
@@ -151,10 +151,11 @@ static int camsys_mrv_clkin_cb(void *ptr, unsigned int on)
     } else if (!on && clk->in_on) {
 
 
-         clk_disable_unprepare(clk->aclk_isp);
+        clk_disable_unprepare(clk->aclk_isp);
         clk_disable_unprepare(clk->hclk_isp);
         clk_disable_unprepare(clk->isp);
-        clk_disable_unprepare( clk->isp_jpe);
+        clk_disable_unprepare(clk->isp_jpe);
+        clk_disable_unprepare(clk->clk_mipi_24m); 
 
   //      clk_disable(clk->pd_isp);
   //      clk_disable(clk->aclk_isp);
@@ -337,16 +338,16 @@ int camsys_mrv_probe_cb(struct platform_device *pdev, camsys_dev_t *camsys_dev)
      
    // mrv_clk->pd_isp = devm_clk_get(&pdev->dev, "pd_isp");
     mrv_clk->pd_isp = NULL;
-    mrv_clk->aclk_isp = devm_clk_get(&pdev->dev, "g_aclk_isp");
-    mrv_clk->hclk_isp = devm_clk_get(&pdev->dev, "g_hclk_isp");
+    mrv_clk->aclk_isp = devm_clk_get(&pdev->dev, "aclk_isp");
+    mrv_clk->hclk_isp = devm_clk_get(&pdev->dev, "hclk_isp");
     mrv_clk->isp = devm_clk_get(&pdev->dev, "clk_isp");
     mrv_clk->isp_jpe = devm_clk_get(&pdev->dev, "clk_isp_jpe");
     mrv_clk->pclkin_isp = devm_clk_get(&pdev->dev, "pclkin_isp");
-    mrv_clk->cif_clk_out = devm_clk_get(&pdev->dev, "clk_cif_out");
-    
+    mrv_clk->cif_clk_out = devm_clk_get(&pdev->dev, "clk_vipout");
+    mrv_clk->clk_mipi_24m = devm_clk_get(&pdev->dev,"clk_mipi_24m"); 
     if (/*IS_ERR_OR_NULL(mrv_clk->pd_isp) ||*/ IS_ERR_OR_NULL(mrv_clk->aclk_isp) || IS_ERR_OR_NULL(mrv_clk->hclk_isp) ||
         IS_ERR_OR_NULL(mrv_clk->isp) || IS_ERR_OR_NULL(mrv_clk->isp_jpe) /*|| IS_ERR_OR_NULL(mrv_clk->pclkin_isp)*/ || 
-        IS_ERR_OR_NULL(mrv_clk->cif_clk_out)) {
+        IS_ERR_OR_NULL(mrv_clk->cif_clk_out) || IS_ERR_OR_NULL(mrv_clk->clk_mipi_24m)) {
         camsys_err("Get %s clock resouce failed!\n",miscdev_name);
         err = -EINVAL;
         goto clk_failed;
index 7b92eddfb11c9cba88335f6935d71d3e117bb284..dfdd0dbd40f8bcaec97a78fb66280a01fc06dd17 100755 (executable)
@@ -29,6 +29,7 @@ typedef struct camsys_mrv_clk_s {
     struct clk      *isp;
     struct clk      *isp_jpe;
     struct clk      *pclkin_isp;
+    struct clk      *clk_mipi_24m;
     bool             in_on;
 
     struct clk      *cif_clk_out;