Add MVT::is128BitVector and is64BitVector. Shrink

unaligned load/store code using them.  Per review
of unaligned load/store vector patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47782 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h
index f2b8dfcccaddaccd0c23a9c5b233b3a8e9ebda0b..6b20b7d6a990723672a6f1c686f19c31341d1af4 100644 (file)
--- a/include/llvm/CodeGen/ValueTypes.h
+++ b/include/llvm/CodeGen/ValueTypes.h
@@ -250,6 +250,19 @@ namespace MVT {  // MVT = Machine Value Types
     return (getSizeInBits(VT) + 7)/8*8;
   }
 
+  /// MVT::is64BitVector - Return true if this is a 64-bit vector type.
+  static inline bool is64BitVector(ValueType VT) {
+    return (VT==v8i8 || VT==v4i16 || VT==v2i32 || VT==v1i64 || VT==v2f32 ||
+            (isExtendedVT(VT) && isVector(VT) && getSizeInBits(VT)==64));
+  }
+
+  /// MVT::is128BitVector - Return true if this is a 128-bit vector type.
+  static inline bool is128BitVector(ValueType VT) {
+    return (VT==v16i8 || VT==v8i16 || VT==v4i32 || VT==v2i64 || 
+            VT==v4f32 || VT==v2f64 ||
+            (isExtendedVT(VT) && isVector(VT) && getSizeInBits(VT)==128));
+  }
+
   /// MVT::getIntegerType - Returns the ValueType that represents an integer
   /// with the given number of bits.
   ///

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 2acb1e36684bcc0f91497bb3dd2e230337755a27..bd9e2302fb6e5e66c8419305935a22311a929b3a 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -574,15 +574,9 @@ SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
     // Expand to a bitconvert of the value to the integer type of the 
     // same size, then a (misaligned) int store.
     MVT::ValueType intVT;
-    if (VT == MVT::v8i16 || VT == MVT::v4i32 ||
-        VT == MVT::v2i64 || VT == MVT::v2f64 ||
-        VT == MVT::v4f32 || VT == MVT::v16i8 ||
-        VT == MVT::ppcf128)
+    if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128)
       intVT = MVT::i128;
-    else if (VT==MVT::f64 ||
-        VT == MVT::v8i8 || VT == MVT::v4i16 ||
-        VT == MVT::v2i32 || VT == MVT::v1i64 ||
-        VT == MVT::v2f32)
+    else if (MVT::is64BitVector(VT) || VT==MVT::f64)
       intVT = MVT::i64;
     else if (VT==MVT::f32)
       intVT = MVT::i32;
@@ -634,15 +628,10 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
     // Expand to a (misaligned) integer load of the same size,
     // then bitconvert to floating point or vector.
     MVT::ValueType intVT;
-    if (LoadedVT == MVT::v8i16 || LoadedVT == MVT::v4i32 ||
-        LoadedVT == MVT::v2i64 || LoadedVT == MVT::v2f64 ||
-        LoadedVT == MVT::v4f32 || LoadedVT == MVT::v16i8 ||
-        LoadedVT == MVT::ppcf128)
+    if (MVT::is128BitVector(LoadedVT) || 
+         LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
       intVT = MVT::i128;
-    else if (LoadedVT == MVT::f64 || 
-             LoadedVT == MVT::v8i8 || LoadedVT == MVT::v4i16 ||
-             LoadedVT == MVT::v2i32 || LoadedVT == MVT::v1i64 ||
-             LoadedVT == MVT::v2f32)
+    else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64)
       intVT = MVT::i64;
     else if (LoadedVT == MVT::f32)
       intVT = MVT::i32;