+++ /dev/null
-; RUN: llvm-as < %s | llc -march=ppc32 | grep or | count 3
-; This should produce one 'or' or 'cror' instruction per function.
-
-; XFAIL: *
-
-; RUN: llvm-as < %s | llc -march=ppc32 | grep mfcr | count 3
-; PR2964
-
-define i32 @test(double %x, double %y) nounwind {
-entry:
- %tmp3 = fcmp ole double %x, %y ; <i1> [#uses=1]
- %tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
- ret i32 %tmp345
-}
-
-define i32 @test2(double %x, double %y) nounwind {
-entry:
- %tmp3 = fcmp one double %x, %y ; <i1> [#uses=1]
- %tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
- ret i32 %tmp345
-}
-
-define i32 @test3(double %x, double %y) nounwind {
-entry:
- %tmp3 = fcmp ugt double %x, %y ; <i1> [#uses=1]
- %tmp34 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
- ret i32 %tmp34
-}
-
+++ /dev/null
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep fneg
-
-; FSEL is not IEEE-safe, and should not be generated except with
-; -enable-finite-only-fp-math. Further, it can't be generated for
-; GT ever; it tests for GE. Leaving in the test for now as it may
-; be useful as a basis for a correct test.
-;
-; XFAIL: *
-
-define double @test_FNEG_sel(double %A, double %B, double %C) {
- %D = sub double -0.000000e+00, %A ; <double> [#uses=1]
- %Cond = fcmp ugt double %D, -0.000000e+00 ; <i1> [#uses=1]
- %E = select i1 %Cond, double %B, double %C ; <double> [#uses=1]
- ret double %E
-}
-