rk2928: set peri_aclk/peri_phclk/peri_pclk all 24M

diff --git a/arch/arm/mach-rk2928/include/mach/cru.h b/arch/arm/mach-rk2928/include/mach/cru.h
index 90653753460724c68acee9ee6d51563edc0b0a81..8eb853318b6e195d7622749366bbf4eebde159f3 100755 (executable)
--- a/arch/arm/mach-rk2928/include/mach/cru.h
+++ b/arch/arm/mach-rk2928/include/mach/cru.h
@@ -113,6 +113,11 @@ enum rk_plls_id {
 #define A9_CORE_DIV_MASK               (0x1f)
 #define A9_CORE_DIV_SHIFT              (0)
 
+#define RATIO_11               (1)
+#define RATIO_21               (2)
+#define RATIO_41               (4)
+#define RATIO_81               (8)
+
 #define ACLK_CPU_DIV(val)              CLK_SET_DIV_CON_SUB1(val, ACLK_CPU_DIV_SHIFT, ACLK_CPU_DIV_MASK)
 #define CLK_CORE_DIV(val)              CLK_SET_DIV_CON_SUB1(val, A9_CORE_DIV_SHIFT, A9_CORE_DIV_MASK)  
 /*******************CLKSEL1 BITS***************************/
@@ -142,15 +147,8 @@ enum rk_plls_id {
 #define SEL_2PLL_GPLL          (0)
 #define SEL_2PLL_CPLL          (1)
 
-#define RATIO_11               (1)
-#define RATIO_21               (2)
-#define RATIO_41               (4)
-#define RATIO_81               (8)
-
 #define PERI_CLK_SEL_PLL(plls) CRU_W_MSK_SETBIT(plls, PERI_PLL_SEL_SHIFT)
-#define PERI_SET_A2P_RATIO(ratio)      CRU_W_MSK_SETBITS(ratio, PERI_PCLK_DIV_SHIFT, PERI_PCLK_DIV_MASK)
-#define PERI_SET_A2H_RATIO(ratio)      CRU_W_MSK_SETBITS(ratio, PERI_HCLK_DIV_SHIFT, PERI_PCLK_DIV_MASK)
-#define PERI_SET_ACLK_DIV(val)         CRU_W_MSK_SETBITS(val, PERI_ACLK_DIV_SHIFT, PERI_ACLK_DIV_MASK)
+#define PERI_SET_ACLK_DIV(val)         CLK_SET_DIV_CON_SUB1(val, PERI_ACLK_DIV_SHIFT, PERI_ACLK_DIV_MASK)
 /*******************gate BITS***************************/
 #define CLK_GATE_CLKID_CONS(i) CRU_CLKGATES_CON((i) / 16)
 

diff --git a/arch/arm/mach-rk2928/pm.c b/arch/arm/mach-rk2928/pm.c
index 2c95c023ef9bb0ffff2851be3bb61cd6e417eb71..eae40064af5285264727dbcf41c7d314e4af85e1 100644 (file)
--- a/arch/arm/mach-rk2928/pm.c
+++ b/arch/arm/mach-rk2928/pm.c
@@ -453,9 +453,9 @@ static int rk2928_pm_enter(suspend_state_t state)
        
        cru_writel(PLL_MODE_SLOW(GPLL_ID), CRU_MODE_CON);
        cru_writel(PERI_SET_ACLK_DIV(1)
-                  | PERI_SET_A2H_RATIO(RATIO_11)
-                  | PERI_SET_A2P_RATIO(RATIO_11)
-                  , CRU_CLKSELS_CON(10));
+                       | CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_SHIFT, PERI_PCLK_DIV_MASK)
+                       | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_SHIFT, PERI_HCLK_DIV_MASK)
+                       , CRU_CLKSELS_CON(10));
        cru_writel(CRU_W_MSK_SETBIT(0x01, PLL_PWR_DN_SHIFT), PLL_CONS(GPLL_ID, 1));//power down gpll
 
        sram_printch('3');