fixed rt5631 capture not work well at the first time (after device booting)
authorcch <cch@rock-chips.com>
Thu, 19 Jul 2012 09:11:01 +0000 (17:11 +0800)
committercch <cch@rock-chips.com>
Thu, 19 Jul 2012 09:11:01 +0000 (17:11 +0800)
sound/soc/codecs/rt5631.c
sound/soc/rk29/rk29_i2s.c
sound/soc/rk29/rk29_i2s.h
sound/soc/rk29/rk30_i2s.c

index db1b1397c90d5e8d779c2cd7ffeb2048811b43f3..03d944d7ac97ad4a3f659e3bac43526c8d242189 100755 (executable)
@@ -56,6 +56,8 @@ static bool last_is_spk = false;      // need modify.
 #endif
 
 static struct snd_soc_codec *rt5631_codec;
+struct delayed_work rt5631_delay_cap; //bard 7-16
+EXPORT_SYMBOL(rt5631_delay_cap); //bard 7-16
 static const u16 rt5631_reg[0x80];
 static int timesofbclk = 32;
 bool isPlaybackon = false, isCaptureon = false;
@@ -274,7 +276,25 @@ static int rt5631_reg_init(struct snd_soc_codec *codec)
 
        return 0;
 }
+//bard 7-16 s
+void rt5631_adc_on(void)
+{
+       int val;
+
+       val = snd_soc_read(rt5631_codec,RT5631_ADC_REC_MIXER);
+       snd_soc_write(rt5631_codec,RT5631_ADC_REC_MIXER,0xf0f0);
+
+       snd_soc_update_bits(rt5631_codec, RT5631_PWR_MANAG_ADD1,
+               PWR_ADC_L_CLK | PWR_ADC_R_CLK, 0);
+       snd_soc_update_bits(rt5631_codec, RT5631_PWR_MANAG_ADD1,
+               PWR_ADC_L_CLK | PWR_ADC_R_CLK,
+               PWR_ADC_L_CLK | PWR_ADC_R_CLK);
+       snd_soc_write(rt5631_codec,RT5631_ADC_REC_MIXER,val);
+       snd_soc_update_bits(rt5631_codec, RT5631_ADC_CTRL_1,
+                               RT_L_MUTE|RT_R_MUTE,0x0);
 
+}
+//bard 7-16 e
 static const char *rt5631_spol_source_sel[] = {
        "SPOLMIX", "MONOIN_RX", "VDAC", "DACL"};
 static const char *rt5631_spor_source_sel[] = {
@@ -1984,7 +2004,9 @@ static int rt5631_probe(struct snd_soc_codec *codec)
 
        INIT_WORK(&spk_work, spk_work_handler);
 #endif
-
+//bard 7-16 s
+       INIT_DELAYED_WORK(&rt5631_delay_cap,rt5631_adc_on);
+//bard 7-16 e
        snd_soc_add_controls(codec, rt5631_snd_controls,
                ARRAY_SIZE(rt5631_snd_controls));
        rt5631_add_widgets(codec);
index 3c129885ba7312ccf49509cbe74ed5a2ff7f8a7c..923aa15acd3b43610367d7c937561e808fabff24 100755 (executable)
@@ -254,6 +254,11 @@ static void rockchip_snd_rxctrl(struct rk29_i2s_info *i2s, int on, bool stopI2S)
                }
 
          flag_i2s_rx = 1;
+#if (CONFIG_SND_SOC_RT5631)
+//bard 7-16 s
+               schedule_delayed_work(&rt5631_delay_cap,HZ/4);
+//bard 7-16 e
+#endif
        }
        else
        {
index 7787d32f39f286b34b66b7946b33192bcd86c1ec..374c773f65b0f9bed36f5f173aec724966ef5975 100755 (executable)
@@ -244,5 +244,9 @@ extern struct snd_soc_dai_driver rk29_i2s_dai[];
 extern struct snd_soc_dai rk29_i2s_dai[];
 #endif
 
+#if (CONFIG_SND_SOC_RT5631)
+extern struct delayed_work rt5631_delay_cap; //bard 7-16
+#endif
+
 #endif /* _ROCKCHIP_IIS_H */
 
index 19ce1882057152677fc475e70393f0413f50cec2..67ad0342a9b246f9bf38d91813fca0f721974e9e 100755 (executable)
@@ -46,7 +46,7 @@
 
 #define pheadi2s  ((pI2S_REG)(i2s->regs))
 
-#define MAX_I2S         3
+#define MAX_I2S          3
 
 struct rk29_i2s_info {
        struct device   *dev;
@@ -164,6 +164,7 @@ static void rockchip_snd_txctrl(struct rk29_i2s_info *i2s, int on, bool stopI2S)
        } 
 }
 
+
 static void rockchip_snd_rxctrl(struct rk29_i2s_info *i2s, int on, bool stopI2S)
 {
        u32 opr,xfer;
@@ -196,6 +197,11 @@ static void rockchip_snd_rxctrl(struct rk29_i2s_info *i2s, int on, bool stopI2S)
                }
 
          flag_i2s_rx = 1;
+#if (CONFIG_SND_SOC_RT5631)
+//bard 7-16 s
+               schedule_delayed_work(&rt5631_delay_cap,HZ/4);
+//bard 7-16 e
+#endif
        }
        else
        {