rk3188 : disable ddr freq && disable nand suspend && disable power onoff pll for...
author陈亮 <cl@rock-chips.com>
Mon, 17 Mar 2014 08:54:34 +0000 (01:54 -0700)
committer陈亮 <cl@rock-chips.com>
Mon, 17 Mar 2014 08:55:06 +0000 (01:55 -0700)
arch/arm/mach-rockchip/Kconfig
arch/arm/mach-rockchip/pm-rk3188.c
drivers/mtd/rknand/rknand_base_ko.c

index 43389aab03140c476a6d6c687ac8d12319eefc2b..a0c4d82fe7ae9e88abc6a678e3dd634acea2e1bf 100755 (executable)
@@ -50,7 +50,7 @@ config DVFS
 
 config DDR_FREQ
        bool "Enable DDR frequency scaling"
-       default y
+       default n
        select DVFS
 
 config RK_VPU
index 2f69c4404ca994fbbc88fe50bbdc373f1dc29981..1aa770820c2979e6d196d66ef09be1fd928ebb5e 100755 (executable)
@@ -342,7 +342,7 @@ void plls_suspend(void)
     cru_writel(RK3188_PLL_MODE_SLOW(RK3188_CPLL_ID), RK3188_CRU_MODE_CON);
 
     cpll_con3 = cru_readl(RK3188_PLL_CONS(RK3188_CPLL_ID, 3));
-   power_off_pll(RK3188_CPLL_ID);
+   //power_off_pll(RK3188_CPLL_ID);
        
 
        //apll
@@ -364,7 +364,7 @@ void plls_suspend(void)
               | RK3188_ACLK_PCLK_W_MSK | RK3188_ACLK_PCLK_11
               | RK3188_AHB2APB_W_MSK | RK3188_AHB2APB_11
               , RK3188_CRU_CLKSELS_CON(1));
-       power_off_pll(RK3188_APLL_ID);
+       //power_off_pll(RK3188_APLL_ID);
     cru_writel(RK3188_PLL_MODE_SLOW(RK3188_GPLL_ID), RK3188_CRU_MODE_CON);
 
        
@@ -374,7 +374,7 @@ void plls_suspend(void)
     | RK3188_CRU_W_MSK_SETBITS(0, RK3188_PERI_PCLK_DIV_OFF, RK3188_PERI_PCLK_DIV_MASK)
     , RK3188_CRU_CLKSELS_CON(10));
     
-  power_off_pll(RK3188_GPLL_ID);
+  //power_off_pll(RK3188_GPLL_ID);
 
 }
 
@@ -384,7 +384,7 @@ void plls_resume(void)
        
         cru_writel(0xffff0000 | clk_sel10, RK3188_CRU_CLKSELS_CON(10));
     
-       power_on_pll(RK3188_GPLL_ID);
+      // power_on_pll(RK3188_GPLL_ID);
         cru_writel((RK3188_PLL_MODE_MSK(RK3188_GPLL_ID) << 16) 
                         | (RK3188_PLL_MODE_MSK(RK3188_GPLL_ID) & cru_mode_con)
                         ,  RK3188_CRU_MODE_CON);
@@ -401,7 +401,7 @@ void plls_resume(void)
                         | clk_sel0
                         , RK3188_CRU_CLKSELS_CON(0));
         
-        power_on_pll(RK3188_APLL_ID);
+     //   power_on_pll(RK3188_APLL_ID);
         cru_writel((RK3188_PLL_MODE_MSK(RK3188_APLL_ID) << 16)
                         | (RK3188_PLL_MODE_MSK(RK3188_APLL_ID) & cru_mode_con)
                         , RK3188_CRU_MODE_CON);
@@ -411,7 +411,7 @@ void plls_resume(void)
         if (((cpll_con3 & RK3188_PLL_PWR_DN_MSK) == RK3188_PLL_PWR_ON) 
             &&((RK3188_PLL_MODE_NORM(RK3188_CPLL_ID) & RK3188_PLL_MODE_MSK(RK3188_CPLL_ID)) 
             == (cru_mode_con & RK3188_PLL_MODE_MSK(RK3188_CPLL_ID)))) {
-            power_on_pll(RK3188_CPLL_ID);
+       //     power_on_pll(RK3188_CPLL_ID);
         }
         cru_writel((RK3188_PLL_MODE_MSK(RK3188_CPLL_ID) << 16) 
                         | (RK3188_PLL_MODE_MSK(RK3188_CPLL_ID) & cru_mode_con)
index 9b8ebb83cfca92a197f4a1a25a45b8218e358d9a..e0c2e59c4a26c46d7b740b90356f66b3cf294ab3 100755 (executable)
@@ -627,16 +627,16 @@ exit_free:
 static int rknand_suspend(struct platform_device *pdev, pm_message_t state)\r
 {\r
     gpNandInfo->rknand.rknand_schedule_enable = 0;\r
-    if(gpNandInfo->rknand_suspend)\r
-        gpNandInfo->rknand_suspend();  \r
+   // if(gpNandInfo->rknand_suspend)\r
+     //   gpNandInfo->rknand_suspend();  \r
        NAND_DEBUG(NAND_DEBUG_LEVEL0,"rknand_suspend: \n");\r
        return 0;\r
 }\r
 \r
 static int rknand_resume(struct platform_device *pdev)\r
 {\r
-    if(gpNandInfo->rknand_resume)\r
-       gpNandInfo->rknand_resume();  \r
+    //if(gpNandInfo->rknand_resume)\r
+      // gpNandInfo->rknand_resume();  \r
     gpNandInfo->rknand.rknand_schedule_enable = 1;\r
        NAND_DEBUG(NAND_DEBUG_LEVEL0,"rknand_resume: \n");\r
        return 0;\r