cru_writel(RK3188_PLL_MODE_SLOW(RK3188_CPLL_ID), RK3188_CRU_MODE_CON);
cpll_con3 = cru_readl(RK3188_PLL_CONS(RK3188_CPLL_ID, 3));
- power_off_pll(RK3188_CPLL_ID);
+ //power_off_pll(RK3188_CPLL_ID);
//apll
| RK3188_ACLK_PCLK_W_MSK | RK3188_ACLK_PCLK_11
| RK3188_AHB2APB_W_MSK | RK3188_AHB2APB_11
, RK3188_CRU_CLKSELS_CON(1));
- power_off_pll(RK3188_APLL_ID);
+ //power_off_pll(RK3188_APLL_ID);
cru_writel(RK3188_PLL_MODE_SLOW(RK3188_GPLL_ID), RK3188_CRU_MODE_CON);
| RK3188_CRU_W_MSK_SETBITS(0, RK3188_PERI_PCLK_DIV_OFF, RK3188_PERI_PCLK_DIV_MASK)
, RK3188_CRU_CLKSELS_CON(10));
- power_off_pll(RK3188_GPLL_ID);
+ //power_off_pll(RK3188_GPLL_ID);
}
cru_writel(0xffff0000 | clk_sel10, RK3188_CRU_CLKSELS_CON(10));
- power_on_pll(RK3188_GPLL_ID);
+ // power_on_pll(RK3188_GPLL_ID);
cru_writel((RK3188_PLL_MODE_MSK(RK3188_GPLL_ID) << 16)
| (RK3188_PLL_MODE_MSK(RK3188_GPLL_ID) & cru_mode_con)
, RK3188_CRU_MODE_CON);
| clk_sel0
, RK3188_CRU_CLKSELS_CON(0));
- power_on_pll(RK3188_APLL_ID);
+ // power_on_pll(RK3188_APLL_ID);
cru_writel((RK3188_PLL_MODE_MSK(RK3188_APLL_ID) << 16)
| (RK3188_PLL_MODE_MSK(RK3188_APLL_ID) & cru_mode_con)
, RK3188_CRU_MODE_CON);
if (((cpll_con3 & RK3188_PLL_PWR_DN_MSK) == RK3188_PLL_PWR_ON)
&&((RK3188_PLL_MODE_NORM(RK3188_CPLL_ID) & RK3188_PLL_MODE_MSK(RK3188_CPLL_ID))
== (cru_mode_con & RK3188_PLL_MODE_MSK(RK3188_CPLL_ID)))) {
- power_on_pll(RK3188_CPLL_ID);
+ // power_on_pll(RK3188_CPLL_ID);
}
cru_writel((RK3188_PLL_MODE_MSK(RK3188_CPLL_ID) << 16)
| (RK3188_PLL_MODE_MSK(RK3188_CPLL_ID) & cru_mode_con)
static int rknand_suspend(struct platform_device *pdev, pm_message_t state)\r
{\r
gpNandInfo->rknand.rknand_schedule_enable = 0;\r
- if(gpNandInfo->rknand_suspend)\r
- gpNandInfo->rknand_suspend(); \r
+ // if(gpNandInfo->rknand_suspend)\r
+ // gpNandInfo->rknand_suspend(); \r
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rknand_suspend: \n");\r
return 0;\r
}\r
\r
static int rknand_resume(struct platform_device *pdev)\r
{\r
- if(gpNandInfo->rknand_resume)\r
- gpNandInfo->rknand_resume(); \r
+ //if(gpNandInfo->rknand_resume)\r
+ // gpNandInfo->rknand_resume(); \r
gpNandInfo->rknand.rknand_schedule_enable = 1;\r
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rknand_resume: \n");\r
return 0;\r