namespace {
class WebAssemblyAsmPrinter final : public AsmPrinter {
+ const WebAssemblyInstrInfo *TII;
+
public:
WebAssemblyAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
- : AsmPrinter(TM, std::move(Streamer)) {}
+ : AsmPrinter(TM, std::move(Streamer)), TII(nullptr) {}
private:
const char *getPassName() const override {
AsmPrinter::getAnalysisUsage(AU);
}
- bool runOnMachineFunction(MachineFunction &F) override {
- return AsmPrinter::runOnMachineFunction(F);
+ bool runOnMachineFunction(MachineFunction &MF) override {
+ TII = static_cast<const WebAssemblyInstrInfo *>(
+ MF.getSubtarget().getInstrInfo());
+ return AsmPrinter::runOnMachineFunction(MF);
}
//===------------------------------------------------------------------===//
SmallString<128> Str;
raw_svector_ostream OS(Str);
+ unsigned NumDefs = MI->getDesc().getNumDefs();
+ assert(NumDefs <= 1 &&
+ "Instructions with multiple result values not implemented");
+
+ if (NumDefs != 0) {
+ const MachineOperand &MO = MI->getOperand(0);
+ unsigned Reg = MO.getReg();
+ OS << "(setlocal @" << TargetRegisterInfo::virtReg2Index(Reg) << ' ';
+ }
+
+ OS << '(';
+
+ bool PrintOperands = true;
switch (MI->getOpcode()) {
+ case WebAssembly::ARGUMENT:
+ OS << "argument " << MI->getOperand(1).getImm();
+ PrintOperands = false;
+ break;
default:
- DEBUG(MI->print(dbgs()));
- llvm_unreachable("Unhandled instruction");
+ OS << TII->getName(MI->getOpcode());
break;
}
+ if (PrintOperands)
+ for (const MachineOperand &MO : MI->uses()) {
+ if (MO.isReg() && MO.isImplicit())
+ continue;
+ unsigned Reg = MO.getReg();
+ OS << " @" << TargetRegisterInfo::virtReg2Index(Reg);
+ }
+ OS << ')';
+
+ if (NumDefs != 0)
+ OS << ')';
+
+ OS << '\n';
+
OutStreamer->EmitRawText(OS.str());
}
assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
if (CallConv != CallingConv::C)
fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
+ if (IsVarArg)
+ fail(DL, DAG, "WebAssembly doesn't support varargs yet");
- // FIXME: Implement LowerReturn.
+ SmallVector<SDValue, 4> RetOps(1, Chain);
+ RetOps.append(OutVals.begin(), OutVals.end());
+ const SDValue Ops[] = {Chain, OutVals.front()};
+ Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, Ops);
return Chain;
}
if (MF.getFunction()->hasStructRetAttr())
fail(DL, DAG, "WebAssembly doesn't support struct return yet");
- // FIXME: Implement LowerFormalArguments.
- for (const ISD::InputArg &In : Ins)
- InVals.push_back(DAG.getNode(ISD::UNDEF, DL, In.VT));
+ unsigned ArgNo = 0;
+ for (const ISD::InputArg &In : Ins) {
+ if (In.Flags.isZExt())
+ fail(DL, DAG, "WebAssembly hasn't implemented zext arguments");
+ if (In.Flags.isSExt())
+ fail(DL, DAG, "WebAssembly hasn't implemented sext arguments");
+ if (In.Flags.isInReg())
+ fail(DL, DAG, "WebAssembly hasn't implemented inreg arguments");
+ if (In.Flags.isSRet())
+ fail(DL, DAG, "WebAssembly hasn't implemented sret arguments");
+ if (In.Flags.isByVal())
+ fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
+ if (In.Flags.isInAlloca())
+ fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
+ if (In.Flags.isNest())
+ fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
+ if (In.Flags.isReturned())
+ fail(DL, DAG, "WebAssembly hasn't implemented returned arguments");
+ if (In.Flags.isInConsecutiveRegs())
+ fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
+ if (In.Flags.isInConsecutiveRegsLast())
+ fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
+ if (In.Flags.isSplit())
+ fail(DL, DAG, "WebAssembly hasn't implemented split arguments");
+ if (In.VT != MVT::i32)
+ fail(DL, DAG, "WebAssembly hasn't implemented non-i32 arguments");
+ if (!In.Used)
+ fail(DL, DAG, "WebAssembly hasn't implemented unused arguments");
+ // FIXME Do something with In.getOrigAlign()?
+ InVals.push_back(DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
+ DAG.getTargetConstant(ArgNo++, DL, MVT::i32)));
+ }
return Chain;
}
enum {
FIRST_NUMBER = ISD::BUILTIN_OP_END,
+ RETURN,
+ ARGUMENT,
// add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...
};
--- /dev/null
+//===- WebAssemblyInstrControl.td-WebAssembly control-flow ------*- tablegen -*-
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// \brief WebAssembly control-flow code-gen constructs.
+///
+//===----------------------------------------------------------------------===//
+
+/*
+ * TODO(jfb): Add the following.
+ *
+ * block: a fixed-length sequence of statements
+ * if: if statement
+ * do_while: do while statement, basically a loop with a conditional branch
+ * forever: infinite loop statement (like while (1)), basically an unconditional
+ * branch (back to the top of the loop)
+ * continue: continue to start of nested loop
+ * break: break to end from nested loop or block
+ * switch: switch statement with fallthrough
+ */
+
+let hasSideEffects = 1, isReturn = 1, isTerminator = 1, hasCtrlDep = 1,
+ isBarrier = 1 in {
+//FIXME return more than just int32.
+def RETURN : I<(outs), (ins Int32:$val), [(WebAssemblyreturn Int32:$val)]>;
+} // hasSideEffects = 1, isReturn = 1, isTerminator = 1, hasCtrlDep = 1,
+ // isBarrier = 1
// WebAssembly-specific DAG Node Types.
//===----------------------------------------------------------------------===//
+def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>;
+def SDT_WebAssemblyReturn : SDTypeProfile<0, 1, []>;
+
//===----------------------------------------------------------------------===//
// WebAssembly-specific DAG Nodes.
//===----------------------------------------------------------------------===//
+def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT",
+ SDT_WebAssemblyArgument>;
+def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN",
+ SDT_WebAssemblyReturn,
+ [SDNPHasChain, SDNPSideEffect]>;
+
//===----------------------------------------------------------------------===//
// WebAssembly-specific Operands.
//===----------------------------------------------------------------------===//
include "WebAssemblyInstrFormats.td"
+def ARGUMENT : I<(outs Int32:$res), (ins i32imm:$argno),
+ [(set Int32:$res, (WebAssemblyargument timm:$argno))]>;
+
//===----------------------------------------------------------------------===//
// Additional sets of instructions.
//===----------------------------------------------------------------------===//
include "WebAssemblyInstrMemory.td"
include "WebAssemblyInstrCall.td"
+include "WebAssemblyInstrControl.td"
include "WebAssemblyInstrInteger.td"
include "WebAssemblyInstrFloat.td"
include "WebAssemblyInstrConv.td"
void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {}
-void WebAssemblyPassConfig::addPostRegAlloc() {}
+void WebAssemblyPassConfig::addPostRegAlloc() {
+ // FIXME: the following passes dislike virtual registers. Disable them for now
+ // so that basic tests can pass. Future patches will remedy this.
+ //
+ // Fails with: Regalloc must assign all vregs.
+ disablePass(&PrologEpilogCodeInserterID);
+ // Fails with: should be run after register allocation.
+ disablePass(&MachineCopyPropagationID);
+}
void WebAssemblyPassConfig::addPreSched2() {}
; CHECK-NOT: {{.*}} is not a recognized processor for this target
; INVALID: {{.*}} is not a recognized processor for this target
-define void @f(i64 %i_like_the_web) {
- ret void
+define i32 @f(i32 %i_like_the_web) {
+ ret i32 %i_like_the_web
}
target datalayout = "e-p:32:32-i64:64-v128:8:128-n32:64-S128"
target triple = "wasm32-unknown-unknown"
+declare i32 @llvm.ctlz.i32(i32, i1)
+declare i32 @llvm.cttz.i32(i32, i1)
+declare i32 @llvm.ctpop.i32(i32)
+
; CHECK-LABEL: add32:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (ADD_I32 @1 @0))
+; CHECK-NEXT: (RETURN @2)
define i32 @add32(i32 %x, i32 %y) {
%a = add i32 %x, %y
ret i32 %a
}
+
+; CHECK-LABEL: sub32:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (SUB_I32 @1 @0))
+; CHECK-NEXT: (RETURN @2)
+define i32 @sub32(i32 %x, i32 %y) {
+ %a = sub i32 %x, %y
+ ret i32 %a
+}
+
+; CHECK-LABEL: mul32:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (MUL_I32 @1 @0))
+; CHECK-NEXT: (RETURN @2)
+define i32 @mul32(i32 %x, i32 %y) {
+ %a = mul i32 %x, %y
+ ret i32 %a
+}
+
+; CHECK-LABEL: sdiv32:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (SDIV_I32 @1 @0))
+; CHECK-NEXT: (RETURN @2)
+define i32 @sdiv32(i32 %x, i32 %y) {
+ %a = sdiv i32 %x, %y
+ ret i32 %a
+}
+
+; CHECK-LABEL: udiv32:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (UDIV_I32 @1 @0))
+; CHECK-NEXT: (RETURN @2)
+define i32 @udiv32(i32 %x, i32 %y) {
+ %a = udiv i32 %x, %y
+ ret i32 %a
+}
+
+; CHECK-LABEL: srem32:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (SREM_I32 @1 @0))
+; CHECK-NEXT: (RETURN @2)
+define i32 @srem32(i32 %x, i32 %y) {
+ %a = srem i32 %x, %y
+ ret i32 %a
+}
+
+; CHECK-LABEL: urem32:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (UREM_I32 @1 @0))
+; CHECK-NEXT: (RETURN @2)
+define i32 @urem32(i32 %x, i32 %y) {
+ %a = urem i32 %x, %y
+ ret i32 %a
+}
+
+; CHECK-LABEL: and32:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (AND_I32 @1 @0))
+; CHECK-NEXT: (RETURN @2)
+define i32 @and32(i32 %x, i32 %y) {
+ %a = and i32 %x, %y
+ ret i32 %a
+}
+
+; CHECK-LABEL: ior32:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (IOR_I32 @1 @0))
+; CHECK-NEXT: (RETURN @2)
+define i32 @ior32(i32 %x, i32 %y) {
+ %a = or i32 %x, %y
+ ret i32 %a
+}
+
+; CHECK-LABEL: xor32:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (XOR_I32 @1 @0))
+; CHECK-NEXT: (RETURN @2)
+define i32 @xor32(i32 %x, i32 %y) {
+ %a = xor i32 %x, %y
+ ret i32 %a
+}
+
+; CHECK-LABEL: shl32:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (SHL_I32 @1 @0))
+; CHECK-NEXT: (RETURN @2)
+define i32 @shl32(i32 %x, i32 %y) {
+ %a = shl i32 %x, %y
+ ret i32 %a
+}
+
+; CHECK-LABEL: shr32:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (SHR_I32 @1 @0))
+; CHECK-NEXT: (RETURN @2)
+define i32 @shr32(i32 %x, i32 %y) {
+ %a = lshr i32 %x, %y
+ ret i32 %a
+}
+
+; CHECK-LABEL: sar32:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (SAR_I32 @1 @0))
+; CHECK-NEXT: (RETURN @2)
+define i32 @sar32(i32 %x, i32 %y) {
+ %a = ashr i32 %x, %y
+ ret i32 %a
+}
+
+; CHECK-LABEL: clz32:
+; CHECK-NEXT: (setlocal @0 (argument 0))
+; CHECK-NEXT: (setlocal @1 (CLZ_I32 @0))
+; CHECK-NEXT: (RETURN @1)
+define i32 @clz32(i32 %x) {
+ %a = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
+ ret i32 %a
+}
+
+; CHECK-LABEL: ctz32:
+; CHECK-NEXT: (setlocal @0 (argument 0))
+; CHECK-NEXT: (setlocal @1 (CTZ_I32 @0))
+; CHECK-NEXT: (RETURN @1)
+define i32 @ctz32(i32 %x) {
+ %a = call i32 @llvm.cttz.i32(i32 %x, i1 false)
+ ret i32 %a
+}
+
+; CHECK-LABEL: popcnt32:
+; CHECK-NEXT: (setlocal @0 (argument 0))
+; CHECK-NEXT: (setlocal @1 (POPCNT_I32 @0))
+; CHECK-NEXT: (RETURN @1)
+define i32 @popcnt32(i32 %x) {
+ %a = call i32 @llvm.ctpop.i32(i32 %x)
+ ret i32 %a
+}
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