-#include <linux/fb.h>\r
-#include <linux/delay.h>\r
-#include "../../rk29_fb.h"\r
-#include <mach/gpio.h>\r
-#include <mach/iomux.h>\r
-#include <mach/board.h>\r
-#include "../../rockchip/hdmi/rk_hdmi.h"\r
-#include "screen.h"\r
-\r
-\r
-/* Base */\r
-#define OUT_TYPE SCREEN_LVDS\r
-\r
-#define OUT_FACE OUT_D888_P666 \r
-#define OUT_CLK 65000000\r
-#define LCDC_ACLK 300000000//312000000 //29 lcdc axi DMA ƵÂÊ\r
-\r
-/* Timing */\r
-#define H_PW 10\r
-#define H_BP 100\r
-#define H_VD 1024\r
-#define H_FP 210\r
-\r
-#define V_PW 10\r
-#define V_BP 10\r
-#define V_VD 768\r
-#define V_FP 18\r
-\r
-#define LCD_WIDTH 202\r
-#define LCD_HEIGHT 152\r
-/* Other */\r
-#define DCLK_POL 1\r
-#define SWAP_RB 0 \r
-\r
-\r
-#ifdef CONFIG_ONE_LCDC_DUAL_OUTPUT_INF\r
-/* scaler Timing */\r
-//1920*1080*60\r
-\r
-#define S_OUT_CLK 64512000\r
-#define S_H_PW 114\r
-#define S_H_BP 210\r
-#define S_H_VD 1024\r
-#define S_H_FP 0\r
-\r
-#define S_V_PW 4\r
-#define S_V_BP 10\r
-#define S_V_VD 768\r
-#define S_V_FP 0\r
-\r
-#define S_H_ST 0\r
-#define S_V_ST 23\r
-\r
-//1920*1080*50\r
-#define S1_OUT_CLK 53760000\r
-#define S1_H_PW 114\r
-#define S1_H_BP 210\r
-#define S1_H_VD 1024\r
-#define S1_H_FP 0\r
-\r
-#define S1_V_PW 4\r
-#define S1_V_BP 10\r
-#define S1_V_VD 768\r
-#define S1_V_FP 0\r
-\r
-#define S1_H_ST 0\r
-#define S1_V_ST 23\r
-//1280*720*60\r
-#define S2_OUT_CLK 64512000\r
-#define S2_H_PW 114\r
-#define S2_H_BP 210\r
-#define S2_H_VD 1024\r
-#define S2_H_FP 0\r
-\r
-#define S2_V_PW 4\r
-#define S2_V_BP 10\r
-#define S2_V_VD 768\r
-#define S2_V_FP 0\r
-\r
-#define S2_H_ST 0\r
-#define S2_V_ST 23\r
-//1280*720*50\r
-\r
-#define S3_OUT_CLK 53760000\r
-#define S3_H_PW 114\r
-#define S3_H_BP 210\r
-#define S3_H_VD 1024\r
-#define S3_H_FP 0\r
-\r
-#define S3_V_PW 4\r
-#define S3_V_BP 10\r
-#define S3_V_VD 768\r
-#define S3_V_FP 0\r
-\r
-#define S3_H_ST 0\r
-#define S3_V_ST 23\r
-\r
-//720*576*50\r
-#define S4_OUT_CLK 30000000\r
-#define S4_H_PW 1\r
-#define S4_H_BP 88\r
-#define S4_H_VD 800\r
-#define S4_H_FP 263\r
-\r
-#define S4_V_PW 3\r
-#define S4_V_BP 9\r
-#define S4_V_VD 480\r
-#define S4_V_FP 28\r
-\r
-#define S4_H_ST 0\r
-#define S4_V_ST 33\r
-//720*480*60\r
-#define S5_OUT_CLK 30000000\r
-#define S5_H_PW 1\r
-#define S5_H_BP 88\r
-#define S5_H_VD 800\r
-#define S5_H_FP 112\r
-\r
-#define S5_V_PW 3\r
-#define S5_V_BP 9\r
-#define S5_V_VD 480\r
-#define S5_V_FP 28\r
-\r
-#define S5_H_ST 0\r
-#define S5_V_ST 29\r
-\r
-#define S_DCLK_POL 1\r
-\r
-\r
-static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)\r
-{\r
- screen->s_clk_inv = S_DCLK_POL;\r
- screen->s_den_inv = 0;\r
- screen->s_hv_sync_inv = 0;\r
- \r
- printk("%s>>>>>>>>mode:%d\n",__func__,hdmi_resolution);\r
- switch(hdmi_resolution){\r
- case HDMI_1920x1080p_60Hz:\r
- /* Scaler Timing */\r
- screen->hdmi_resolution = hdmi_resolution;\r
- screen->s_pixclock = S_OUT_CLK;\r
- screen->s_hsync_len = S_H_PW;\r
- screen->s_left_margin = S_H_BP;\r
- screen->s_right_margin = S_H_FP;\r
- screen->s_hsync_len = S_H_PW;\r
- screen->s_upper_margin = S_V_BP;\r
- screen->s_lower_margin = S_V_FP;\r
- screen->s_vsync_len = S_V_PW;\r
- screen->s_hsync_st = S_H_ST;\r
- screen->s_vsync_st = S_V_ST;\r
- break;\r
- case HDMI_1920x1080p_50Hz:\r
- /* Scaler Timing */\r
- screen->s_pixclock = S1_OUT_CLK;\r
- screen->s_hsync_len = S1_H_PW;\r
- screen->s_left_margin = S1_H_BP;\r
- screen->s_right_margin = S1_H_FP;\r
- screen->s_hsync_len = S1_H_PW;\r
- screen->s_upper_margin = S1_V_BP;\r
- screen->s_lower_margin = S1_V_FP;\r
- screen->s_vsync_len = S1_V_PW;\r
- screen->s_hsync_st = S1_H_ST;\r
- screen->s_vsync_st = S1_V_ST;\r
- break;\r
- case HDMI_1280x720p_60Hz:\r
- /* Scaler Timing */\r
- screen->hdmi_resolution = hdmi_resolution;\r
- screen->s_pixclock = S2_OUT_CLK;\r
- screen->s_hsync_len = S2_H_PW;\r
- screen->s_left_margin = S2_H_BP;\r
- screen->s_right_margin = S2_H_FP;\r
- screen->s_hsync_len = S2_H_PW;\r
- screen->s_upper_margin = S2_V_BP;\r
- screen->s_lower_margin = S2_V_FP;\r
- screen->s_vsync_len = S2_V_PW;\r
- screen->s_hsync_st = S2_H_ST;\r
- screen->s_vsync_st = S2_V_ST;\r
- break;\r
- case HDMI_1280x720p_50Hz:\r
- /* Scaler Timing */\r
- screen->hdmi_resolution = hdmi_resolution;\r
- screen->s_pixclock = S3_OUT_CLK;\r
- screen->s_hsync_len = S3_H_PW;\r
- screen->s_left_margin = S3_H_BP;\r
- screen->s_right_margin = S3_H_FP;\r
- screen->s_hsync_len = S3_H_PW;\r
- screen->s_upper_margin = S3_V_BP;\r
- screen->s_lower_margin = S3_V_FP;\r
- screen->s_vsync_len = S3_V_PW;\r
- screen->s_hsync_st = S3_H_ST;\r
- screen->s_vsync_st = S3_V_ST;\r
- break;\r
- case HDMI_720x576p_50Hz_4_3:\r
- case HDMI_720x576p_50Hz_16_9:\r
- /* Scaler Timing */\r
- screen->hdmi_resolution = hdmi_resolution;\r
- screen->s_pixclock = S4_OUT_CLK;\r
- screen->s_hsync_len = S4_H_PW;\r
- screen->s_left_margin = S4_H_BP;\r
- screen->s_right_margin = S4_H_FP;\r
- screen->s_hsync_len = S4_H_PW;\r
- screen->s_upper_margin = S4_V_BP;\r
- screen->s_lower_margin = S4_V_FP;\r
- screen->s_vsync_len = S4_V_PW;\r
- screen->s_hsync_st = S4_H_ST;\r
- screen->s_vsync_st = S4_V_ST;\r
- break;\r
- case HDMI_720x480p_60Hz_16_9:\r
- case HDMI_720x480p_60Hz_4_3:\r
- /* Scaler Timing */\r
- screen->hdmi_resolution = hdmi_resolution;\r
- screen->s_pixclock = S5_OUT_CLK;\r
- screen->s_hsync_len = S5_H_PW;\r
- screen->s_left_margin = S5_H_BP;\r
- screen->s_right_margin = S5_H_FP;\r
- screen->s_hsync_len = S5_H_PW;\r
- screen->s_upper_margin = S5_V_BP;\r
- screen->s_lower_margin = S5_V_FP;\r
- screen->s_vsync_len = S5_V_PW;\r
- screen->s_hsync_st = S5_H_ST;\r
- screen->s_vsync_st = S5_V_ST;\r
- break;\r
- default :\r
- printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);\r
- return -1;\r
- break;\r
- }\r
- \r
- return 0;\r
-}\r
-#else\r
-#define set_scaler_info NULL\r
-#endif\r
-\r
-\r
-\r
-void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )\r
-{\r
- /* screen type & face */\r
- screen->type = OUT_TYPE;\r
- screen->face = OUT_FACE;\r
- screen->hw_format = 1;\r
-\r
- /* Screen size */\r
- screen->x_res = H_VD;\r
- screen->y_res = V_VD;\r
-\r
- screen->width = LCD_WIDTH;\r
- screen->height = LCD_HEIGHT;\r
-\r
- /* Timing */\r
- screen->lcdc_aclk = LCDC_ACLK;\r
- screen->pixclock = OUT_CLK;\r
- screen->left_margin = H_BP;\r
- screen->right_margin = H_FP;\r
- screen->hsync_len = H_PW;\r
- screen->upper_margin = V_BP;\r
- screen->lower_margin = V_FP;\r
- screen->vsync_len = V_PW;\r
-\r
- /* Pin polarity */\r
- screen->pin_hsync = 0;\r
- screen->pin_vsync = 0;\r
- screen->pin_den = 0;\r
- screen->pin_dclk = DCLK_POL;\r
-\r
- /* Swap rule */\r
- screen->swap_rb = SWAP_RB;\r
- screen->swap_rg = 0;\r
- screen->swap_gb = 0;\r
- screen->swap_delta = 0;\r
- screen->swap_dumy = 0;\r
-\r
- /* Operation function*/\r
- screen->init = NULL;\r
- screen->standby = NULL;\r
-\r
-#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)\r
- screen->sscreen_get = set_scaler_info;\r
- screen->s_pixclock = OUT_CLK;\r
- screen->s_hsync_len = H_PW;\r
- screen->s_left_margin = H_BP;\r
- screen->s_right_margin = H_FP;\r
- screen->s_hsync_len = H_PW;\r
- screen->s_upper_margin = V_BP;\r
- screen->s_lower_margin = V_FP;\r
- screen->s_vsync_len = V_PW;\r
- screen->s_hsync_st = 0;\r
- screen->s_vsync_st = 0;\r
-#endif\r
-}\r
-\r
-\r
-\r
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include "../../rk29_fb.h"
+#include <mach/gpio.h>
+#include <mach/iomux.h>
+#include <mach/board.h>
+#include "../../rockchip/hdmi/rk_hdmi.h"
+#include "screen.h"
+
+
+/* Base */
+#define OUT_TYPE SCREEN_LVDS
+
+#define OUT_FACE OUT_D888_P666
+#define OUT_CLK 65000000
+#define LCDC_ACLK 300000000//312000000 //29 lcdc axi DMA ƵÂÊ
+
+/* Timing */
+#define H_PW 10
+#define H_BP 100
+#define H_VD 1024
+#define H_FP 210
+
+#define V_PW 10
+#define V_BP 10
+#define V_VD 768
+#define V_FP 18
+
+#define LCD_WIDTH 202
+#define LCD_HEIGHT 152
+/* Other */
+#define DCLK_POL 1
+#define SWAP_RB 0
+
+
+#ifdef CONFIG_ONE_LCDC_DUAL_OUTPUT_INF
+/* scaler Timing */
+//1920*1080*60
+
+#define S_OUT_CLK 64512000
+#define S_H_PW 114
+#define S_H_BP 210
+#define S_H_VD 1024
+#define S_H_FP 0
+
+#define S_V_PW 4
+#define S_V_BP 10
+#define S_V_VD 768
+#define S_V_FP 0
+
+#define S_H_ST 0
+#define S_V_ST 23
+
+//1920*1080*50
+#define S1_OUT_CLK 53760000
+#define S1_H_PW 114
+#define S1_H_BP 210
+#define S1_H_VD 1024
+#define S1_H_FP 0
+
+#define S1_V_PW 4
+#define S1_V_BP 10
+#define S1_V_VD 768
+#define S1_V_FP 0
+
+#define S1_H_ST 0
+#define S1_V_ST 23
+//1280*720*60
+#define S2_OUT_CLK 64512000
+#define S2_H_PW 114
+#define S2_H_BP 210
+#define S2_H_VD 1024
+#define S2_H_FP 0
+
+#define S2_V_PW 4
+#define S2_V_BP 10
+#define S2_V_VD 768
+#define S2_V_FP 0
+
+#define S2_H_ST 0
+#define S2_V_ST 23
+//1280*720*50
+
+#define S3_OUT_CLK 53760000
+#define S3_H_PW 114
+#define S3_H_BP 210
+#define S3_H_VD 1024
+#define S3_H_FP 0
+
+#define S3_V_PW 4
+#define S3_V_BP 10
+#define S3_V_VD 768
+#define S3_V_FP 0
+
+#define S3_H_ST 0
+#define S3_V_ST 23
+
+//720*576*50
+#define S4_OUT_CLK 30000000
+#define S4_H_PW 1
+#define S4_H_BP 88
+#define S4_H_VD 800
+#define S4_H_FP 263
+
+#define S4_V_PW 3
+#define S4_V_BP 9
+#define S4_V_VD 480
+#define S4_V_FP 28
+
+#define S4_H_ST 0
+#define S4_V_ST 33
+//720*480*60
+#define S5_OUT_CLK 30000000
+#define S5_H_PW 1
+#define S5_H_BP 88
+#define S5_H_VD 800
+#define S5_H_FP 112
+
+#define S5_V_PW 3
+#define S5_V_BP 9
+#define S5_V_VD 480
+#define S5_V_FP 28
+
+#define S5_H_ST 0
+#define S5_V_ST 29
+
+#define S_DCLK_POL 1
+
+
+static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
+{
+ screen->s_clk_inv = S_DCLK_POL;
+ screen->s_den_inv = 0;
+ screen->s_hv_sync_inv = 0;
+
+ printk("%s>>>>>>>>mode:%d\n",__func__,hdmi_resolution);
+ switch(hdmi_resolution){
+ case HDMI_1920x1080p_60Hz:
+ /* Scaler Timing */
+ screen->hdmi_resolution = hdmi_resolution;
+ screen->s_pixclock = S_OUT_CLK;
+ screen->s_hsync_len = S_H_PW;
+ screen->s_left_margin = S_H_BP;
+ screen->s_right_margin = S_H_FP;
+ screen->s_hsync_len = S_H_PW;
+ screen->s_upper_margin = S_V_BP;
+ screen->s_lower_margin = S_V_FP;
+ screen->s_vsync_len = S_V_PW;
+ screen->s_hsync_st = S_H_ST;
+ screen->s_vsync_st = S_V_ST;
+ break;
+ case HDMI_1920x1080p_50Hz:
+ /* Scaler Timing */
+ screen->s_pixclock = S1_OUT_CLK;
+ screen->s_hsync_len = S1_H_PW;
+ screen->s_left_margin = S1_H_BP;
+ screen->s_right_margin = S1_H_FP;
+ screen->s_hsync_len = S1_H_PW;
+ screen->s_upper_margin = S1_V_BP;
+ screen->s_lower_margin = S1_V_FP;
+ screen->s_vsync_len = S1_V_PW;
+ screen->s_hsync_st = S1_H_ST;
+ screen->s_vsync_st = S1_V_ST;
+ break;
+ case HDMI_1280x720p_60Hz:
+ /* Scaler Timing */
+ screen->hdmi_resolution = hdmi_resolution;
+ screen->s_pixclock = S2_OUT_CLK;
+ screen->s_hsync_len = S2_H_PW;
+ screen->s_left_margin = S2_H_BP;
+ screen->s_right_margin = S2_H_FP;
+ screen->s_hsync_len = S2_H_PW;
+ screen->s_upper_margin = S2_V_BP;
+ screen->s_lower_margin = S2_V_FP;
+ screen->s_vsync_len = S2_V_PW;
+ screen->s_hsync_st = S2_H_ST;
+ screen->s_vsync_st = S2_V_ST;
+ break;
+ case HDMI_1280x720p_50Hz:
+ /* Scaler Timing */
+ screen->hdmi_resolution = hdmi_resolution;
+ screen->s_pixclock = S3_OUT_CLK;
+ screen->s_hsync_len = S3_H_PW;
+ screen->s_left_margin = S3_H_BP;
+ screen->s_right_margin = S3_H_FP;
+ screen->s_hsync_len = S3_H_PW;
+ screen->s_upper_margin = S3_V_BP;
+ screen->s_lower_margin = S3_V_FP;
+ screen->s_vsync_len = S3_V_PW;
+ screen->s_hsync_st = S3_H_ST;
+ screen->s_vsync_st = S3_V_ST;
+ break;
+ case HDMI_720x576p_50Hz_4_3:
+ case HDMI_720x576p_50Hz_16_9:
+ /* Scaler Timing */
+ screen->hdmi_resolution = hdmi_resolution;
+ screen->s_pixclock = S4_OUT_CLK;
+ screen->s_hsync_len = S4_H_PW;
+ screen->s_left_margin = S4_H_BP;
+ screen->s_right_margin = S4_H_FP;
+ screen->s_hsync_len = S4_H_PW;
+ screen->s_upper_margin = S4_V_BP;
+ screen->s_lower_margin = S4_V_FP;
+ screen->s_vsync_len = S4_V_PW;
+ screen->s_hsync_st = S4_H_ST;
+ screen->s_vsync_st = S4_V_ST;
+ break;
+ case HDMI_720x480p_60Hz_16_9:
+ case HDMI_720x480p_60Hz_4_3:
+ /* Scaler Timing */
+ screen->hdmi_resolution = hdmi_resolution;
+ screen->s_pixclock = S5_OUT_CLK;
+ screen->s_hsync_len = S5_H_PW;
+ screen->s_left_margin = S5_H_BP;
+ screen->s_right_margin = S5_H_FP;
+ screen->s_hsync_len = S5_H_PW;
+ screen->s_upper_margin = S5_V_BP;
+ screen->s_lower_margin = S5_V_FP;
+ screen->s_vsync_len = S5_V_PW;
+ screen->s_hsync_st = S5_H_ST;
+ screen->s_vsync_st = S5_V_ST;
+ break;
+ default :
+ printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
+ return -1;
+ break;
+ }
+
+ return 0;
+}
+#else
+#define set_scaler_info NULL
+#endif
+
+
+
+void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
+{
+ /* screen type & face */
+ screen->type = OUT_TYPE;
+ screen->face = OUT_FACE;
+ screen->hw_format = 1;
+
+ /* Screen size */
+ screen->x_res = H_VD;
+ screen->y_res = V_VD;
+
+ screen->width = LCD_WIDTH;
+ screen->height = LCD_HEIGHT;
+
+ /* Timing */
+ screen->lcdc_aclk = LCDC_ACLK;
+ screen->pixclock = OUT_CLK;
+ screen->left_margin = H_BP;
+ screen->right_margin = H_FP;
+ screen->hsync_len = H_PW;
+ screen->upper_margin = V_BP;
+ screen->lower_margin = V_FP;
+ screen->vsync_len = V_PW;
+
+ /* Pin polarity */
+ screen->pin_hsync = 0;
+ screen->pin_vsync = 0;
+ screen->pin_den = 0;
+ screen->pin_dclk = DCLK_POL;
+
+ /* Swap rule */
+ screen->swap_rb = SWAP_RB;
+ screen->swap_rg = 0;
+ screen->swap_gb = 0;
+ screen->swap_delta = 0;
+ screen->swap_dumy = 0;
+
+ /* Operation function*/
+ screen->init = NULL;
+ screen->standby = NULL;
+
+#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)
+ screen->sscreen_get = set_scaler_info;
+ screen->s_pixclock = OUT_CLK;
+ screen->s_hsync_len = H_PW;
+ screen->s_left_margin = H_BP;
+ screen->s_right_margin = H_FP;
+ screen->s_hsync_len = H_PW;
+ screen->s_upper_margin = V_BP;
+ screen->s_lower_margin = V_FP;
+ screen->s_vsync_len = V_PW;
+ screen->s_hsync_st = 0;
+ screen->s_vsync_st = 0;
+#endif
+}
+
+
+size_t get_fb_size(void)
+{
+ size_t size = 0;
+ #if defined(CONFIG_THREE_FB_BUFFER)
+ size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
+ #else
+ size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
+ #endif
+ return ALIGN(size,SZ_1M);
+}
+
projects / firefly-linux-kernel-4.4.55.git / commitdiff