rk29_map_common_io();
rk29_setup_early_printk();
rk29_sram_init();
- rk29_clock_init(periph_pll_288mhz);
+ rk29_clock_init(periph_pll_default);
rk29_iomux_init();
ddr_init(DDR_TYPE,DDR_FREQ); // DDR3_1333H, 400
}
clk_set_rate_nolock(&pclk_periph, pclk_p);
clk_set_parent_nolock(&clk_uhost, &general_pll_clk);
clk_set_rate_nolock(&clk_uhost, 48 * MHZ);
+ if (clk_uhost.rate != 48 * MHZ)
+ clk_set_parent_nolock(&clk_uhost, &otgphy1_clkin);
clk_set_parent_nolock(&clk_i2s0_div, &general_pll_clk);
clk_set_parent_nolock(&clk_i2s1_div, &general_pll_clk);
clk_set_parent_nolock(&clk_spdif_div, &general_pll_clk);
printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz",
arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, general_pll_clk.rate / MHZ, clk_core.rate / MHZ,
aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ);
- printk(KERN_CONT " (20110714)\n");
+ printk(KERN_CONT " (20110715)\n");
}
void __init rk29_clock_init(enum periph_pll ppll_rate)
int board_boot_mode(void);
enum periph_pll {
- periph_pll_96mhz = 96000000,
+ periph_pll_96mhz = 96000000, /* save more power */
periph_pll_144mhz = 144000000,
periph_pll_288mhz = 288000000, /* for USB 1.1 */
periph_pll_300mhz = 300000000, /* for Ethernet */
+#if defined(CONFIG_RK29_VMAC) && defined(CONFIG_USB20_HOST_EN)
+ periph_pll_default = periph_pll_300mhz,
+#else
+ periph_pll_default = periph_pll_288mhz,
+#endif
};
enum codec_pll {