rk29: fix for vmac and usb host 1.1 both enabled
author黄涛 <huangtao@rock-chips.com>
Fri, 15 Jul 2011 03:03:32 +0000 (11:03 +0800)
committer黄涛 <huangtao@rock-chips.com>
Fri, 15 Jul 2011 03:04:11 +0000 (11:04 +0800)
arch/arm/mach-rk29/board-rk29-ddr3sdk.c
arch/arm/mach-rk29/board-rk29sdk.c
arch/arm/mach-rk29/clock.c
arch/arm/mach-rk29/include/mach/board.h

index 4fb9faf0dbd3739dbc009f393a9798eb2a76ab6c..90c59030924ae4ca270ade572c9f3b02bd85e394 100755 (executable)
@@ -1746,7 +1746,7 @@ static void __init machine_rk29_mapio(void)
        rk29_map_common_io();
        rk29_setup_early_printk();
        rk29_sram_init();
-       rk29_clock_init(periph_pll_288mhz);
+       rk29_clock_init(periph_pll_default);
        rk29_iomux_init();
        ddr_init(DDR_TYPE, DDR_FREQ);
 }
index a9867898e0ccc177f7a1e93526406ecd31be2480..7a11667ce000a98050be3efd05c32bd1866a6ccc 100755 (executable)
@@ -1746,7 +1746,7 @@ static void __init machine_rk29_mapio(void)
        rk29_map_common_io();
        rk29_setup_early_printk();
        rk29_sram_init();
-       rk29_clock_init(periph_pll_288mhz);
+       rk29_clock_init(periph_pll_default);
        rk29_iomux_init();
     ddr_init(DDR_TYPE,DDR_FREQ);  // DDR3_1333H, 400
 }
index 9d9af56a4e283c6bb6ab9bd44384b82395550e7e..f15715cdaecf46fd40203977a8d07daa75a295f3 100755 (executable)
@@ -2526,6 +2526,8 @@ static void __init rk29_clock_common_init(unsigned long ppll_rate, unsigned long
        clk_set_rate_nolock(&pclk_periph, pclk_p);
        clk_set_parent_nolock(&clk_uhost, &general_pll_clk);
        clk_set_rate_nolock(&clk_uhost, 48 * MHZ);
+       if (clk_uhost.rate != 48 * MHZ)
+               clk_set_parent_nolock(&clk_uhost, &otgphy1_clkin);
        clk_set_parent_nolock(&clk_i2s0_div, &general_pll_clk);
        clk_set_parent_nolock(&clk_i2s1_div, &general_pll_clk);
        clk_set_parent_nolock(&clk_spdif_div, &general_pll_clk);
@@ -2636,7 +2638,7 @@ void __init rk29_clock_init2(enum periph_pll ppll_rate, enum codec_pll cpll_rate
        printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz",
               arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, general_pll_clk.rate / MHZ, clk_core.rate / MHZ,
               aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ);
-       printk(KERN_CONT " (20110714)\n");
+       printk(KERN_CONT " (20110715)\n");
 }
 
 void __init rk29_clock_init(enum periph_pll ppll_rate)
index e2b47210fc82222788fc30971f5c5488faecdfb5..706abdda19e8a0e5503b321be4d2e3ef1056e5f9 100755 (executable)
@@ -299,10 +299,15 @@ void __init board_power_init(void);
 int board_boot_mode(void);
 
 enum periph_pll {
-       periph_pll_96mhz = 96000000,
+       periph_pll_96mhz = 96000000, /* save more power */
        periph_pll_144mhz = 144000000,
        periph_pll_288mhz = 288000000, /* for USB 1.1 */
        periph_pll_300mhz = 300000000, /* for Ethernet */
+#if defined(CONFIG_RK29_VMAC) && defined(CONFIG_USB20_HOST_EN)
+       periph_pll_default = periph_pll_300mhz,
+#else
+       periph_pll_default = periph_pll_288mhz,
+#endif
 };
 
 enum codec_pll {