rk29: L2 cache设置变更。根据IC部的建议，810~972频率，data ram latency设为6 cycles

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index f5e368dc0912dab82cc778552018813b7d075466..9e41985cca25b4c18a3fe1182185687b0a099dbc 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -272,7 +272,7 @@ __v7_setup:
        bic     r5, r5, #7 << 6
        bic     r5, r5, #15
        orr     r5, r5, #3 << 6                 @ Tag RAM latency: b011 = 4 cycles
-       orr     r5, r5, #4                      @ Data RAM latency: b0100 = 5 cycles
+       orr     r5, r5, #5                      @ Data RAM latency: b0101 = 6 cycles
        mcr     p15, 1, r5, c9, c0, 2
 #endif