iwlwifi: TX update chicken bits
authorWinkler, Tomas <tomas.winkler@intel.com>
Wed, 19 Nov 2008 23:32:27 +0000 (15:32 -0800)
committerJohn W. Linville <linville@tuxdriver.com>
Wed, 26 Nov 2008 14:47:39 +0000 (09:47 -0500)
This instructs FH to increment the retry count of a packet when
it is brought from the memory to TX-FIFO to save transactions
during aggregation flow.

Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/iwlwifi/iwl-4965.c
drivers/net/wireless/iwlwifi/iwl-5000.c
drivers/net/wireless/iwlwifi/iwl-fh.h

index 60769b12b68525abc24d09a78c6d8ebf49e7e5b7..ab0b40531989b060fc9e1b247485fa21435408b8 100644 (file)
@@ -695,6 +695,7 @@ static int iwl4965_alive_notify(struct iwl_priv *priv)
        unsigned long flags;
        int ret;
        int i, chan;
+       u32 reg_val;
 
        spin_lock_irqsave(&priv->lock, flags);
 
@@ -724,6 +725,11 @@ static int iwl4965_alive_notify(struct iwl_priv *priv)
                                FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
                                FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 
+       /* Update FH chicken bits */
+       reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
+       iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
+                          reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
+
        /* Disable chain mode for all queues */
        iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
 
index d73760c3f769f2033e2c9a22ecb6385051bb7fcc..a738886b434f66e907eb332b81d1d28ca7fc09bb 100644 (file)
@@ -703,6 +703,7 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
        unsigned long flags;
        int ret;
        int i, chan;
+       u32 reg_val;
 
        spin_lock_irqsave(&priv->lock, flags);
 
@@ -732,6 +733,11 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
                                FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
                                FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 
+       /* Update FH chicken bits */
+       reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
+       iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
+                          reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
+
        iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
                IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
        iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
index bc20acb36aa600b667e3ababde71c593019f175c..c3dadb03701c1993cb8af8a2af1cdb6182870488 100644 (file)
 #define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
                (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
 
+#define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98)
+/* Instruct FH to increment the retry count of a packet when
+ * it is brought from the memory to TX-FIFO
+ */
+#define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN   (0x00000002)
 
 /**
  * struct iwl_rb_status - reseve buffer status