Add a sanity-check to tablegen to catch the case where isSimpleLoad

is set but mayLoad is not set. Fix all the problems this turned up.

Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60459 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp
index aedd7c9be7e58274526dccf458c62a2db4c6a32e..727f0a5cd14f0562ebd907eaf1f09cbdd939e864 100644 (file)
--- a/lib/CodeGen/BranchFolding.cpp
+++ b/lib/CodeGen/BranchFolding.cpp
@@ -414,7 +414,7 @@ static unsigned EstimateRuntime(MachineBasicBlock::iterator I,
     const TargetInstrDesc &TID = I->getDesc();
     if (TID.isCall())
       Time += 10;
-    else if (TID.isSimpleLoad() || TID.mayStore())
+    else if (TID.mayLoad() || TID.mayStore())
       Time += 2;
     else
       ++Time;

diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index b85daa13f5f68f6f42ace66728d32e987123ec94..cd5f321f98b5db58e4e4bd0227adcbbc47dd631d 100644 (file)
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -834,7 +834,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   assert(Offset && "This code isn't needed if offset already handled!");
 
   if (isThumb) {
-    if (Desc.isSimpleLoad()) {
+    if (Desc.mayLoad()) {
       // Use the destination register to materialize sp + offset.
       unsigned TmpReg = MI.getOperand(0).getReg();
       bool UseRR = false;

diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index c4e6edc2e10bcc23c85d3875616b2718b7600f08..531b7fa3cd8a533ca59aead83e2e785da136d575 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -570,7 +570,9 @@ def : Pat<(truncstorei8 GPRC:$DATA, GPRC:$addr),
 
 
 //load address, rellocated gpdist form
-let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
+let OutOperandList = (ops GPRC:$RA),
+    InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM),
+    mayLoad = 1 in {
 def LDAg  : MForm<0x08, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;  //Load address
 def LDAHg : MForm<0x09, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;  //Load address
 }
@@ -589,7 +591,9 @@ let OutOperandList = (outs GPRC:$RR),
 def STQ_C : MForm<0x2F, 0, "stq_l $RA,$DISP($RB)", [], s_ist>;
 def STL_C : MForm<0x2E, 0, "stl_l $RA,$DISP($RB)", [], s_ist>;
 }
-let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
+let OutOperandList = (ops GPRC:$RA),
+    InOperandList = (ops s64imm:$DISP, GPRC:$RB),
+    mayLoad = 1 in {
 def LDQ_L : MForm<0x2B, 1, "ldq_l $RA,$DISP($RB)", [], s_ild>;
 def LDL_L : MForm<0x2A, 1, "ldl_l $RA,$DISP($RB)", [], s_ild>;
 }

diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index b9b7496a1b8728c555c7c604826407d38707f4ee..14745e61e1420222d785cbaa7185cffdca9b0103 100644 (file)
--- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -72,7 +72,7 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
   
   const TargetInstrDesc &TID = TII.get(Opcode);
   
-  isLoad  = TID.isSimpleLoad();
+  isLoad  = TID.mayLoad();
   isStore = TID.mayStore();
   
   unsigned TSFlags = TID.TSFlags;

diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index 6867cd7d737d6c842c36810880c8ebcabec3e3ce..a2f1834165b64e3c79025549211b6033b7ae2017 100644 (file)
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -487,6 +487,7 @@ def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
                    PPC970_DGroup_Cracked;
 
 // Update forms.
+let mayLoad = 1 in
 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
                             ptr_rc:$rA),
                     "lhau $rD, $disp($rA)", LdStGeneral,
@@ -520,6 +521,7 @@ def LWZX8 : XForm_1<31,  23, (outs G8RC:$rD), (ins memrr:$src),
                    
                    
 // Update forms.
+let mayLoad = 1 in {
 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
                     "lbzu $rD, $addr", LdStGeneral,
                     []>, RegConstraint<"$addr.reg = $ea_result">,
@@ -533,6 +535,7 @@ def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
                     []>, RegConstraint<"$addr.reg = $ea_result">,
                     NoEncode<"$ea_result">;
 }
+}
 
 
 // Full 8-byte loads.
@@ -544,6 +547,7 @@ def LDX  : XForm_1<31,  21, (outs G8RC:$rD), (ins memrr:$src),
                    "ldx $rD, $src", LdStLD,
                    [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
                    
+let mayLoad = 1 in
 def LDU  : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
                     "ldu $rD, $addr", LdStLD,
                     []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 0cb7c854130347f293880bf89838f96e68d35577..4106c4582a63b6756676b5f9dca351937a9faa06 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -683,6 +683,7 @@ def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
 
 
 // Unindexed (r+i) Loads with Update (preinc).
+let mayLoad = 1 in {
 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
                    "lbzu $rD, $addr", LdStGeneral,
                    []>, RegConstraint<"$addr.reg = $ea_result">,
@@ -713,6 +714,7 @@ def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
                   []>, RegConstraint<"$addr.reg = $ea_result">,
                    NoEncode<"$ea_result">;
 }
+}
 
 // Indexed (r+r) Loads.
 //

diff --git a/utils/TableGen/CodeGenDAGPatterns.cpp b/utils/TableGen/CodeGenDAGPatterns.cpp
index 859a8ccac8d9e6cb1286f07b250547fbab038dcb..b3ed27b8d8971b95b5b1e5e4527c11b5874bc8e3 100644 (file)
--- a/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -1759,6 +1759,15 @@ static void InferFromPattern(const CodeGenInstruction &Inst,
     MayLoad = true;
   }
 
+  // Sanity-check the isSimpleLoad flag.
+  if (Inst.isSimpleLoad) {
+    if (!MayLoad)
+      fprintf(stderr,
+              "Warning: mayLoad flag not set or inferred for instruction '%s'"
+              " which has isSimpleLoad set.\n",
+              Inst.TheDef->getName().c_str());
+  }
+
   if (Inst.neverHasSideEffects) {
     if (HadPattern)
       fprintf(stderr, "Warning: neverHasSideEffects set on instruction '%s' "

diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp
index 3674a136c9cef5251aa55b6f79b3544482b19b88..a6e3730ab12fd1b88359c852e1ee81dbe3a49674 100644 (file)
--- a/utils/TableGen/DAGISelEmitter.cpp
+++ b/utils/TableGen/DAGISelEmitter.cpp
@@ -1097,7 +1097,7 @@ public:
 
       // Generate MemOperandSDNodes nodes for each memory accesses covered by 
       // this pattern.
-      if (II.isSimpleLoad | II.mayLoad | II.mayStore) {
+      if (II.mayLoad | II.mayStore) {
         std::vector<std::string>::const_iterator mi, mie;
         for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) {
           std::string LSIName = "LSI_" + *mi;