Print some new nodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21001 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 023848a9f9187f03ec32666cd9ca1ad676a188d8..7f15e19f9d5874814773afc2ef4a29113cd9c17a 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -924,7 +924,9 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
   default:
     // FIXME: MEMOIZE!!
     SDNode *N = new SDNode(Opcode, Children);
-    if (Opcode != ISD::ADD_PARTS && Opcode != ISD::SUB_PARTS) {
+    if (Opcode != ISD::ADD_PARTS && Opcode != ISD::SUB_PARTS &&
+        Opcode != ISD::SRA_PARTS && Opcode != ISD::SRL_PARTS &&
+        Opcode != ISD::SHL_PARTS) {
       N->setValueTypes(VT);
     } else {
       std::vector<MVT::ValueType> V(N->getNumOperands()/2, VT);
@@ -1131,6 +1133,9 @@ const char *SDNode::getOperationName() const {
   case ISD::SELECT: return "select";
   case ISD::ADD_PARTS:   return "add_parts";
   case ISD::SUB_PARTS:   return "sub_parts";
+  case ISD::SHL_PARTS:   return "shl_parts";
+  case ISD::SRA_PARTS:   return "sra_parts";
+  case ISD::SRL_PARTS:   return "srl_parts";
 
     // Conversion operators.
   case ISD::SIGN_EXTEND: return "sign_extend";