Size reducing SP adjusting t2ADDri needs to check predication.

tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the
predicate is anything other than "always."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134130 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Thumb2SizeReduction.cpp b/lib/Target/ARM/Thumb2SizeReduction.cpp
index 65846b242215aa2a2995ef45d1d23123e221ddfa..cb44f8e71c47788e53d5a97778d84a588555436b 100644 (file)
--- a/lib/Target/ARM/Thumb2SizeReduction.cpp
+++ b/lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -491,11 +491,14 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
     // Try to reduce to tADDrSPi.
     unsigned Imm = MI->getOperand(2).getImm();
     // The immediate must be in range, the destination register must be a low
-    // reg, and the condition flags must not be being set.
+    // reg, the predicate must be "always" and the condition flags must not
+    // be being set.
     if (Imm & 3 || Imm > 1024)
       return false;
     if (!isARMLowRegister(MI->getOperand(0).getReg()))
       return false;
+    if (MI->getOperand(3).getImm() != ARMCC::AL)
+      return false;
     const MCInstrDesc &MCID = MI->getDesc();
     if (MCID.hasOptionalDef() &&
         MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)