switch TargetLowering::getConstraintType to take the entire constraint,

not just the first letter.  No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 71923b6d671b3ef19c2141da7db304033003a8ca..5f51d13fcd20b1c3dbd4ecdf9d655d18cf788a54 100644 (file)
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -806,9 +806,9 @@ public:
     C_Unknown              // Unsupported constraint.
   };
   
-  /// getConstraintType - Given a constraint letter, return the type of
-  /// constraint it is for this target.
-  virtual ConstraintType getConstraintType(char ConstraintLetter) const;
+  /// getConstraintType - Given a constraint, return the type of constraint it
+  /// is for this target.
+  virtual ConstraintType getConstraintType(const std::string &Constraint) const;
   
   
   /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 5a12aeb706995fab2dd892bd1ae4e52c5a4ac778..c41e00c0ebc3bb4ee272401056e409e8ed74bf34 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2633,9 +2633,9 @@ static std::string GetMostGeneralConstraint(std::vector<std::string> &C,
   std::string *Current = &C[0];
   // If we have multiple constraints, try to pick the most general one ahead
   // of time.  This isn't a wonderful solution, but handles common cases.
-  TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0][0]);
+  TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0]);
   for (unsigned j = 1, e = C.size(); j != e; ++j) {
-    TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j][0]);
+    TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j]);
     if (getConstraintGenerality(ThisFlavor) > 
         getConstraintGenerality(Flavor)) {
       // This constraint letter is more general than the previous one,
@@ -2748,7 +2748,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
     case InlineAsm::isOutput: {
       TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
       if (ConstraintCode.size() == 1)   // not a physreg name.
-        CTy = TLI.getConstraintType(ConstraintCode[0]);
+        CTy = TLI.getConstraintType(ConstraintCode);
       
       if (CTy == TargetLowering::C_Memory) {
         // Memory output.
@@ -2863,7 +2863,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
       
       TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
       if (ConstraintCode.size() == 1)   // not a physreg name.
-        CTy = TLI.getConstraintType(ConstraintCode[0]);
+        CTy = TLI.getConstraintType(ConstraintCode);
         
       if (CTy == TargetLowering::C_Other) {
         InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,

diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 718d983389253359f33f6a0ae024794155ec5e80..7436c1747adf03d76253e3a59a49404b0948a6c0 100644 (file)
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1828,28 +1828,32 @@ PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
 //===----------------------------------------------------------------------===//
 
 TargetLowering::ConstraintType
-TargetLowering::getConstraintType(char ConstraintLetter) const {
+TargetLowering::getConstraintType(const std::string &Constraint) const {
   // FIXME: lots more standard ones to handle.
-  switch (ConstraintLetter) {
-  default: return C_Unknown;
-  case 'r': return C_RegisterClass;
-  case 'm':    // memory
-  case 'o':    // offsetable
-  case 'V':    // not offsetable
-    return C_Memory;
-  case 'i':    // Simple Integer or Relocatable Constant
-  case 'n':    // Simple Integer
-  case 's':    // Relocatable Constant
-  case 'I':    // Target registers.
-  case 'J':
-  case 'K':
-  case 'L':
-  case 'M':
-  case 'N':
-  case 'O':
-  case 'P':
-    return C_Other;
+  if (Constraint.size() == 1) {
+    switch (Constraint[0]) {
+    default: break;
+    case 'r': return C_RegisterClass;
+    case 'm':    // memory
+    case 'o':    // offsetable
+    case 'V':    // not offsetable
+      return C_Memory;
+    case 'i':    // Simple Integer or Relocatable Constant
+    case 'n':    // Simple Integer
+    case 's':    // Relocatable Constant
+    case 'I':    // Target registers.
+    case 'J':
+    case 'K':
+    case 'L':
+    case 'M':
+    case 'N':
+    case 'O':
+    case 'P':
+      return C_Other;
+    }
   }
+  // TODO: Handle registers.
+  return C_Unknown;
 }
 
 /// isOperandValidForConstraint - Return the specified operand (possibly

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 2521e3b1d037717e7ad6a2748aebaf7dce81505b..cb3d923351fa24c6bc795a7fb6042a7c26c3600f 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -1550,12 +1550,14 @@ void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.
 ARMTargetLowering::ConstraintType
-ARMTargetLowering::getConstraintType(char ConstraintLetter) const {
-  switch (ConstraintLetter) {
-    case 'l':
-      return C_RegisterClass;
-    default: return TargetLowering::getConstraintType(ConstraintLetter);
+ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
+  if (Constraint.size() == 1) {
+    switch (Constraint[0]) {
+    default:  break;
+    case 'l': return C_RegisterClass;
+    }
   }
+  return TargetLowering::getConstraintType(Constraint);
 }
 
 std::pair<unsigned, const TargetRegisterClass*> 

diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h
index 2c2a2cd1b237290ef15a09ed1ded5699e2c097a5..149628510b49299a5706c83b98869ba99663196e 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.h
+++ b/lib/Target/ARM/ARMISelLowering.h
@@ -133,7 +133,7 @@ namespace llvm {
                                                 uint64_t &KnownZero, 
                                                 uint64_t &KnownOne,
                                                 unsigned Depth) const;
-    ConstraintType getConstraintType(char ConstraintLetter) const;
+    ConstraintType getConstraintType(const std::string &Constraint) const;
     std::pair<unsigned, const TargetRegisterClass*> 
       getRegForInlineAsmConstraint(const std::string &Constraint,
                                    MVT::ValueType VT) const;

diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index e8ae5a3e355f13afee0d96231fdb188a347e48fe..4f636dc8f911e2c43942f653be468f9491ea7a13 100644 (file)
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -571,14 +571,16 @@ SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.
 AlphaTargetLowering::ConstraintType 
-AlphaTargetLowering::getConstraintType(char ConstraintLetter) const {
-  switch (ConstraintLetter) {
-  default: break;
-  case 'f':
-  case 'r':
-    return C_RegisterClass;
-  }  
-  return TargetLowering::getConstraintType(ConstraintLetter);
+AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
+  if (Constraint.size() == 1) {
+    switch (Constraint[0]) {
+    default: break;
+    case 'f':
+    case 'r':
+      return C_RegisterClass;
+    }
+  }
+  return TargetLowering::getConstraintType(Constraint);
 }
 
 std::vector<unsigned> AlphaTargetLowering::

diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h
index 7b26d836eefb810d3c2a8e9734f4f8f4d9c178cc..24e40a5576456155d9dc11ce434f292880211480 100644 (file)
--- a/lib/Target/Alpha/AlphaISelLowering.h
+++ b/lib/Target/Alpha/AlphaISelLowering.h
@@ -81,7 +81,7 @@ namespace llvm {
                 bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, 
                 ArgListTy &Args, SelectionDAG &DAG);
 
-    ConstraintType getConstraintType(char ConstraintLetter) const;
+    ConstraintType getConstraintType(const std::string &Constraint) const;
 
     std::vector<unsigned> 
       getRegClassForInlineAsmConstraint(const std::string &Constraint,

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 54d6c4f87bf1c811c07379569bca565606ff141f..adfe3b70a1e3bbb0dba98a62fdf7d9a068a5b03e 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3105,20 +3105,22 @@ void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
 }
 
 
-/// getConstraintType - Given a constraint letter, return the type of
+/// getConstraintType - Given a constraint, return the type of
 /// constraint it is for this target.
 PPCTargetLowering::ConstraintType 
-PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
-  switch (ConstraintLetter) {
-  default: break;
-  case 'b':
-  case 'r':
-  case 'f':
-  case 'v':
-  case 'y':
-    return C_RegisterClass;
-  }  
-  return TargetLowering::getConstraintType(ConstraintLetter);
+PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
+  if (Constraint.size() == 1) {
+    switch (Constraint[0]) {
+    default: break;
+    case 'b':
+    case 'r':
+    case 'f':
+    case 'v':
+    case 'y':
+      return C_RegisterClass;
+    }
+  }
+  return TargetLowering::getConstraintType(Constraint);
 }
 
 std::pair<unsigned, const TargetRegisterClass*> 

diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index cc1f032493f0031a27abd47c3afbb7cd27c7395c..e66d16590bcd65a3d1976dafe2c9afc959bf8626 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -229,7 +229,7 @@ namespace llvm {
     virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
                                                        MachineBasicBlock *MBB);
     
-    ConstraintType getConstraintType(char ConstraintLetter) const;
+    ConstraintType getConstraintType(const std::string &Constraint) const;
     std::pair<unsigned, const TargetRegisterClass*> 
       getRegForInlineAsmConstraint(const std::string &Constraint,
                                    MVT::ValueType VT) const;

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 3796f3090c77af10d03b33d6865a97fb9f1424d2..1686c25ed09162b45983da0bbb632ac6ffb918a5 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4521,19 +4521,23 @@ SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.
 X86TargetLowering::ConstraintType
-X86TargetLowering::getConstraintType(char ConstraintLetter) const {
-  switch (ConstraintLetter) {
-  case 'A':
-  case 'r':
-  case 'R':
-  case 'l':
-  case 'q':
-  case 'Q':
-  case 'x':
-  case 'Y':
-    return C_RegisterClass;
-  default: return TargetLowering::getConstraintType(ConstraintLetter);
+X86TargetLowering::getConstraintType(const std::string &Constraint) const {
+  if (Constraint.size() == 1) {
+    switch (Constraint[0]) {
+    case 'A':
+    case 'r':
+    case 'R':
+    case 'l':
+    case 'q':
+    case 'Q':
+    case 'x':
+    case 'Y':
+      return C_RegisterClass;
+    default:
+      break;
+    }
   }
+  return TargetLowering::getConstraintType(Constraint);
 }
 
 /// isOperandValidForConstraint - Return the specified operand (possibly

diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index 3ed8d18f4ed1244012540469c8ab41bd04a55a2f..2e43778a3fce29de60a130960f7f4f135ea53c6c 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -316,7 +316,7 @@ namespace llvm {
     
     SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
 
-    ConstraintType getConstraintType(char ConstraintLetter) const;
+    ConstraintType getConstraintType(const std::string &Constraint) const;
      
     std::vector<unsigned> 
       getRegClassForInlineAsmConstraint(const std::string &Constraint,