Hook up one type, v4f32, to the VR RegisterClass for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24517 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 9526ae1f2a7c755742a36e84f1c5a9c32402bda0..1ef1d3e9d0e7be1db78288e3d075fdd715fb67ce 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -121,6 +121,12 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
     setOperationAction(ISD::SRA, MVT::i64, Custom);
   }
   
+  if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
+    // FIXME: AltiVec supports a wide variety of packed types.  For now, we're
+    // bringing up support with just v4f32.
+    addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
+  }
+  
   setSetCCResultContents(ZeroOrOneSetCCResult);
   
   computeRegisterProperties();