clk: rockchip: rk3228: add SCLK_SDIO_SRC clk id
authorElaine Zhang <zhangqing@rock-chips.com>
Thu, 15 Jun 2017 09:01:21 +0000 (17:01 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Fri, 16 Jun 2017 06:14:29 +0000 (14:14 +0800)
This patch exports sdio src clock for dts reference.

Change-Id: I3e83cce4da3d82af4b18df43ecd51c504d308c02
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
drivers/clk/rockchip/clk-rk3228.c
include/dt-bindings/clock/rk3228-cru.h

index cd6efa761f14bdd53103fcf6ce5db9d5cf34e9ba..ca2b87d05418ea9118031f98a9bc3ec250316e4c 100644 (file)
@@ -392,7 +392,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
                        RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
                        RK2928_CLKGATE_CON(2), 11, GFLAGS),
 
-       COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
+       COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0,
                        RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
                        RK2928_CLKGATE_CON(2), 13, GFLAGS),
        DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
index 007267331695c6037507ca926a4b57600cb8faf6..d9544a90b94a06024e2d492e9ae985c827a1fb80 100644 (file)
@@ -49,6 +49,7 @@
 #define SCLK_EMMC_DRV          117
 #define SCLK_SDMMC_SAMPLE      118
 #define SCLK_SDIO_SAMPLE       119
+#define SCLK_SDIO_SRC          120
 #define SCLK_EMMC_SAMPLE       121
 #define SCLK_VOP               122
 #define SCLK_HDMI_HDCP         123