pinctrl: sirf: fix the pin number and mux bit for usp0

we missed a pin and related mux bit for usp pin group, this
patch fixes it.

Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
index 1fa39a4441717e233c8844c0a7e72357356ece0d..c641be9c5b8088688377c17731b864650cf4ddc6 100644 (file)
--- a/drivers/pinctrl/sirf/pinctrl-atlas6.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c
@@ -496,7 +496,7 @@ static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
 static const struct sirfsoc_muxmask usp0_muxmask[] = {
        {
                .group = 1,
-               .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
+               .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
        },
 };
 
@@ -507,7 +507,7 @@ static const struct sirfsoc_padmux usp0_padmux = {
        .funcval = 0,
 };
 
-static const unsigned usp0_pins[] = { 51, 52, 53, 54 };
+static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
 
 static const struct sirfsoc_muxmask usp1_muxmask[] = {
        {