R0 is a sub-register of X0, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36939 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index 3891755247ef77d0a9a30daf8e32ffb031579b05..0b3b4cabde77d456acc52d7e7c7ba838a2ae8f39 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -22,9 +22,9 @@ class GPR<bits<5> num, string n> : PPCReg<n> {
 }
 
 // GP8 - One of the 32 64-bit general-purpose registers
-class GP8<GPR Alias> : PPCReg<Alias.Name> {
-  field bits<5> Num = Alias.Num;
-  let Aliases = [Alias];
+class GP8<GPR SubReg> : PPCReg<SubReg.Name> {
+  field bits<5> Num = SubReg.Num;
+  let SubRegs = [SubReg];
 }
 
 // SPR - One of the 32-bit special-purpose registers