Add simple reg-reg add.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70712 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td
index 308a8d0f87bc763d456bb0051441905ccfdc6873..06709d5459374158c94182e3aaee06d69ba6681a 100644 (file)
--- a/lib/Target/MSP430/MSP430InstrInfo.td
+++ b/lib/Target/MSP430/MSP430InstrInfo.td
@@ -60,3 +60,17 @@ def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
                      "mov.w\t{$src, $dst|$dst, $src}",
                      [(set GR16:$dst, imm:$src)]>;
 }
+
+//===----------------------------------------------------------------------===//
+// Arithmetic Instructions
+
+let Defs = [SR] in {
+let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
+
+// FIXME: Provide proper encoding!
+def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+                     "add.w\t{$src2, $dst|$dst, $src2}",
+                     [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
+                      (implicit SR)]>;
+}
+}