Determine whether a spill kills the register it's spilling before insertion rather...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46953 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 12064a957c174eea6062307b0300e758fde71222..b14af2761c6bcf7817f918b00e052f1555d630f0 100644 (file)
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -303,17 +303,12 @@ void RALocal::spillVirtReg(MachineBasicBlock &MBB,
     const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
     int FrameIndex = getStackSpaceFor(VirtReg, RC);
     DOUT << " to stack slot #" << FrameIndex;
-    TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
-
     // If the instruction reads the register that's spilled, (e.g. this can
     // happen if it is a move to a physical register), then the spill
     // instruction is not a kill.
-    if (I != MBB.end() && I->findRegisterUseOperandIdx(PhysReg) != -1) {
-      MachineBasicBlock::iterator StoreMI = prior(I);
-      int Idx = StoreMI->findRegisterUseOperandIdx(PhysReg, true);
-      assert(Idx != -1 && "Unrecognized spill instruction!");
-      StoreMI->getOperand(Idx).setIsKill(false);
-    }
+    bool isKill = !(I != MBB.end() &&
+                    I->findRegisterUseOperandIdx(PhysReg) != -1);
+    TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC);
     ++NumStores;   // Update statistics
   }
 

diff --git a/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll
new file mode 100644 (file)
index 0000000..5edf6b7
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll
@@ -0,0 +1,10 @@
+; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin -regalloc=local
+
+define i32 @bork(i64 %foo, i64 %bar) {
+entry:
+        %tmp = load i64* null, align 8          ; <i64> [#uses=2]
+        %tmp2 = icmp ule i64 %tmp, 0            ; <i1> [#uses=1]
+        %min = select i1 %tmp2, i64 %tmp, i64 0   ; <i64> [#uses=1]
+        store i64 %min, i64* null, align 8
+        ret i32 0
+}