This target doesn't support fabs/fneg yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21010 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index ba5178b621287ad089168de7fc039ed4d5400ff8..7242f8f1fdb4a246d8dc76c7472f5916c7a7788d 100644 (file)
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -75,6 +75,10 @@ namespace {
       setOperationAction(ISD::MEMSET           , MVT::Other, Expand);
       setOperationAction(ISD::MEMCPY           , MVT::Other, Expand);
 
+      // We don't support these yet.
+      setOperationAction(ISD::FNEG             , MVT::f64  , Expand);
+      setOperationAction(ISD::FABS             , MVT::f64  , Expand);
+
       //Doesn't work yet
       setOperationAction(ISD::SETCC            , MVT::f32,   Promote);
 

diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index 16607cbcc32ee680aba19b8ffcc80653bbb9b11b..bb31fc7f5c8caf2d5b545dab4dec9b332a9e4bc6 100644 (file)
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -80,6 +80,9 @@ namespace {
       setOperationAction(ISD::MEMSET           , MVT::Other, Expand);
       setOperationAction(ISD::MEMCPY           , MVT::Other, Expand);
 
+      // We don't support these yet.
+      setOperationAction(ISD::FNEG             , MVT::f64  , Expand);
+      setOperationAction(ISD::FABS             , MVT::f64  , Expand);
       
       computeRegisterProperties();
 

diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index a6ebbadf569d6042daccc83f4c9c297fa67646ff..751b5533572c7b1ba138db22c4f421be45402e11 100644 (file)
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -53,6 +53,10 @@ namespace {
       // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
       setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
       setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
+
+      // We don't support these yet.
+      setOperationAction(ISD::FNEG             , MVT::f64  , Expand);
+      setOperationAction(ISD::FABS             , MVT::f64  , Expand);
       
       addLegalFPImmediate(+0.0); // Necessary for FSEL
       addLegalFPImmediate(-0.0); // 

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index ff23e66c04fead84e8ac1e637beafe34e540f907..c81b7794f7c51c498df53a139b4e2015518beef5 100644 (file)
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -63,6 +63,10 @@ namespace {
       setOperationAction(ISD::FP_ROUND_INREG   , MVT::f32  , Expand);
       setOperationAction(ISD::SEXTLOAD         , MVT::i1   , Expand);
       setOperationAction(ISD::SREM             , MVT::f64  , Expand);
+
+      // We don't support these yet.
+      setOperationAction(ISD::FNEG             , MVT::f64  , Expand);
+      setOperationAction(ISD::FABS             , MVT::f64  , Expand);
       
       // These should be promoted to a larger select which is supported.
 /**/  setOperationAction(ISD::SELECT           , MVT::i1   , Promote);