mmc: rk_sdmmc: add host->hw_reset for eMMC

diff --git a/drivers/mmc/host/rk_sdmmc.c b/drivers/mmc/host/rk_sdmmc.c
index 12caf5db93e9b915ef8b4c9933322ac27b41aa42..00c480dfadbed16516f9ef8776ac574bc028c70e 100755 (executable)
--- a/drivers/mmc/host/rk_sdmmc.c
+++ b/drivers/mmc/host/rk_sdmmc.c
@@ -1089,6 +1089,27 @@ static int dw_mci_get_cd(struct mmc_host *mmc)
        return present;
 }
 
+static void dw_mci_hw_reset(struct mmc_host *mmc)
+{
+    struct dw_mci_slot *slot = mmc_priv(mmc);
+
+    /* 
+     * According to eMMC spec 
+     * tRstW >= 1us ;   RST_n pulse width
+     * tRSCA >= 200us ; RST_n to Command time
+     * tRSTH >= 1us ;   RST_n high period
+     */
+
+    mci_writel(slot->host, RST_n, 0x1);
+    dsb();
+    udelay(10); //10us for bad quality eMMc.
+
+    mci_writel(slot->host, RST_n, 0x0);
+    dsb();
+    usleep_range(300, 1000); //ay least 300(> 200us)
+    
+}
+
 /*
  * Disable lower power mode.
  *
@@ -1177,6 +1198,7 @@ static const struct mmc_host_ops dw_mci_ops = {
        .set_ios                = dw_mci_set_ios,
        .get_ro                 = dw_mci_get_ro,
        .get_cd                 = dw_mci_get_cd,
+       .hw_reset       = dw_mci_hw_reset,
        .enable_sdio_irq        = dw_mci_enable_sdio_irq,
        .execute_tuning         = dw_mci_execute_tuning,
 };

diff --git a/drivers/mmc/host/rk_sdmmc.h b/drivers/mmc/host/rk_sdmmc.h
index ce50e561dbe3daeee3e1520df7d85c414d992b74..1b8b109f0b9d78e29228935a398f1c3c5fbd98b2 100755 (executable)
--- a/drivers/mmc/host/rk_sdmmc.h
+++ b/drivers/mmc/host/rk_sdmmc.h
@@ -16,42 +16,43 @@
 #ifndef _DW_MMC_H_
 #define _DW_MMC_H_
 
-#define DW_MMC_240A            0x240a
+#define DW_MMC_240A                    0x240a
 
-#define SDMMC_CTRL             0x000
-#define SDMMC_PWREN            0x004
+#define SDMMC_CTRL                     0x000
+#define SDMMC_PWREN                    0x004
 #define SDMMC_CLKDIV           0x008
 #define SDMMC_CLKSRC           0x00c
 #define SDMMC_CLKENA           0x010
-#define SDMMC_TMOUT            0x014
-#define SDMMC_CTYPE            0x018
+#define SDMMC_TMOUT                    0x014
+#define SDMMC_CTYPE                    0x018
 #define SDMMC_BLKSIZ           0x01c
 #define SDMMC_BYTCNT           0x020
 #define SDMMC_INTMASK          0x024
 #define SDMMC_CMDARG           0x028
-#define SDMMC_CMD              0x02c
-#define SDMMC_RESP0            0x030
-#define SDMMC_RESP1            0x034
-#define SDMMC_RESP2            0x038
-#define SDMMC_RESP3            0x03c
+#define SDMMC_CMD                      0x02c
+#define SDMMC_RESP0                    0x030
+#define SDMMC_RESP1                    0x034
+#define SDMMC_RESP2                    0x038
+#define SDMMC_RESP3                    0x03c
 #define SDMMC_MINTSTS          0x040
 #define SDMMC_RINTSTS          0x044
 #define SDMMC_STATUS           0x048
 #define SDMMC_FIFOTH           0x04c
 #define SDMMC_CDETECT          0x050
 #define SDMMC_WRTPRT           0x054
-#define SDMMC_GPIO             0x058
+#define SDMMC_GPIO                     0x058
 #define SDMMC_TCBCNT           0x05c
 #define SDMMC_TBBCNT           0x060
 #define SDMMC_DEBNCE           0x064
-#define SDMMC_USRID            0x068
-#define SDMMC_VERID            0x06c
-#define SDMMC_HCON             0x070
+#define SDMMC_USRID                    0x068
+#define SDMMC_VERID                    0x06c
+#define SDMMC_HCON                     0x070
 #define SDMMC_UHS_REG          0x074
-#define SDMMC_BMOD             0x080
+#define SDMMC_RST_n            0x078
+#define SDMMC_BMOD                     0x080
 #define SDMMC_PLDMND           0x084
 #define SDMMC_DBADDR           0x088
-#define SDMMC_IDSTS            0x08c
+#define SDMMC_IDSTS                    0x08c
 #define SDMMC_IDINTEN          0x090
 #define SDMMC_DSCADDR          0x094
 #define SDMMC_BUFADDR          0x098