powerpc: Free up some CPU feature bits by moving out MMU-related features
authorMatt Evans <matt@ozlabs.org>
Wed, 6 Apr 2011 19:48:50 +0000 (19:48 +0000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Wed, 27 Apr 2011 04:18:52 +0000 (14:18 +1000)
Some of the 64bit PPC CPU features are MMU-related, so this patch moves
them to MMU_FTR_ bits.  All cpu_has_feature()-style tests are moved to
mmu_has_feature(), and seven feature bits are freed as a result.

Signed-off-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
20 files changed:
arch/powerpc/include/asm/cputable.h
arch/powerpc/include/asm/mmu.h
arch/powerpc/include/asm/mmu_context.h
arch/powerpc/kernel/cputable.c
arch/powerpc/kernel/entry_64.S
arch/powerpc/kernel/exceptions-64s.S
arch/powerpc/kernel/process.c
arch/powerpc/kernel/prom.c
arch/powerpc/kernel/setup_64.c
arch/powerpc/mm/hash_low_64.S
arch/powerpc/mm/hash_native_64.c
arch/powerpc/mm/hash_utils_64.c
arch/powerpc/mm/hugetlbpage.c
arch/powerpc/mm/slb.c
arch/powerpc/mm/slb_low.S
arch/powerpc/mm/stab.c
arch/powerpc/platforms/iseries/exception.S
arch/powerpc/platforms/iseries/setup.c
arch/powerpc/platforms/pseries/lpar.c
arch/powerpc/xmon/xmon.c

index 2d71523ebb03399e04b160804968e6766d7f97c7..3db2476704d6a3e8ed9d99047c65e48f4fa5083e 100644 (file)
@@ -178,23 +178,17 @@ extern const char *powerpc_base_platform;
 #define LONG_ASM_CONST(x)              0
 #endif
 
-#define CPU_FTR_SLB                    LONG_ASM_CONST(0x0000000100000000)
-#define CPU_FTR_16M_PAGE               LONG_ASM_CONST(0x0000000200000000)
-#define CPU_FTR_TLBIEL                 LONG_ASM_CONST(0x0000000400000000)
+
 #define CPU_FTR_HVMODE_206             LONG_ASM_CONST(0x0000000800000000)
 #define CPU_FTR_IABR                   LONG_ASM_CONST(0x0000002000000000)
 #define CPU_FTR_MMCRA                  LONG_ASM_CONST(0x0000004000000000)
 #define CPU_FTR_CTRL                   LONG_ASM_CONST(0x0000008000000000)
 #define CPU_FTR_SMT                    LONG_ASM_CONST(0x0000010000000000)
-#define CPU_FTR_LOCKLESS_TLBIE         LONG_ASM_CONST(0x0000040000000000)
-#define CPU_FTR_CI_LARGE_PAGE          LONG_ASM_CONST(0x0000100000000000)
 #define CPU_FTR_PAUSE_ZERO             LONG_ASM_CONST(0x0000200000000000)
 #define CPU_FTR_PURR                   LONG_ASM_CONST(0x0000400000000000)
 #define CPU_FTR_CELL_TB_BUG            LONG_ASM_CONST(0x0000800000000000)
 #define CPU_FTR_SPURR                  LONG_ASM_CONST(0x0001000000000000)
 #define CPU_FTR_DSCR                   LONG_ASM_CONST(0x0002000000000000)
-#define CPU_FTR_1T_SEGMENT             LONG_ASM_CONST(0x0004000000000000)
-#define CPU_FTR_NO_SLBIE_B             LONG_ASM_CONST(0x0008000000000000)
 #define CPU_FTR_VSX                    LONG_ASM_CONST(0x0010000000000000)
 #define CPU_FTR_SAO                    LONG_ASM_CONST(0x0020000000000000)
 #define CPU_FTR_CP_USE_DCBTZ           LONG_ASM_CONST(0x0040000000000000)
@@ -206,9 +200,10 @@ extern const char *powerpc_base_platform;
 
 #ifndef __ASSEMBLY__
 
-#define CPU_FTR_PPCAS_ARCH_V2  (CPU_FTR_SLB | \
-                                CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
-                                CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
+#define CPU_FTR_PPCAS_ARCH_V2  (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+
+#define MMU_FTR_PPCAS_ARCH_V2  (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
+                                MMU_FTR_16M_PAGE)
 
 /* We only set the altivec features if the kernel was compiled with altivec
  * support
@@ -408,38 +403,34 @@ extern const char *powerpc_base_platform;
 #define CPU_FTRS_POWER5        (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
            CPU_FTR_MMCRA | CPU_FTR_SMT | \
-           CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
-           CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \
-           CPU_FTR_POPCNTB)
+           CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
+           CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
            CPU_FTR_MMCRA | CPU_FTR_SMT | \
-           CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
+           CPU_FTR_COHERENT_ICACHE | \
            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
            CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_HVMODE_206 |\
            CPU_FTR_MMCRA | CPU_FTR_SMT | \
-           CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
+           CPU_FTR_COHERENT_ICACHE | \
            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
            CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
 #define CPU_FTRS_CELL  (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
-           CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \
-           CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
+           CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
            CPU_FTR_UNALIGNED_LD_STD)
 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
-           CPU_FTR_PPCAS_ARCH_V2 | \
-           CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
-           CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
+           CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
+           CPU_FTR_PURR | CPU_FTR_REAL_LE)
 #define CPU_FTRS_COMPATIBLE    (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 
 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
-           CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \
-           CPU_FTR_16M_PAGE)
+                    CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
 
 #ifdef __powerpc64__
 #ifdef CONFIG_PPC_BOOK3E
@@ -449,7 +440,7 @@ extern const char *powerpc_base_platform;
            (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
            CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
            CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T |           \
-           CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
+           CPU_FTR_VSX)
 #endif
 #else
 enum {
index bb40a06d3b7701d418b750a24b16a22385570bba..a39304b74f84cbe53f2164290dd0683dd3f8286f 100644 (file)
  */
 #define MMU_FTR_USE_PAIRED_MAS         ASM_CONST(0x01000000)
 
+/* MMU is SLB-based
+ */
+#define MMU_FTR_SLB                    ASM_CONST(0x02000000)
+
+/* Support 16M large pages
+ */
+#define MMU_FTR_16M_PAGE               ASM_CONST(0x04000000)
+
+/* Supports TLBIEL variant
+ */
+#define MMU_FTR_TLBIEL                 ASM_CONST(0x08000000)
+
+/* Supports tlbies w/o locking
+ */
+#define MMU_FTR_LOCKLESS_TLBIE         ASM_CONST(0x10000000)
+
+/* Large pages can be marked CI
+ */
+#define MMU_FTR_CI_LARGE_PAGE          ASM_CONST(0x20000000)
+
+/* 1T segments available
+ */
+#define MMU_FTR_1T_SEGMENT             ASM_CONST(0x40000000)
+
+/* Doesn't support the B bit (1T segment) in SLBIE
+ */
+#define MMU_FTR_NO_SLBIE_B             ASM_CONST(0x80000000)
+
+/* MMU feature bit sets for various CPUs */
+#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2  \
+       MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
+#define MMU_FTRS_POWER4                MMU_FTRS_DEFAULT_HPTE_ARCH_V2
+#define MMU_FTRS_PPC970                MMU_FTRS_POWER4
+#define MMU_FTRS_POWER5                MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
+#define MMU_FTRS_POWER6                MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
+#define MMU_FTRS_POWER7                MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | \
+                               MMU_FTR_TLBIE_206
+#define MMU_FTRS_CELL          MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
+                               MMU_FTR_CI_LARGE_PAGE
+#define MMU_FTRS_PA6T          MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
+                               MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
+#define MMU_FTRS_A2            MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \
+                               MMU_FTR_USE_TLBIVAX_BCAST | \
+                               MMU_FTR_LOCK_BCAST_INVAL | \
+                               MMU_FTR_USE_TLBRSRV | \
+                               MMU_FTR_USE_PAIRED_MAS | \
+                               MMU_FTR_TLBIEL | \
+                               MMU_FTR_16M_PAGE
 #ifndef __ASSEMBLY__
 #include <asm/cputable.h>
 
index 81fb41289d6cb071474c5df484a4ca81b963d1db..8e13f65b498ce53b188d2d5cdde05211795452ed 100644 (file)
@@ -67,7 +67,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
         * sub architectures.
         */
 #ifdef CONFIG_PPC_STD_MMU_64
-       if (cpu_has_feature(CPU_FTR_SLB))
+       if (mmu_has_feature(MMU_FTR_SLB))
                switch_slb(tsk, next);
        else
                switch_stab(tsk, next);
index 3d7b65ad4962b7ee77bdeb6a2a3ab14f24e56340..34d2722b9451f816b08405549a691d421ae7d81a 100644 (file)
@@ -201,7 +201,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER4 (gp)",
                .cpu_features           = CPU_FTRS_POWER4,
                .cpu_user_features      = COMMON_USER_POWER4,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_POWER4,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 8,
@@ -216,7 +216,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER4+ (gq)",
                .cpu_features           = CPU_FTRS_POWER4,
                .cpu_user_features      = COMMON_USER_POWER4,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_POWER4,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 8,
@@ -232,7 +232,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_features           = CPU_FTRS_PPC970,
                .cpu_user_features      = COMMON_USER_POWER4 |
                        PPC_FEATURE_HAS_ALTIVEC_COMP,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_PPC970,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 8,
@@ -250,7 +250,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_features           = CPU_FTRS_PPC970,
                .cpu_user_features      = COMMON_USER_POWER4 |
                        PPC_FEATURE_HAS_ALTIVEC_COMP,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_PPC970,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 8,
@@ -286,7 +286,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_features           = CPU_FTRS_PPC970,
                .cpu_user_features      = COMMON_USER_POWER4 |
                        PPC_FEATURE_HAS_ALTIVEC_COMP,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_PPC970,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 8,
@@ -304,7 +304,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_features           = CPU_FTRS_PPC970,
                .cpu_user_features      = COMMON_USER_POWER4 |
                        PPC_FEATURE_HAS_ALTIVEC_COMP,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_PPC970,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 8,
@@ -320,7 +320,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER5 (gr)",
                .cpu_features           = CPU_FTRS_POWER5,
                .cpu_user_features      = COMMON_USER_POWER5,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_POWER5,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 6,
@@ -340,7 +340,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER5+ (gs)",
                .cpu_features           = CPU_FTRS_POWER5,
                .cpu_user_features      = COMMON_USER_POWER5_PLUS,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_POWER5,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 6,
@@ -356,7 +356,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER5+ (gs)",
                .cpu_features           = CPU_FTRS_POWER5,
                .cpu_user_features      = COMMON_USER_POWER5_PLUS,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_POWER5,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 6,
@@ -373,7 +373,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER5+",
                .cpu_features           = CPU_FTRS_POWER5,
                .cpu_user_features      = COMMON_USER_POWER5_PLUS,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_POWER5,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .oprofile_cpu_type      = "ppc64/ibm-compat-v1",
@@ -387,7 +387,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_features           = CPU_FTRS_POWER6,
                .cpu_user_features      = COMMON_USER_POWER6 |
                        PPC_FEATURE_POWER6_EXT,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_POWER6,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 6,
@@ -406,7 +406,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER6 (architected)",
                .cpu_features           = CPU_FTRS_POWER6,
                .cpu_user_features      = COMMON_USER_POWER6,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_POWER6,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .oprofile_cpu_type      = "ppc64/ibm-compat-v1",
@@ -419,8 +419,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER7 (architected)",
                .cpu_features           = CPU_FTRS_POWER7,
                .cpu_user_features      = COMMON_USER_POWER7,
-               .mmu_features           = MMU_FTR_HPTE_TABLE |
-                       MMU_FTR_TLBIE_206,
+               .mmu_features           = MMU_FTRS_POWER7,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .oprofile_type          = PPC_OPROFILE_POWER4,
@@ -435,8 +434,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER7 (raw)",
                .cpu_features           = CPU_FTRS_POWER7,
                .cpu_user_features      = COMMON_USER_POWER7,
-               .mmu_features           = MMU_FTR_HPTE_TABLE |
-                       MMU_FTR_TLBIE_206,
+               .mmu_features           = MMU_FTRS_POWER7,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 6,
@@ -453,8 +451,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER7+ (raw)",
                .cpu_features           = CPU_FTRS_POWER7,
                .cpu_user_features      = COMMON_USER_POWER7,
-               .mmu_features           = MMU_FTR_HPTE_TABLE |
-                       MMU_FTR_TLBIE_206,
+               .mmu_features           = MMU_FTRS_POWER7,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 6,
@@ -473,7 +470,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_user_features      = COMMON_USER_PPC64 |
                        PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
                        PPC_FEATURE_SMT,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_CELL,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 4,
@@ -488,7 +485,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "PA6T",
                .cpu_features           = CPU_FTRS_PA6T,
                .cpu_user_features      = COMMON_USER_PA6T,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_PA6T,
                .icache_bsize           = 64,
                .dcache_bsize           = 64,
                .num_pmcs               = 6,
@@ -505,7 +502,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER4 (compatible)",
                .cpu_features           = CPU_FTRS_COMPATIBLE,
                .cpu_user_features      = COMMON_USER_PPC64,
-               .mmu_features           = MMU_FTR_HPTE_TABLE,
+               .mmu_features           = MMU_FTRS_DEFAULT_HPTE_ARCH_V2,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 6,
@@ -2020,11 +2017,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "A2 (>= DD2)",
                .cpu_features           = CPU_FTRS_A2,
                .cpu_user_features      = COMMON_USER_PPC64,
-               .mmu_features           = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
-                                         MMU_FTR_USE_TLBIVAX_BCAST |
-                                         MMU_FTR_LOCK_BCAST_INVAL |
-                                         MMU_FTR_USE_TLBRSRV |
-                                         MMU_FTR_USE_PAIRED_MAS,
+               .mmu_features           = MMU_FTRS_A2,
                .icache_bsize           = 64,
                .dcache_bsize           = 64,
                .num_pmcs               = 0,
index 64693706ebfd4833e8ab0ef601c7a638d40d85c3..d834425186aeaa7fae6905bd8bffb50d0d99354d 100644 (file)
@@ -468,10 +468,10 @@ BEGIN_FTR_SECTION
   FTR_SECTION_ELSE_NESTED(95)
        clrrdi  r6,r8,40        /* get its 1T ESID */
        clrrdi  r9,r1,40        /* get current sp 1T ESID */
-  ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_1T_SEGMENT, 95)
+  ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
 FTR_SECTION_ELSE
        b       2f
-ALT_FTR_SECTION_END_IFSET(CPU_FTR_SLB)
+ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
        clrldi. r0,r6,2         /* is new ESID c00000000? */
        cmpd    cr1,r6,r9       /* or is new ESID the same as current ESID? */
        cror    eq,4*cr1+eq,eq
@@ -485,7 +485,7 @@ BEGIN_FTR_SECTION
        li      r9,MMU_SEGSIZE_1T       /* insert B field */
        oris    r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
        rldimi  r7,r9,SLB_VSID_SSIZE_SHIFT,0
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
 
        /* Update the last bolted SLB.  No write barriers are needed
         * here, provided we only update the current CPU's SLB shadow
@@ -497,7 +497,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
        std     r7,SLBSHADOW_STACKVSID(r9)  /* Save VSID */
        std     r0,SLBSHADOW_STACKESID(r9)  /* Save ESID */
 
-       /* No need to check for CPU_FTR_NO_SLBIE_B here, since when
+       /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
         * we have 1TB segments, the only CPUs known to have the errata
         * only support less than 1TB of system memory and we'll never
         * actually hit this code path.
index ad06333631acab02f9984797421ab114afdba334..226cc8c62224d3e27b0e530abe9f6b73acc03a2d 100644 (file)
@@ -102,7 +102,7 @@ BEGIN_FTR_SECTION
        EXCEPTION_PROLOG_PSERIES_1(data_access_common, EXC_STD)
 FTR_SECTION_ELSE
        EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD)
-ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
+ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_SLB)
 
        . = 0x380
        .globl data_access_slb_pSeries
@@ -840,7 +840,7 @@ _STATIC(do_hash_page)
 BEGIN_FTR_SECTION
        andis.  r0,r4,0x0020            /* Is it a segment table fault? */
        bne-    do_ste_alloc            /* If so handle it */
-END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
 
        clrrdi  r11,r1,THREAD_SHIFT
        lwz     r0,TI_PREEMPT(r11)      /* If we're in an "NMI" */
index a01c2d93fd2f9fd31a9a05b5f7e8304ccfe0b6c3..095043d79946cfbfd8c9f15e56584ef393192456 100644 (file)
@@ -757,11 +757,11 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
                                _ALIGN_UP(sizeof(struct thread_info), 16);
 
 #ifdef CONFIG_PPC_STD_MMU_64
-       if (cpu_has_feature(CPU_FTR_SLB)) {
+       if (mmu_has_feature(MMU_FTR_SLB)) {
                unsigned long sp_vsid;
                unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
 
-               if (cpu_has_feature(CPU_FTR_1T_SEGMENT))
+               if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
                        sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
                                << SLB_VSID_SHIFT_1T;
                else
index c391dc4c8bad8ffa9e028e5d6bfb546c18509de7..5f5e6aed2b70b50f7d116c6e266cadb6687de4de 100644 (file)
@@ -123,18 +123,19 @@ static void __init move_device_tree(void)
  */
 static struct ibm_pa_feature {
        unsigned long   cpu_features;   /* CPU_FTR_xxx bit */
+       unsigned long   mmu_features;   /* MMU_FTR_xxx bit */
        unsigned int    cpu_user_ftrs;  /* PPC_FEATURE_xxx bit */
        unsigned char   pabyte;         /* byte number in ibm,pa-features */
        unsigned char   pabit;          /* bit number (big-endian) */
        unsigned char   invert;         /* if 1, pa bit set => clear feature */
 } ibm_pa_features[] __initdata = {
-       {0, PPC_FEATURE_HAS_MMU,        0, 0, 0},
-       {0, PPC_FEATURE_HAS_FPU,        0, 1, 0},
-       {CPU_FTR_SLB, 0,                0, 2, 0},
-       {CPU_FTR_CTRL, 0,               0, 3, 0},
-       {CPU_FTR_NOEXECUTE, 0,          0, 6, 0},
-       {CPU_FTR_NODSISRALIGN, 0,       1, 1, 1},
-       {CPU_FTR_CI_LARGE_PAGE, 0,      1, 2, 0},
+       {0, 0, PPC_FEATURE_HAS_MMU,     0, 0, 0},
+       {0, 0, PPC_FEATURE_HAS_FPU,     0, 1, 0},
+       {0, MMU_FTR_SLB, 0,             0, 2, 0},
+       {CPU_FTR_CTRL, 0, 0,            0, 3, 0},
+       {CPU_FTR_NOEXECUTE, 0, 0,       0, 6, 0},
+       {CPU_FTR_NODSISRALIGN, 0, 0,    1, 1, 1},
+       {0, MMU_FTR_CI_LARGE_PAGE, 0,   1, 2, 0},
        {CPU_FTR_REAL_LE, PPC_FEATURE_TRUE_LE, 5, 0, 0},
 };
 
@@ -166,9 +167,11 @@ static void __init scan_features(unsigned long node, unsigned char *ftrs,
                if (bit ^ fp->invert) {
                        cur_cpu_spec->cpu_features |= fp->cpu_features;
                        cur_cpu_spec->cpu_user_features |= fp->cpu_user_ftrs;
+                       cur_cpu_spec->mmu_features |= fp->mmu_features;
                } else {
                        cur_cpu_spec->cpu_features &= ~fp->cpu_features;
                        cur_cpu_spec->cpu_user_features &= ~fp->cpu_user_ftrs;
+                       cur_cpu_spec->mmu_features &= ~fp->mmu_features;
                }
        }
 }
index 91a5cc5f0d022237cef58a20317442993d428c8e..959c63cf62e484100fd4b907068692b4539cf759 100644 (file)
@@ -436,7 +436,7 @@ void __init setup_system(void)
 
 static u64 slb0_limit(void)
 {
-       if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
+       if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
                return 1UL << SID_SHIFT_1T;
        }
        return 1UL << SID_SHIFT;
index 5b7dd4ea02b57bce76dfb26d0e41e1c650863d46..a242b5d7cbe477c109a78152a344b663444738a1 100644 (file)
@@ -118,7 +118,7 @@ _GLOBAL(__hash_page_4K)
 BEGIN_FTR_SECTION
        cmpdi   r9,0                    /* check segment size */
        bne     3f
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
        /* Calc va and put it in r29 */
        rldicr  r29,r5,28,63-28
        rldicl  r3,r3,0,36
@@ -401,7 +401,7 @@ _GLOBAL(__hash_page_4K)
 BEGIN_FTR_SECTION
        cmpdi   r9,0                    /* check segment size */
        bne     3f
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
        /* Calc va and put it in r29 */
        rldicr  r29,r5,28,63-28         /* r29 = (vsid << 28) */
        rldicl  r3,r3,0,36              /* r3 = (ea & 0x0fffffff) */
@@ -715,7 +715,7 @@ BEGIN_FTR_SECTION
        andi.   r0,r31,_PAGE_NO_CACHE
        /* If so, bail out and refault as a 4k page */
        bne-    ht64_bail_ok
-END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_CI_LARGE_PAGE)
        /* Prepare new PTE value (turn access RW into DIRTY, then
         * add BUSY and ACCESSED)
         */
@@ -736,7 +736,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
 BEGIN_FTR_SECTION
        cmpdi   r9,0                    /* check segment size */
        bne     3f
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
        /* Calc va and put it in r29 */
        rldicr  r29,r5,28,63-28
        rldicl  r3,r3,0,36
index 784a400e078145acaa90ad839d75e9c494162882..c23eef2b81a61f5a1beadc3c6322bcbd00593b43 100644 (file)
@@ -98,8 +98,8 @@ static inline void __tlbiel(unsigned long va, int psize, int ssize)
 
 static inline void tlbie(unsigned long va, int psize, int ssize, int local)
 {
-       unsigned int use_local = local && cpu_has_feature(CPU_FTR_TLBIEL);
-       int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
+       unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL);
+       int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 
        if (use_local)
                use_local = mmu_psize_defs[psize].tlbiel;
@@ -503,7 +503,7 @@ static void native_flush_hash_range(unsigned long number, int local)
                } pte_iterate_hashed_end();
        }
 
-       if (cpu_has_feature(CPU_FTR_TLBIEL) &&
+       if (mmu_has_feature(MMU_FTR_TLBIEL) &&
            mmu_psize_defs[psize].tlbiel && local) {
                asm volatile("ptesync":::"memory");
                for (i = 0; i < number; i++) {
@@ -517,7 +517,7 @@ static void native_flush_hash_range(unsigned long number, int local)
                }
                asm volatile("ptesync":::"memory");
        } else {
-               int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
+               int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 
                if (lock_tlbie)
                        raw_spin_lock(&native_tlbie_lock);
index d95d8f484d2f432109c51eedd36d3c583ff0b98e..26b2872b3d002e431fb3f423f0d7d6878ac049db 100644 (file)
@@ -259,11 +259,11 @@ static int __init htab_dt_scan_seg_sizes(unsigned long node,
        for (; size >= 4; size -= 4, ++prop) {
                if (prop[0] == 40) {
                        DBG("1T segment support detected\n");
-                       cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
+                       cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
                        return 1;
                }
        }
-       cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
+       cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
        return 0;
 }
 
@@ -289,7 +289,7 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
        if (prop != NULL) {
                DBG("Page sizes from device-tree:\n");
                size /= 4;
-               cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
+               cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
                while(size > 0) {
                        unsigned int shift = prop[0];
                        unsigned int slbenc = prop[1];
@@ -317,7 +317,7 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
                                break;
                        case 0x18:
                                idx = MMU_PAGE_16M;
-                               cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
+                               cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
                                break;
                        case 0x22:
                                idx = MMU_PAGE_16G;
@@ -412,7 +412,7 @@ static void __init htab_init_page_sizes(void)
         * Not in the device-tree, let's fallback on known size
         * list for 16M capable GP & GR
         */
-       if (cpu_has_feature(CPU_FTR_16M_PAGE))
+       if (mmu_has_feature(MMU_FTR_16M_PAGE))
                memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
                       sizeof(mmu_psize_defaults_gp));
  found:
@@ -442,7 +442,7 @@ static void __init htab_init_page_sizes(void)
                mmu_vmalloc_psize = MMU_PAGE_64K;
                if (mmu_linear_psize == MMU_PAGE_4K)
                        mmu_linear_psize = MMU_PAGE_64K;
-               if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
+               if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
                        /*
                         * Don't use 64k pages for ioremap on pSeries, since
                         * that would stop us accessing the HEA ethernet.
@@ -608,7 +608,7 @@ static void __init htab_initialize(void)
        /* Initialize page sizes */
        htab_init_page_sizes();
 
-       if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
+       if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
                mmu_kernel_ssize = MMU_SEGSIZE_1T;
                mmu_highuser_ssize = MMU_SEGSIZE_1T;
                printk(KERN_INFO "Using 1TB segments\n");
@@ -749,7 +749,7 @@ void __init early_init_mmu(void)
 
        /* Initialize stab / SLB management except on iSeries
         */
-       if (cpu_has_feature(CPU_FTR_SLB))
+       if (mmu_has_feature(MMU_FTR_SLB))
                slb_initialize();
        else if (!firmware_has_feature(FW_FEATURE_ISERIES))
                stab_initialize(get_paca()->stab_real);
@@ -766,7 +766,7 @@ void __cpuinit early_init_mmu_secondary(void)
         * in real mode on pSeries and we want a virtual address on
         * iSeries anyway
         */
-       if (cpu_has_feature(CPU_FTR_SLB))
+       if (mmu_has_feature(MMU_FTR_SLB))
                slb_initialize();
        else
                stab_initialize(get_paca()->stab_addr);
index 9bb249c3046e3eb6aae16bdfc4a4dd3972f363f8..0b9a5c1901b9e52a89880f684e9507acb9cc9e09 100644 (file)
@@ -529,7 +529,7 @@ static int __init hugetlbpage_init(void)
 {
        int psize;
 
-       if (!cpu_has_feature(CPU_FTR_16M_PAGE))
+       if (!mmu_has_feature(MMU_FTR_16M_PAGE))
                return -ENODEV;
 
        for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
index 5500712781d4b1e59481de076867901d1f6a2213..e22276cb67a40a4c9290784cf2bf358b88e0646e 100644 (file)
@@ -167,7 +167,7 @@ static inline int esids_match(unsigned long addr1, unsigned long addr2)
        int esid_1t_count;
 
        /* System is not 1T segment size capable. */
-       if (!cpu_has_feature(CPU_FTR_1T_SEGMENT))
+       if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
                return (GET_ESID(addr1) == GET_ESID(addr2));
 
        esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) +
@@ -202,7 +202,7 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
         */
        hard_irq_disable();
        offset = get_paca()->slb_cache_ptr;
-       if (!cpu_has_feature(CPU_FTR_NO_SLBIE_B) &&
+       if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
            offset <= SLB_CACHE_ENTRIES) {
                int i;
                asm volatile("isync" : : : "memory");
index 95ce355816966b36ccca9b3b4fbb4a956c60214d..ef653dc95b6594a2f4883ab46fc4a0f07f4c4e3b 100644 (file)
@@ -58,7 +58,7 @@ _GLOBAL(slb_miss_kernel_load_linear)
        li      r11,0
 BEGIN_FTR_SECTION
        b       slb_finish_load
-END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
        b       slb_finish_load_1T
 
 1:
@@ -87,7 +87,7 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
 6:
 BEGIN_FTR_SECTION
        b       slb_finish_load
-END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
        b       slb_finish_load_1T
 
 0:     /* user address: proto-VSID = context << 15 | ESID. First check
@@ -138,11 +138,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
        ld      r9,PACACONTEXTID(r13)
 BEGIN_FTR_SECTION
        cmpldi  r10,0x1000
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
        rldimi  r10,r9,USER_ESID_BITS,0
 BEGIN_FTR_SECTION
        bge     slb_finish_load_1T
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
        b       slb_finish_load
 
 8:     /* invalid EA */
index 446a01842a73eff71046e558bd71ea37677ce254..41e31642a86ad900853ed03dfdf3dc556db71a22 100644 (file)
@@ -243,7 +243,7 @@ void __init stabs_alloc(void)
 {
        int cpu;
 
-       if (cpu_has_feature(CPU_FTR_SLB))
+       if (mmu_has_feature(MMU_FTR_SLB))
                return;
 
        for_each_possible_cpu(cpu) {
index 32a56c6dfa72b03c1e5c51b3b5680e92f1315c6d..a67984c049541c5326064a2d2f02b53b3c9f5adf 100644 (file)
@@ -31,6 +31,7 @@
 #include <asm/thread_info.h>
 #include <asm/ptrace.h>
 #include <asm/cputable.h>
+#include <asm/mmu.h>
 
 #include "exception.h"
 
@@ -157,7 +158,7 @@ BEGIN_FTR_SECTION
 FTR_SECTION_ELSE
        EXCEPTION_PROLOG_1(PACA_EXGEN)
        EXCEPTION_PROLOG_ISERIES_1
-ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
+ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_SLB)
        b       data_access_common
 
 .do_stab_bolted_iSeries:
index 2946ae10fbfdba2ea2eb2cc1e730eedf1cc4ad8b..81cb8d2c4132f2f17ce72ab735a36fe40cce8491 100644 (file)
@@ -249,7 +249,7 @@ static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array,
        unsigned long i;
        unsigned long mem_blocks = 0;
 
-       if (cpu_has_feature(CPU_FTR_SLB))
+       if (mmu_has_feature(MMU_FTR_SLB))
                mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array,
                                max_entries);
        else
@@ -634,7 +634,7 @@ static int __init iseries_probe(void)
 
        hpte_init_iSeries();
        /* iSeries does not support 16M pages */
-       cur_cpu_spec->cpu_features &= ~CPU_FTR_16M_PAGE;
+       cur_cpu_spec->mmu_features &= ~MMU_FTR_16M_PAGE;
 
        return 1;
 }
index ca5d5898d3201f56a8c2dc1f86f0a52c2bf054ac..6f0ed3aac77f1562b2dc0a72c4263db82ec096a1 100644 (file)
@@ -573,7 +573,7 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
        unsigned long i, pix, rc;
        unsigned long flags = 0;
        struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
-       int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
+       int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
        unsigned long param[9];
        unsigned long va;
        unsigned long hash, index, shift, hidx, slot;
index ef9756ee284e08d345540b459559830f233f5564..60593ad861e803938956b352135c2028ea93de08 100644 (file)
@@ -2663,7 +2663,7 @@ static void dump_stab(void)
 
 void dump_segments(void)
 {
-       if (cpu_has_feature(CPU_FTR_SLB))
+       if (mmu_has_feature(MMU_FTR_SLB))
                dump_slb();
        else
                dump_stab();