added a default isDef arg to SetMachineOperand method - Ruchira

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index d3e468cc2ebba1124a451451a409dfb7edd59055..d09813272de0ea834c2b9a92636e3e85028bb83b 100644 (file)
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -42,27 +42,30 @@ MachineInstr::MachineInstr(MachineOpCode _opCode,
 void
 MachineInstr::SetMachineOperand(unsigned int i,
                                MachineOperand::MachineOperandType operandType,
-                               Value* _val)
+                               Value* _val, bool isdef=false)
 {
   assert(i < operands.size());
   operands[i].Initialize(operandType, _val);
+  operands[i].isDef = isdef;
 }
 
 void
 MachineInstr::SetMachineOperand(unsigned int i,
                                MachineOperand::MachineOperandType operandType,
-                               int64_t intValue)
+                               int64_t intValue, bool isdef=false)
 {
   assert(i < operands.size());
   operands[i].InitializeConst(operandType, intValue);
+  operands[i].isDef = isdef;
 }
 
 void
 MachineInstr::SetMachineOperand(unsigned int i,
-                               unsigned int regNum)
+                               unsigned int regNum, bool isdef=false)
 {
   assert(i < operands.size());
   operands[i].InitializeReg(regNum);
+  operands[i].isDef = isdef;
 }
 
 void