R600: Remove unecessary VREG alignment.

Unlike SGPRs VGPRs doesn't need to be aligned.

Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170593 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td
index e52311ab8a9d02e34fe5621cc8d2d0ecec487ec8..c3f136191a68cd3d99bad970a3bdb59645f1d5de 100644 (file)
--- a/lib/Target/R600/SIRegisterInfo.td
+++ b/lib/Target/R600/SIRegisterInfo.td
@@ -105,15 +105,15 @@ def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
 
 // VGPR 64-bit registers
 def VGPR_64 : RegisterTuples<[low, high],
-                             [(add (decimate VGPR_32, 2)),
-                              (add (decimate (rotl VGPR_32, 1), 2))]>;
+                             [(add VGPR_32),
+                              (add (rotl VGPR_32, 1))]>;
 
 // VGPR 128-bit registers
 def VGPR_128 : RegisterTuples<[sel_x, sel_y, sel_z, sel_w],
-                              [(add (decimate VGPR_32, 4)),
-                               (add (decimate (rotl VGPR_32, 1), 4)),
-                               (add (decimate (rotl VGPR_32, 2), 4)),
-                               (add (decimate (rotl VGPR_32, 3), 4))]>;
+                              [(add VGPR_32),
+                               (add (rotl VGPR_32, 1)),
+                               (add (rotl VGPR_32, 2)),
+                               (add (rotl VGPR_32, 3))]>;
 
 // Register class for all scalar registers (SGPRs + Special Registers)
 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,