reset-names = "otg_ahb", "otg_phy", "otg_controller";
/* 0 - Normal, 1 - Force Host, 2 - Force Device */
rockchip,usb-mode = <0>;
+ assigned-clocks = <&cru SCLK_USBPHY480M>;
+ assigned-clock-parents = <&usbphy0>;
status = "okay";
};
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
- <&cru SCLK_32K>,
+ <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
<&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
<&cru PLL_CPLL>, <&cru PLL_GPLL>,
<&cru PLL_NPLL>, <&cru PLL_MPLL>,
<&cru ACLK_BUS>, <&cru ACLK_PERI0>,
<&cru ACLK_PERI1>;
assigned-clock-rates =
- <0>,
+ <0>, <0>,
<0>, <0>,
<750000000>, <576000000>,
<594000000>, <594000000>,
<288000000>, <288000000>,
<144000000>;
assigned-clock-parents =
- <&cru SCLK_32K_INTR>,
+ <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
<&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
};