Typos

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75991 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index d1bd2d647773e2b2111499b751addca77cd283b7..fb0c5dc42d37146be343a8af6141548f1eda87ff 100644 (file)
--- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -312,7 +312,7 @@ bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N,
                                            SystemZRRIAddressMode &AM) {
   // Is the base register already occupied?
   if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) {
-    // If so, check to see if the scale register is set.
+    // If so, check to see if the index register is set.
     if (AM.IndexReg.getNode() == 0 && !AM.isRI) {
       AM.IndexReg = N;
       return false;
@@ -439,7 +439,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI(SDValue Op, SDValue& Addr,
 /// index register plus an unsigned 12-bit displacement [base + idx + imm].
 bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr,
                                 SDValue &Base, SDValue &Disp, SDValue &Index) {
-  SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
+  SystemZRRIAddressMode AM20, AM12;
   bool Done = false;
 
   if (!Addr.hasOneUse()) {