change the addressing mode of the str instruction to reg+imm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29571 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 5437c1dda1059aeac6a16865bc871d69fc7ef72f..4384c2889662a51aa05000c54aceb7bfaf042227 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -22,6 +22,10 @@ ARMInstrInfo::ARMInstrInfo()
   : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) {
 }
 
+const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
+  return &ARM::IntRegsRegClass;
+}
+
 /// Return true if the instruction is a register to register move and
 /// leave the source and dest operands in the passed parameters.
 ///

diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h
index e75a71d0e2632b1cc75937e9cedc3b3ec98bc0b0..6318caa8db05955951729067cb124c9adac92cb1 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.h
+++ b/lib/Target/ARM/ARMInstrInfo.h
@@ -31,6 +31,10 @@ public:
   ///
   virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
 
+  /// getPointerRegClass - Return the register class to use to hold pointers.
+  /// This is used for addressing modes.
+  virtual const TargetRegisterClass *getPointerRegClass() const;
+
   /// Return true if the instruction is a register to register move and
   /// leave the source and dest operands in the passed parameters.
   ///

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 5ba4deba2e0979fe26801c2a7f091da3ad5c41c7..9dc596ab462bc38e64525d592f9edcefc891faa3 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -67,9 +67,9 @@ def ldr   : InstARM<(ops IntRegs:$dst, memri:$addr),
                      "ldr $dst, $addr",
                      [(set IntRegs:$dst, (load iaddr:$addr))]>;
 
-def str  : InstARM<(ops IntRegs:$src, IntRegs:$addr),
-                    "str $src, [$addr]",
-                    [(store IntRegs:$src, IntRegs:$addr)]>;
+def str  : InstARM<(ops IntRegs:$src, memri:$addr),
+                    "str $src, $addr",
+                    [(store IntRegs:$src, iaddr:$addr)]>;
 
 def movrr   : InstARM<(ops IntRegs:$dst, IntRegs:$src),
                        "mov $dst, $src", []>;

diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 719ce321e0ad39651691a2e6b9d36106dcf410f9..67d0b7c801aa22bbe1afc2c93ce6b63d7d687769 100644 (file)
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -135,10 +135,8 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
 
   //sub sp, sp, #NumBytes
   BuildMI(MBB, MBBI, ARM::subri, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
-  //add ip, sp, #NumBytes - 4
-  BuildMI(MBB, MBBI, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(NumBytes - 4);
-  //str lr, [ip]
-  BuildMI(MBB, MBBI, ARM::str, 1, ARM::R14).addReg(ARM::R12);
+  //str lr, [sp, #NumBytes - 4]
+  BuildMI(MBB, MBBI, ARM::str, 2, ARM::R14).addImm(NumBytes - 4).addReg(ARM::R13);
 }
 
 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,