Add dwarf register numbering to register data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.td b/lib/Target/Alpha/AlphaRegisterInfo.td
index febf6fe2ff55952fa98322f5f5ce6c6386cae24e..f6cea9ee4b8e3a71137a885a1acbeed8df385440 100644 (file)
--- a/lib/Target/Alpha/AlphaRegisterInfo.td
+++ b/lib/Target/Alpha/AlphaRegisterInfo.td
@@ -35,40 +35,72 @@ class FPR<bits<5> num, string n> : AlphaReg<n> {
 //#define SP    $30
 
 // General-purpose registers
-def R0  : GPR< 0,  "$0">;  def R1  : GPR< 1,  "$1">;
-def R2  : GPR< 2,  "$2">;  def R3  : GPR< 3,  "$3">;
-def R4  : GPR< 4,  "$4">;  def R5  : GPR< 5,  "$5">;
-def R6  : GPR< 6,  "$6">;  def R7  : GPR< 7,  "$7">;
-def R8  : GPR< 8,  "$8">;  def R9  : GPR< 9,  "$9">;
-def R10 : GPR<10, "$10">;  def R11 : GPR<11, "$11">;
-def R12 : GPR<12, "$12">;  def R13 : GPR<13, "$13">;
-def R14 : GPR<14, "$14">;  def R15 : GPR<15, "$15">;
-def R16 : GPR<16, "$16">;  def R17 : GPR<17, "$17">;
-def R18 : GPR<18, "$18">;  def R19 : GPR<19, "$19">;
-def R20 : GPR<20, "$20">;  def R21 : GPR<21, "$21">;
-def R22 : GPR<22, "$22">;  def R23 : GPR<23, "$23">;
-def R24 : GPR<24, "$24">;  def R25 : GPR<25, "$25">;
-def R26 : GPR<26, "$26">;  def R27 : GPR<27, "$27">;
-def R28 : GPR<28, "$28">;  def R29 : GPR<29, "$29">;
-def R30 : GPR<30, "$30">;  def R31 : GPR<31, "$31">;
+def R0  : GPR< 0,  "$0">, DwarfRegNum<0>;
+def R1  : GPR< 1,  "$1">, DwarfRegNum<1>;
+def R2  : GPR< 2,  "$2">, DwarfRegNum<2>;
+def R3  : GPR< 3,  "$3">, DwarfRegNum<3>;
+def R4  : GPR< 4,  "$4">, DwarfRegNum<4>;
+def R5  : GPR< 5,  "$5">, DwarfRegNum<5>;
+def R6  : GPR< 6,  "$6">, DwarfRegNum<6>;
+def R7  : GPR< 7,  "$7">, DwarfRegNum<7>;
+def R8  : GPR< 8,  "$8">, DwarfRegNum<8>;
+def R9  : GPR< 9,  "$9">, DwarfRegNum<9>;
+def R10 : GPR<10, "$10">, DwarfRegNum<10>;
+def R11 : GPR<11, "$11">, DwarfRegNum<11>;
+def R12 : GPR<12, "$12">, DwarfRegNum<12>;
+def R13 : GPR<13, "$13">, DwarfRegNum<13>;
+def R14 : GPR<14, "$14">, DwarfRegNum<14>;
+def R15 : GPR<15, "$15">, DwarfRegNum<15>;
+def R16 : GPR<16, "$16">, DwarfRegNum<16>;
+def R17 : GPR<17, "$17">, DwarfRegNum<17>;
+def R18 : GPR<18, "$18">, DwarfRegNum<18>;
+def R19 : GPR<19, "$19">, DwarfRegNum<19>;
+def R20 : GPR<20, "$20">, DwarfRegNum<20>;
+def R21 : GPR<21, "$21">, DwarfRegNum<21>;
+def R22 : GPR<22, "$22">, DwarfRegNum<22>;
+def R23 : GPR<23, "$23">, DwarfRegNum<23>;
+def R24 : GPR<24, "$24">, DwarfRegNum<24>;
+def R25 : GPR<25, "$25">, DwarfRegNum<25>;
+def R26 : GPR<26, "$26">, DwarfRegNum<26>;
+def R27 : GPR<27, "$27">, DwarfRegNum<27>;
+def R28 : GPR<28, "$28">, DwarfRegNum<28>;
+def R29 : GPR<29, "$29">, DwarfRegNum<29>;
+def R30 : GPR<30, "$30">, DwarfRegNum<30>;
+def R31 : GPR<31, "$31">, DwarfRegNum<31>;
 
 // Floating-point registers
-def F0  : FPR< 0,  "$f0">;  def F1  : FPR< 1,  "$f1">;
-def F2  : FPR< 2,  "$f2">;  def F3  : FPR< 3,  "$f3">;
-def F4  : FPR< 4,  "$f4">;  def F5  : FPR< 5,  "$f5">;
-def F6  : FPR< 6,  "$f6">;  def F7  : FPR< 7,  "$f7">;
-def F8  : FPR< 8,  "$f8">;  def F9  : FPR< 9,  "$f9">;
-def F10 : FPR<10, "$f10">;  def F11 : FPR<11, "$f11">;
-def F12 : FPR<12, "$f12">;  def F13 : FPR<13, "$f13">;
-def F14 : FPR<14, "$f14">;  def F15 : FPR<15, "$f15">;
-def F16 : FPR<16, "$f16">;  def F17 : FPR<17, "$f17">;
-def F18 : FPR<18, "$f18">;  def F19 : FPR<19, "$f19">;
-def F20 : FPR<20, "$f20">;  def F21 : FPR<21, "$f21">;
-def F22 : FPR<22, "$f22">;  def F23 : FPR<23, "$f23">;
-def F24 : FPR<24, "$f24">;  def F25 : FPR<25, "$f25">;
-def F26 : FPR<26, "$f26">;  def F27 : FPR<27, "$f27">;
-def F28 : FPR<28, "$f28">;  def F29 : FPR<29, "$f29">;
-def F30 : FPR<30, "$f30">;  def F31 : FPR<31, "$f31">;
+def F0  : FPR< 0,  "$f0">, DwarfRegNum<33>;
+def F1  : FPR< 1,  "$f1">, DwarfRegNum<34>;
+def F2  : FPR< 2,  "$f2">, DwarfRegNum<35>;
+def F3  : FPR< 3,  "$f3">, DwarfRegNum<36>;
+def F4  : FPR< 4,  "$f4">, DwarfRegNum<37>;
+def F5  : FPR< 5,  "$f5">, DwarfRegNum<38>;
+def F6  : FPR< 6,  "$f6">, DwarfRegNum<39>;
+def F7  : FPR< 7,  "$f7">, DwarfRegNum<40>;
+def F8  : FPR< 8,  "$f8">, DwarfRegNum<41>;
+def F9  : FPR< 9,  "$f9">, DwarfRegNum<42>;
+def F10 : FPR<10, "$f10">, DwarfRegNum<43>;
+def F11 : FPR<11, "$f11">, DwarfRegNum<44>;
+def F12 : FPR<12, "$f12">, DwarfRegNum<45>;
+def F13 : FPR<13, "$f13">, DwarfRegNum<46>;
+def F14 : FPR<14, "$f14">, DwarfRegNum<47>;
+def F15 : FPR<15, "$f15">, DwarfRegNum<48>;
+def F16 : FPR<16, "$f16">, DwarfRegNum<49>;
+def F17 : FPR<17, "$f17">, DwarfRegNum<50>;
+def F18 : FPR<18, "$f18">, DwarfRegNum<51>;
+def F19 : FPR<19, "$f19">, DwarfRegNum<52>;
+def F20 : FPR<20, "$f20">, DwarfRegNum<53>;
+def F21 : FPR<21, "$f21">, DwarfRegNum<54>;
+def F22 : FPR<22, "$f22">, DwarfRegNum<55>;
+def F23 : FPR<23, "$f23">, DwarfRegNum<56>;
+def F24 : FPR<24, "$f24">, DwarfRegNum<57>;
+def F25 : FPR<25, "$f25">, DwarfRegNum<58>;
+def F26 : FPR<26, "$f26">, DwarfRegNum<59>;
+def F27 : FPR<27, "$f27">, DwarfRegNum<60>;
+def F28 : FPR<28, "$f28">, DwarfRegNum<61>;
+def F29 : FPR<29, "$f29">, DwarfRegNum<62>;
+def F30 : FPR<30, "$f30">, DwarfRegNum<63>;
+def F31 : FPR<31, "$f31">, DwarfRegNum<64>;
 
   // //#define FP    $15
   // //#define RA    $26
@@ -137,4 +169,3 @@ def F8RC : RegisterClass<"Alpha", [f64], 64, [F0, F1,
     }
   }];
 }
-

diff --git a/lib/Target/IA64/IA64RegisterInfo.td b/lib/Target/IA64/IA64RegisterInfo.td
index 4447113607a0752064735354dfb7a200d4780c9a..bb71ec6b3f539c8726585a368e964a631f3237f1 100644 (file)
--- a/lib/Target/IA64/IA64RegisterInfo.td
+++ b/lib/Target/IA64/IA64RegisterInfo.td
@@ -37,187 +37,352 @@ class PR<bits<6> num, string n> : IA64Register<n> {
 }
 
 /* general registers */
-def r0 : GR< 0, "r0">; def r1 : GR< 1, "r1">;
-def r2 : GR< 2, "r2">; def r3 : GR< 3, "r3">;
-def r4 : GR< 4, "r4">; def r5 : GR< 5, "r5">;
-def r6 : GR< 6, "r6">; def r7 : GR< 7, "r7">;
-def r8 : GR< 8, "r8">; def r9 : GR< 9, "r9">;
-def r10 : GR< 10, "r10">;      def r11 : GR< 11, "r11">;
-def r12 : GR< 12, "r12">;      def r13 : GR< 13, "r13">;
-def r14 : GR< 14, "r14">;      def r15 : GR< 15, "r15">;
-def r16 : GR< 16, "r16">;      def r17 : GR< 17, "r17">;
-def r18 : GR< 18, "r18">;      def r19 : GR< 19, "r19">;
-def r20 : GR< 20, "r20">;      def r21 : GR< 21, "r21">;
-def r22 : GR< 22, "r22">;      def r23 : GR< 23, "r23">;
-def r24 : GR< 24, "r24">;      def r25 : GR< 25, "r25">;
-def r26 : GR< 26, "r26">;      def r27 : GR< 27, "r27">;
-def r28 : GR< 28, "r28">;      def r29 : GR< 29, "r29">;
-def r30 : GR< 30, "r30">;      def r31 : GR< 31, "r31">;
-def r32 : GR< 32, "r32">;      def r33 : GR< 33, "r33">;
-def r34 : GR< 34, "r34">;      def r35 : GR< 35, "r35">;
-def r36 : GR< 36, "r36">;      def r37 : GR< 37, "r37">;
-def r38 : GR< 38, "r38">;      def r39 : GR< 39, "r39">;
-def r40 : GR< 40, "r40">;      def r41 : GR< 41, "r41">;
-def r42 : GR< 42, "r42">;      def r43 : GR< 43, "r43">;
-def r44 : GR< 44, "r44">;      def r45 : GR< 45, "r45">;
-def r46 : GR< 46, "r46">;      def r47 : GR< 47, "r47">;
-def r48 : GR< 48, "r48">;      def r49 : GR< 49, "r49">;
-def r50 : GR< 50, "r50">;      def r51 : GR< 51, "r51">;
-def r52 : GR< 52, "r52">;      def r53 : GR< 53, "r53">;
-def r54 : GR< 54, "r54">;      def r55 : GR< 55, "r55">;
-def r56 : GR< 56, "r56">;      def r57 : GR< 57, "r57">;
-def r58 : GR< 58, "r58">;      def r59 : GR< 59, "r59">;
-def r60 : GR< 60, "r60">;      def r61 : GR< 61, "r61">;
-def r62 : GR< 62, "r62">;      def r63 : GR< 63, "r63">;
-def r64 : GR< 64, "r64">;      def r65 : GR< 65, "r65">;
-def r66 : GR< 66, "r66">;      def r67 : GR< 67, "r67">;
-def r68 : GR< 68, "r68">;      def r69 : GR< 69, "r69">;
-def r70 : GR< 70, "r70">;      def r71 : GR< 71, "r71">;
-def r72 : GR< 72, "r72">;      def r73 : GR< 73, "r73">;
-def r74 : GR< 74, "r74">;      def r75 : GR< 75, "r75">;
-def r76 : GR< 76, "r76">;      def r77 : GR< 77, "r77">;
-def r78 : GR< 78, "r78">;      def r79 : GR< 79, "r79">;
-def r80 : GR< 80, "r80">;      def r81 : GR< 81, "r81">;
-def r82 : GR< 82, "r82">;      def r83 : GR< 83, "r83">;
-def r84 : GR< 84, "r84">;      def r85 : GR< 85, "r85">;
-def r86 : GR< 86, "r86">;      def r87 : GR< 87, "r87">;
-def r88 : GR< 88, "r88">;      def r89 : GR< 89, "r89">;
-def r90 : GR< 90, "r90">;      def r91 : GR< 91, "r91">;
-def r92 : GR< 92, "r92">;      def r93 : GR< 93, "r93">;
-def r94 : GR< 94, "r94">;      def r95 : GR< 95, "r95">;
-def r96 : GR< 96, "r96">;      def r97 : GR< 97, "r97">;
-def r98 : GR< 98, "r98">;      def r99 : GR< 99, "r99">;
-def r100 : GR< 100, "r100">;   def r101 : GR< 101, "r101">;
-def r102 : GR< 102, "r102">;   def r103 : GR< 103, "r103">;
-def r104 : GR< 104, "r104">;   def r105 : GR< 105, "r105">;
-def r106 : GR< 106, "r106">;   def r107 : GR< 107, "r107">;
-def r108 : GR< 108, "r108">;   def r109 : GR< 109, "r109">;
-def r110 : GR< 110, "r110">;   def r111 : GR< 111, "r111">;
-def r112 : GR< 112, "r112">;   def r113 : GR< 113, "r113">;
-def r114 : GR< 114, "r114">;   def r115 : GR< 115, "r115">;
-def r116 : GR< 116, "r116">;   def r117 : GR< 117, "r117">;
-def r118 : GR< 118, "r118">;   def r119 : GR< 119, "r119">;
-def r120 : GR< 120, "r120">;   def r121 : GR< 121, "r121">;
-def r122 : GR< 122, "r122">;   def r123 : GR< 123, "r123">;
-def r124 : GR< 124, "r124">;   def r125 : GR< 125, "r125">;
-def r126 : GR< 126, "r126">;   def r127 : GR< 127, "r127">;
+def r0 : GR< 0, "r0">, DwarfRegNum<0>;
+def r1 : GR< 1, "r1">, DwarfRegNum<1>;
+def r2 : GR< 2, "r2">, DwarfRegNum<2>;
+def r3 : GR< 3, "r3">, DwarfRegNum<3>;
+def r4 : GR< 4, "r4">, DwarfRegNum<4>;
+def r5 : GR< 5, "r5">, DwarfRegNum<5>;
+def r6 : GR< 6, "r6">, DwarfRegNum<6>;
+def r7 : GR< 7, "r7">, DwarfRegNum<7>;
+def r8 : GR< 8, "r8">, DwarfRegNum<8>;
+def r9 : GR< 9, "r9">, DwarfRegNum<9>;
+def r10 : GR< 10, "r10">, DwarfRegNum<10>;
+def r11 : GR< 11, "r11">, DwarfRegNum<11>;
+def r12 : GR< 12, "r12">, DwarfRegNum<12>;
+def r13 : GR< 13, "r13">, DwarfRegNum<13>;
+def r14 : GR< 14, "r14">, DwarfRegNum<14>;
+def r15 : GR< 15, "r15">, DwarfRegNum<15>;
+def r16 : GR< 16, "r16">, DwarfRegNum<16>;
+def r17 : GR< 17, "r17">, DwarfRegNum<17>;
+def r18 : GR< 18, "r18">, DwarfRegNum<18>;
+def r19 : GR< 19, "r19">, DwarfRegNum<19>;
+def r20 : GR< 20, "r20">, DwarfRegNum<20>;
+def r21 : GR< 21, "r21">, DwarfRegNum<21>;
+def r22 : GR< 22, "r22">, DwarfRegNum<22>;
+def r23 : GR< 23, "r23">, DwarfRegNum<23>;
+def r24 : GR< 24, "r24">, DwarfRegNum<24>;
+def r25 : GR< 25, "r25">, DwarfRegNum<25>;
+def r26 : GR< 26, "r26">, DwarfRegNum<26>;
+def r27 : GR< 27, "r27">, DwarfRegNum<27>;
+def r28 : GR< 28, "r28">, DwarfRegNum<28>;
+def r29 : GR< 29, "r29">, DwarfRegNum<29>;
+def r30 : GR< 30, "r30">, DwarfRegNum<30>;
+def r31 : GR< 31, "r31">, DwarfRegNum<31>;
+def r32 : GR< 32, "r32">, DwarfRegNum<32>;
+def r33 : GR< 33, "r33">, DwarfRegNum<33>;
+def r34 : GR< 34, "r34">, DwarfRegNum<34>;
+def r35 : GR< 35, "r35">, DwarfRegNum<35>;
+def r36 : GR< 36, "r36">, DwarfRegNum<36>;
+def r37 : GR< 37, "r37">, DwarfRegNum<37>;
+def r38 : GR< 38, "r38">, DwarfRegNum<38>;
+def r39 : GR< 39, "r39">, DwarfRegNum<39>;
+def r40 : GR< 40, "r40">, DwarfRegNum<40>;
+def r41 : GR< 41, "r41">, DwarfRegNum<41>;
+def r42 : GR< 42, "r42">, DwarfRegNum<42>;
+def r43 : GR< 43, "r43">, DwarfRegNum<43>;
+def r44 : GR< 44, "r44">, DwarfRegNum<44>;
+def r45 : GR< 45, "r45">, DwarfRegNum<45>;
+def r46 : GR< 46, "r46">, DwarfRegNum<46>;
+def r47 : GR< 47, "r47">, DwarfRegNum<47>;
+def r48 : GR< 48, "r48">, DwarfRegNum<48>;
+def r49 : GR< 49, "r49">, DwarfRegNum<49>;
+def r50 : GR< 50, "r50">, DwarfRegNum<50>;
+def r51 : GR< 51, "r51">, DwarfRegNum<51>;
+def r52 : GR< 52, "r52">, DwarfRegNum<52>;
+def r53 : GR< 53, "r53">, DwarfRegNum<53>;
+def r54 : GR< 54, "r54">, DwarfRegNum<54>;
+def r55 : GR< 55, "r55">, DwarfRegNum<55>;
+def r56 : GR< 56, "r56">, DwarfRegNum<56>;
+def r57 : GR< 57, "r57">, DwarfRegNum<57>;
+def r58 : GR< 58, "r58">, DwarfRegNum<58>;
+def r59 : GR< 59, "r59">, DwarfRegNum<59>;
+def r60 : GR< 60, "r60">, DwarfRegNum<60>;
+def r61 : GR< 61, "r61">, DwarfRegNum<61>;
+def r62 : GR< 62, "r62">, DwarfRegNum<62>;
+def r63 : GR< 63, "r63">, DwarfRegNum<63>;
+def r64 : GR< 64, "r64">, DwarfRegNum<64>;
+def r65 : GR< 65, "r65">, DwarfRegNum<65>;
+def r66 : GR< 66, "r66">, DwarfRegNum<66>;
+def r67 : GR< 67, "r67">, DwarfRegNum<67>;
+def r68 : GR< 68, "r68">, DwarfRegNum<68>;
+def r69 : GR< 69, "r69">, DwarfRegNum<69>;
+def r70 : GR< 70, "r70">, DwarfRegNum<70>;
+def r71 : GR< 71, "r71">, DwarfRegNum<71>;
+def r72 : GR< 72, "r72">, DwarfRegNum<72>;
+def r73 : GR< 73, "r73">, DwarfRegNum<73>;
+def r74 : GR< 74, "r74">, DwarfRegNum<74>;
+def r75 : GR< 75, "r75">, DwarfRegNum<75>;
+def r76 : GR< 76, "r76">, DwarfRegNum<76>;
+def r77 : GR< 77, "r77">, DwarfRegNum<77>;
+def r78 : GR< 78, "r78">, DwarfRegNum<78>;
+def r79 : GR< 79, "r79">, DwarfRegNum<79>;
+def r80 : GR< 80, "r80">, DwarfRegNum<80>;
+def r81 : GR< 81, "r81">, DwarfRegNum<81>;
+def r82 : GR< 82, "r82">, DwarfRegNum<82>;
+def r83 : GR< 83, "r83">, DwarfRegNum<83>;
+def r84 : GR< 84, "r84">, DwarfRegNum<84>;
+def r85 : GR< 85, "r85">, DwarfRegNum<85>;
+def r86 : GR< 86, "r86">, DwarfRegNum<86>;
+def r87 : GR< 87, "r87">, DwarfRegNum<87>;
+def r88 : GR< 88, "r88">, DwarfRegNum<88>;
+def r89 : GR< 89, "r89">, DwarfRegNum<89>;
+def r90 : GR< 90, "r90">, DwarfRegNum<90>;
+def r91 : GR< 91, "r91">, DwarfRegNum<91>;
+def r92 : GR< 92, "r92">, DwarfRegNum<92>;
+def r93 : GR< 93, "r93">, DwarfRegNum<93>;
+def r94 : GR< 94, "r94">, DwarfRegNum<94>;
+def r95 : GR< 95, "r95">, DwarfRegNum<95>;
+def r96 : GR< 96, "r96">, DwarfRegNum<96>;
+def r97 : GR< 97, "r97">, DwarfRegNum<97>;
+def r98 : GR< 98, "r98">, DwarfRegNum<98>;
+def r99 : GR< 99, "r99">, DwarfRegNum<99>;
+def r100 : GR< 100, "r100">, DwarfRegNum<100>;
+def r101 : GR< 101, "r101">, DwarfRegNum<101>;
+def r102 : GR< 102, "r102">, DwarfRegNum<102>;
+def r103 : GR< 103, "r103">, DwarfRegNum<103>;
+def r104 : GR< 104, "r104">, DwarfRegNum<104>;
+def r105 : GR< 105, "r105">, DwarfRegNum<105>;
+def r106 : GR< 106, "r106">, DwarfRegNum<106>;
+def r107 : GR< 107, "r107">, DwarfRegNum<107>;
+def r108 : GR< 108, "r108">, DwarfRegNum<108>;
+def r109 : GR< 109, "r109">, DwarfRegNum<109>;
+def r110 : GR< 110, "r110">, DwarfRegNum<110>;
+def r111 : GR< 111, "r111">, DwarfRegNum<111>;
+def r112 : GR< 112, "r112">, DwarfRegNum<112>;
+def r113 : GR< 113, "r113">, DwarfRegNum<113>;
+def r114 : GR< 114, "r114">, DwarfRegNum<114>;
+def r115 : GR< 115, "r115">, DwarfRegNum<115>;
+def r116 : GR< 116, "r116">, DwarfRegNum<116>;
+def r117 : GR< 117, "r117">, DwarfRegNum<117>;
+def r118 : GR< 118, "r118">, DwarfRegNum<118>;
+def r119 : GR< 119, "r119">, DwarfRegNum<119>;
+def r120 : GR< 120, "r120">, DwarfRegNum<120>;
+def r121 : GR< 121, "r121">, DwarfRegNum<121>;
+def r122 : GR< 122, "r122">, DwarfRegNum<122>;
+def r123 : GR< 123, "r123">, DwarfRegNum<123>;
+def r124 : GR< 124, "r124">, DwarfRegNum<124>;
+def r125 : GR< 125, "r125">, DwarfRegNum<125>;
+def r126 : GR< 126, "r126">, DwarfRegNum<126>;
+def r127 : GR< 127, "r127">, DwarfRegNum<127>;
 
 /* floating-point registers */
-def F0 : FP< 0, "f0">; def F1 : FP< 1, "f1">;
-def F2 : FP< 2, "f2">; def F3 : FP< 3, "f3">;
-def F4 : FP< 4, "f4">; def F5 : FP< 5, "f5">;
-def F6 : FP< 6, "f6">; def F7 : FP< 7, "f7">;
-def F8 : FP< 8, "f8">; def F9 : FP< 9, "f9">;
-def F10 : FP< 10, "f10">;      def F11 : FP< 11, "f11">;
-def F12 : FP< 12, "f12">;      def F13 : FP< 13, "f13">;
-def F14 : FP< 14, "f14">;      def F15 : FP< 15, "f15">;
-def F16 : FP< 16, "f16">;      def F17 : FP< 17, "f17">;
-def F18 : FP< 18, "f18">;      def F19 : FP< 19, "f19">;
-def F20 : FP< 20, "f20">;      def F21 : FP< 21, "f21">;
-def F22 : FP< 22, "f22">;      def F23 : FP< 23, "f23">;
-def F24 : FP< 24, "f24">;      def F25 : FP< 25, "f25">;
-def F26 : FP< 26, "f26">;      def F27 : FP< 27, "f27">;
-def F28 : FP< 28, "f28">;      def F29 : FP< 29, "f29">;
-def F30 : FP< 30, "f30">;      def F31 : FP< 31, "f31">;
-def F32 : FP< 32, "f32">;      def F33 : FP< 33, "f33">;
-def F34 : FP< 34, "f34">;      def F35 : FP< 35, "f35">;
-def F36 : FP< 36, "f36">;      def F37 : FP< 37, "f37">;
-def F38 : FP< 38, "f38">;      def F39 : FP< 39, "f39">;
-def F40 : FP< 40, "f40">;      def F41 : FP< 41, "f41">;
-def F42 : FP< 42, "f42">;      def F43 : FP< 43, "f43">;
-def F44 : FP< 44, "f44">;      def F45 : FP< 45, "f45">;
-def F46 : FP< 46, "f46">;      def F47 : FP< 47, "f47">;
-def F48 : FP< 48, "f48">;      def F49 : FP< 49, "f49">;
-def F50 : FP< 50, "f50">;      def F51 : FP< 51, "f51">;
-def F52 : FP< 52, "f52">;      def F53 : FP< 53, "f53">;
-def F54 : FP< 54, "f54">;      def F55 : FP< 55, "f55">;
-def F56 : FP< 56, "f56">;      def F57 : FP< 57, "f57">;
-def F58 : FP< 58, "f58">;      def F59 : FP< 59, "f59">;
-def F60 : FP< 60, "f60">;      def F61 : FP< 61, "f61">;
-def F62 : FP< 62, "f62">;      def F63 : FP< 63, "f63">;
-def F64 : FP< 64, "f64">;      def F65 : FP< 65, "f65">;
-def F66 : FP< 66, "f66">;      def F67 : FP< 67, "f67">;
-def F68 : FP< 68, "f68">;      def F69 : FP< 69, "f69">;
-def F70 : FP< 70, "f70">;      def F71 : FP< 71, "f71">;
-def F72 : FP< 72, "f72">;      def F73 : FP< 73, "f73">;
-def F74 : FP< 74, "f74">;      def F75 : FP< 75, "f75">;
-def F76 : FP< 76, "f76">;      def F77 : FP< 77, "f77">;
-def F78 : FP< 78, "f78">;      def F79 : FP< 79, "f79">;
-def F80 : FP< 80, "f80">;      def F81 : FP< 81, "f81">;
-def F82 : FP< 82, "f82">;      def F83 : FP< 83, "f83">;
-def F84 : FP< 84, "f84">;      def F85 : FP< 85, "f85">;
-def F86 : FP< 86, "f86">;      def F87 : FP< 87, "f87">;
-def F88 : FP< 88, "f88">;      def F89 : FP< 89, "f89">;
-def F90 : FP< 90, "f90">;      def F91 : FP< 91, "f91">;
-def F92 : FP< 92, "f92">;      def F93 : FP< 93, "f93">;
-def F94 : FP< 94, "f94">;      def F95 : FP< 95, "f95">;
-def F96 : FP< 96, "f96">;      def F97 : FP< 97, "f97">;
-def F98 : FP< 98, "f98">;      def F99 : FP< 99, "f99">;
-def F100 : FP< 100, "f100">;   def F101 : FP< 101, "f101">;
-def F102 : FP< 102, "f102">;   def F103 : FP< 103, "f103">;
-def F104 : FP< 104, "f104">;   def F105 : FP< 105, "f105">;
-def F106 : FP< 106, "f106">;   def F107 : FP< 107, "f107">;
-def F108 : FP< 108, "f108">;   def F109 : FP< 109, "f109">;
-def F110 : FP< 110, "f110">;   def F111 : FP< 111, "f111">;
-def F112 : FP< 112, "f112">;   def F113 : FP< 113, "f113">;
-def F114 : FP< 114, "f114">;   def F115 : FP< 115, "f115">;
-def F116 : FP< 116, "f116">;   def F117 : FP< 117, "f117">;
-def F118 : FP< 118, "f118">;   def F119 : FP< 119, "f119">;
-def F120 : FP< 120, "f120">;   def F121 : FP< 121, "f121">;
-def F122 : FP< 122, "f122">;   def F123 : FP< 123, "f123">;
-def F124 : FP< 124, "f124">;   def F125 : FP< 125, "f125">;
-def F126 : FP< 126, "f126">;   def F127 : FP< 127, "f127">;
+def F0 : FP< 0, "f0">, DwarfRegNum<128>;
+def F1 : FP< 1, "f1">, DwarfRegNum<129>;
+def F2 : FP< 2, "f2">, DwarfRegNum<130>;
+def F3 : FP< 3, "f3">, DwarfRegNum<131>;
+def F4 : FP< 4, "f4">, DwarfRegNum<132>;
+def F5 : FP< 5, "f5">, DwarfRegNum<133>;
+def F6 : FP< 6, "f6">, DwarfRegNum<134>;
+def F7 : FP< 7, "f7">, DwarfRegNum<135>;
+def F8 : FP< 8, "f8">, DwarfRegNum<136>;
+def F9 : FP< 9, "f9">, DwarfRegNum<137>;
+def F10 : FP< 10, "f10">, DwarfRegNum<138>;
+def F11 : FP< 11, "f11">, DwarfRegNum<139>;
+def F12 : FP< 12, "f12">, DwarfRegNum<140>;
+def F13 : FP< 13, "f13">, DwarfRegNum<141>;
+def F14 : FP< 14, "f14">, DwarfRegNum<142>;
+def F15 : FP< 15, "f15">, DwarfRegNum<143>;
+def F16 : FP< 16, "f16">, DwarfRegNum<144>;
+def F17 : FP< 17, "f17">, DwarfRegNum<145>;
+def F18 : FP< 18, "f18">, DwarfRegNum<146>;
+def F19 : FP< 19, "f19">, DwarfRegNum<147>;
+def F20 : FP< 20, "f20">, DwarfRegNum<148>;
+def F21 : FP< 21, "f21">, DwarfRegNum<149>;
+def F22 : FP< 22, "f22">, DwarfRegNum<150>;
+def F23 : FP< 23, "f23">, DwarfRegNum<151>;
+def F24 : FP< 24, "f24">, DwarfRegNum<152>;
+def F25 : FP< 25, "f25">, DwarfRegNum<153>;
+def F26 : FP< 26, "f26">, DwarfRegNum<154>;
+def F27 : FP< 27, "f27">, DwarfRegNum<155>;
+def F28 : FP< 28, "f28">, DwarfRegNum<156>;
+def F29 : FP< 29, "f29">, DwarfRegNum<157>;
+def F30 : FP< 30, "f30">, DwarfRegNum<158>;
+def F31 : FP< 31, "f31">, DwarfRegNum<159>;
+def F32 : FP< 32, "f32">, DwarfRegNum<160>;
+def F33 : FP< 33, "f33">, DwarfRegNum<161>;
+def F34 : FP< 34, "f34">, DwarfRegNum<162>;
+def F35 : FP< 35, "f35">, DwarfRegNum<163>;
+def F36 : FP< 36, "f36">, DwarfRegNum<164>;
+def F37 : FP< 37, "f37">, DwarfRegNum<165>;
+def F38 : FP< 38, "f38">, DwarfRegNum<166>;
+def F39 : FP< 39, "f39">, DwarfRegNum<167>;
+def F40 : FP< 40, "f40">, DwarfRegNum<168>;
+def F41 : FP< 41, "f41">, DwarfRegNum<169>;
+def F42 : FP< 42, "f42">, DwarfRegNum<170>;
+def F43 : FP< 43, "f43">, DwarfRegNum<171>;
+def F44 : FP< 44, "f44">, DwarfRegNum<172>;
+def F45 : FP< 45, "f45">, DwarfRegNum<173>;
+def F46 : FP< 46, "f46">, DwarfRegNum<174>;
+def F47 : FP< 47, "f47">, DwarfRegNum<175>;
+def F48 : FP< 48, "f48">, DwarfRegNum<176>;
+def F49 : FP< 49, "f49">, DwarfRegNum<177>;
+def F50 : FP< 50, "f50">, DwarfRegNum<178>;
+def F51 : FP< 51, "f51">, DwarfRegNum<179>;
+def F52 : FP< 52, "f52">, DwarfRegNum<180>;
+def F53 : FP< 53, "f53">, DwarfRegNum<181>;
+def F54 : FP< 54, "f54">, DwarfRegNum<182>;
+def F55 : FP< 55, "f55">, DwarfRegNum<183>;
+def F56 : FP< 56, "f56">, DwarfRegNum<184>;
+def F57 : FP< 57, "f57">, DwarfRegNum<185>;
+def F58 : FP< 58, "f58">, DwarfRegNum<186>;
+def F59 : FP< 59, "f59">, DwarfRegNum<187>;
+def F60 : FP< 60, "f60">, DwarfRegNum<188>;
+def F61 : FP< 61, "f61">, DwarfRegNum<189>;
+def F62 : FP< 62, "f62">, DwarfRegNum<190>;
+def F63 : FP< 63, "f63">, DwarfRegNum<191>;
+def F64 : FP< 64, "f64">, DwarfRegNum<192>;
+def F65 : FP< 65, "f65">, DwarfRegNum<193>;
+def F66 : FP< 66, "f66">, DwarfRegNum<194>;
+def F67 : FP< 67, "f67">, DwarfRegNum<195>;
+def F68 : FP< 68, "f68">, DwarfRegNum<196>;
+def F69 : FP< 69, "f69">, DwarfRegNum<197>;
+def F70 : FP< 70, "f70">, DwarfRegNum<198>;
+def F71 : FP< 71, "f71">, DwarfRegNum<199>;
+def F72 : FP< 72, "f72">, DwarfRegNum<200>;
+def F73 : FP< 73, "f73">, DwarfRegNum<201>;
+def F74 : FP< 74, "f74">, DwarfRegNum<202>;
+def F75 : FP< 75, "f75">, DwarfRegNum<203>;
+def F76 : FP< 76, "f76">, DwarfRegNum<204>;
+def F77 : FP< 77, "f77">, DwarfRegNum<205>;
+def F78 : FP< 78, "f78">, DwarfRegNum<206>;
+def F79 : FP< 79, "f79">, DwarfRegNum<207>;
+def F80 : FP< 80, "f80">, DwarfRegNum<208>;
+def F81 : FP< 81, "f81">, DwarfRegNum<209>;
+def F82 : FP< 82, "f82">, DwarfRegNum<210>;
+def F83 : FP< 83, "f83">, DwarfRegNum<211>;
+def F84 : FP< 84, "f84">, DwarfRegNum<212>;
+def F85 : FP< 85, "f85">, DwarfRegNum<213>;
+def F86 : FP< 86, "f86">, DwarfRegNum<214>;
+def F87 : FP< 87, "f87">, DwarfRegNum<215>;
+def F88 : FP< 88, "f88">, DwarfRegNum<216>;
+def F89 : FP< 89, "f89">, DwarfRegNum<217>;
+def F90 : FP< 90, "f90">, DwarfRegNum<218>;
+def F91 : FP< 91, "f91">, DwarfRegNum<219>;
+def F92 : FP< 92, "f92">, DwarfRegNum<220>;
+def F93 : FP< 93, "f93">, DwarfRegNum<221>;
+def F94 : FP< 94, "f94">, DwarfRegNum<222>;
+def F95 : FP< 95, "f95">, DwarfRegNum<223>;
+def F96 : FP< 96, "f96">, DwarfRegNum<224>;
+def F97 : FP< 97, "f97">, DwarfRegNum<225>;
+def F98 : FP< 98, "f98">, DwarfRegNum<226>;
+def F99 : FP< 99, "f99">, DwarfRegNum<227>;
+def F100 : FP< 100, "f100">, DwarfRegNum<228>;
+def F101 : FP< 101, "f101">, DwarfRegNum<229>;
+def F102 : FP< 102, "f102">, DwarfRegNum<230>;
+def F103 : FP< 103, "f103">, DwarfRegNum<231>;
+def F104 : FP< 104, "f104">, DwarfRegNum<232>;
+def F105 : FP< 105, "f105">, DwarfRegNum<233>;
+def F106 : FP< 106, "f106">, DwarfRegNum<234>;
+def F107 : FP< 107, "f107">, DwarfRegNum<235>;
+def F108 : FP< 108, "f108">, DwarfRegNum<236>;
+def F109 : FP< 109, "f109">, DwarfRegNum<237>;
+def F110 : FP< 110, "f110">, DwarfRegNum<238>;
+def F111 : FP< 111, "f111">, DwarfRegNum<239>;
+def F112 : FP< 112, "f112">, DwarfRegNum<240>;
+def F113 : FP< 113, "f113">, DwarfRegNum<241>;
+def F114 : FP< 114, "f114">, DwarfRegNum<242>;
+def F115 : FP< 115, "f115">, DwarfRegNum<243>;
+def F116 : FP< 116, "f116">, DwarfRegNum<244>;
+def F117 : FP< 117, "f117">, DwarfRegNum<245>;
+def F118 : FP< 118, "f118">, DwarfRegNum<246>;
+def F119 : FP< 119, "f119">, DwarfRegNum<247>;
+def F120 : FP< 120, "f120">, DwarfRegNum<248>;
+def F121 : FP< 121, "f121">, DwarfRegNum<249>;
+def F122 : FP< 122, "f122">, DwarfRegNum<250>;
+def F123 : FP< 123, "f123">, DwarfRegNum<251>;
+def F124 : FP< 124, "f124">, DwarfRegNum<252>;
+def F125 : FP< 125, "f125">, DwarfRegNum<253>;
+def F126 : FP< 126, "f126">, DwarfRegNum<254>;
+def F127 : FP< 127, "f127">, DwarfRegNum<255>;
 
 /* predicate registers */
-def p0 : PR< 0, "p0">;  def p1 : PR< 1, "p1">;
-def p2 : PR< 2, "p2">;  def p3 : PR< 3, "p3">;
-def p4 : PR< 4, "p4">;  def p5 : PR< 5, "p5">;
-def p6 : PR< 6, "p6">;  def p7 : PR< 7, "p7">;
-def p8 : PR< 8, "p8">;  def p9 : PR< 9, "p9">;
-def p10 : PR< 10, "p10">;       def p11 : PR< 11, "p11">;
-def p12 : PR< 12, "p12">;       def p13 : PR< 13, "p13">;
-def p14 : PR< 14, "p14">;       def p15 : PR< 15, "p15">;
-def p16 : PR< 16, "p16">;       def p17 : PR< 17, "p17">;
-def p18 : PR< 18, "p18">;       def p19 : PR< 19, "p19">;
-def p20 : PR< 20, "p20">;       def p21 : PR< 21, "p21">;
-def p22 : PR< 22, "p22">;       def p23 : PR< 23, "p23">;
-def p24 : PR< 24, "p24">;       def p25 : PR< 25, "p25">;
-def p26 : PR< 26, "p26">;       def p27 : PR< 27, "p27">;
-def p28 : PR< 28, "p28">;       def p29 : PR< 29, "p29">;
-def p30 : PR< 30, "p30">;       def p31 : PR< 31, "p31">;
-def p32 : PR< 32, "p32">;       def p33 : PR< 33, "p33">;
-def p34 : PR< 34, "p34">;       def p35 : PR< 35, "p35">;
-def p36 : PR< 36, "p36">;       def p37 : PR< 37, "p37">;
-def p38 : PR< 38, "p38">;       def p39 : PR< 39, "p39">;
-def p40 : PR< 40, "p40">;       def p41 : PR< 41, "p41">;
-def p42 : PR< 42, "p42">;       def p43 : PR< 43, "p43">;
-def p44 : PR< 44, "p44">;       def p45 : PR< 45, "p45">;
-def p46 : PR< 46, "p46">;       def p47 : PR< 47, "p47">;
-def p48 : PR< 48, "p48">;       def p49 : PR< 49, "p49">;
-def p50 : PR< 50, "p50">;       def p51 : PR< 51, "p51">;
-def p52 : PR< 52, "p52">;       def p53 : PR< 53, "p53">;
-def p54 : PR< 54, "p54">;       def p55 : PR< 55, "p55">;
-def p56 : PR< 56, "p56">;       def p57 : PR< 57, "p57">;
-def p58 : PR< 58, "p58">;       def p59 : PR< 59, "p59">;
-def p60 : PR< 60, "p60">;       def p61 : PR< 61, "p61">;
-def p62 : PR< 62, "p62">;       def p63 : PR< 63, "p63">;
+def p0 : PR< 0, "p0">, DwarfRegNum<256>;
+def p1 : PR< 1, "p1">, DwarfRegNum<257>;
+def p2 : PR< 2, "p2">, DwarfRegNum<258>;
+def p3 : PR< 3, "p3">, DwarfRegNum<259>;
+def p4 : PR< 4, "p4">, DwarfRegNum<260>;
+def p5 : PR< 5, "p5">, DwarfRegNum<261>;
+def p6 : PR< 6, "p6">, DwarfRegNum<262>;
+def p7 : PR< 7, "p7">, DwarfRegNum<263>;
+def p8 : PR< 8, "p8">, DwarfRegNum<264>;
+def p9 : PR< 9, "p9">, DwarfRegNum<265>;
+def p10 : PR< 10, "p10">, DwarfRegNum<266>;
+def p11 : PR< 11, "p11">, DwarfRegNum<267>;
+def p12 : PR< 12, "p12">, DwarfRegNum<268>;
+def p13 : PR< 13, "p13">, DwarfRegNum<269>;
+def p14 : PR< 14, "p14">, DwarfRegNum<270>;
+def p15 : PR< 15, "p15">, DwarfRegNum<271>;
+def p16 : PR< 16, "p16">, DwarfRegNum<272>;
+def p17 : PR< 17, "p17">, DwarfRegNum<273>;
+def p18 : PR< 18, "p18">, DwarfRegNum<274>;
+def p19 : PR< 19, "p19">, DwarfRegNum<275>;
+def p20 : PR< 20, "p20">, DwarfRegNum<276>;
+def p21 : PR< 21, "p21">, DwarfRegNum<277>;
+def p22 : PR< 22, "p22">, DwarfRegNum<278>;
+def p23 : PR< 23, "p23">, DwarfRegNum<279>;
+def p24 : PR< 24, "p24">, DwarfRegNum<280>;
+def p25 : PR< 25, "p25">, DwarfRegNum<281>;
+def p26 : PR< 26, "p26">, DwarfRegNum<282>;
+def p27 : PR< 27, "p27">, DwarfRegNum<283>;
+def p28 : PR< 28, "p28">, DwarfRegNum<284>;
+def p29 : PR< 29, "p29">, DwarfRegNum<285>;
+def p30 : PR< 30, "p30">, DwarfRegNum<286>;
+def p31 : PR< 31, "p31">, DwarfRegNum<287>;
+def p32 : PR< 32, "p32">, DwarfRegNum<288>;
+def p33 : PR< 33, "p33">, DwarfRegNum<289>;
+def p34 : PR< 34, "p34">, DwarfRegNum<290>;
+def p35 : PR< 35, "p35">, DwarfRegNum<291>;
+def p36 : PR< 36, "p36">, DwarfRegNum<292>;
+def p37 : PR< 37, "p37">, DwarfRegNum<293>;
+def p38 : PR< 38, "p38">, DwarfRegNum<294>;
+def p39 : PR< 39, "p39">, DwarfRegNum<295>;
+def p40 : PR< 40, "p40">, DwarfRegNum<296>;
+def p41 : PR< 41, "p41">, DwarfRegNum<297>;
+def p42 : PR< 42, "p42">, DwarfRegNum<298>;
+def p43 : PR< 43, "p43">, DwarfRegNum<299>;
+def p44 : PR< 44, "p44">, DwarfRegNum<300>;
+def p45 : PR< 45, "p45">, DwarfRegNum<301>;
+def p46 : PR< 46, "p46">, DwarfRegNum<302>;
+def p47 : PR< 47, "p47">, DwarfRegNum<303>;
+def p48 : PR< 48, "p48">, DwarfRegNum<304>;
+def p49 : PR< 49, "p49">, DwarfRegNum<305>;
+def p50 : PR< 50, "p50">, DwarfRegNum<306>;
+def p51 : PR< 51, "p51">, DwarfRegNum<307>;
+def p52 : PR< 52, "p52">, DwarfRegNum<308>;
+def p53 : PR< 53, "p53">, DwarfRegNum<309>;
+def p54 : PR< 54, "p54">, DwarfRegNum<310>;
+def p55 : PR< 55, "p55">, DwarfRegNum<311>;
+def p56 : PR< 56, "p56">, DwarfRegNum<312>;
+def p57 : PR< 57, "p57">, DwarfRegNum<313>;
+def p58 : PR< 58, "p58">, DwarfRegNum<314>;
+def p59 : PR< 59, "p59">, DwarfRegNum<315>;
+def p60 : PR< 60, "p60">, DwarfRegNum<316>;
+def p61 : PR< 61, "p61">, DwarfRegNum<317>;
+def p62 : PR< 62, "p62">, DwarfRegNum<318>;
+def p63 : PR< 63, "p63">, DwarfRegNum<319>;
 
 // XXX : this is temporary, we'll eventually have the output registers
 // in the general purpose register class too?
-def out0 : GR<0, "out0">;  def out1 : GR<1, "out1">;
-def out2 : GR<2, "out2">;  def out3 : GR<3, "out3">;
-def out4 : GR<4, "out4">;  def out5 : GR<5, "out5">;
-def out6 : GR<6, "out6">;  def out7 : GR<7, "out7">;
+def out0 : GR<0, "out0">, DwarfRegNum<120>;
+def out1 : GR<1, "out1">, DwarfRegNum<121>;
+def out2 : GR<2, "out2">, DwarfRegNum<122>;
+def out3 : GR<3, "out3">, DwarfRegNum<123>;
+def out4 : GR<4, "out4">, DwarfRegNum<124>;
+def out5 : GR<5, "out5">, DwarfRegNum<125>;
+def out6 : GR<6, "out6">, DwarfRegNum<126>;
+def out7 : GR<7, "out7">, DwarfRegNum<127>;
 
 // application (special) registers:
 
 // "previous function state" application register
-def AR_PFS : GR<0, "ar.pfs">;
+def AR_PFS : GR<0, "ar.pfs">, DwarfRegNum<331>;
 
 // "return pointer" (this is really branch register b0)
-def rp : GR<0, "rp">;
+def rp : GR<0, "rp">, DwarfRegNum<-1>;
+
 // branch reg 6
-def B6 : GR<0, "b6">;
+def B6 : GR<0, "b6">, DwarfRegNum<326>;
 
 //===----------------------------------------------------------------------===//
 // Register Class Definitions... now that we have all of the pieces, define the
@@ -341,5 +506,3 @@ def PR : RegisterClass<"IA64", [i1], 64,
   p48, p49, p50, p51, p52, p53, p54, p55,
   p56, p57, p58, p59, p60, p61, p62, p63]>;
   */
-
-

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index afb433893223a775b812e4cf517376b067da6dcb..fe5c9d351ef763112ebfd38a73b518d77b7bc94b 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -48,89 +48,157 @@ class CR<bits<5> num, string n> : PPCReg<n> {
 }
 
 // General-purpose registers
-def R0  : GPR< 0,  "r0">;  def R1  : GPR< 1,  "r1">;
-def R2  : GPR< 2,  "r2">;  def R3  : GPR< 3,  "r3">;
-def R4  : GPR< 4,  "r4">;  def R5  : GPR< 5,  "r5">;
-def R6  : GPR< 6,  "r6">;  def R7  : GPR< 7,  "r7">;
-def R8  : GPR< 8,  "r8">;  def R9  : GPR< 9,  "r9">;
-def R10 : GPR<10, "r10">;  def R11 : GPR<11, "r11">;
-def R12 : GPR<12, "r12">;  def R13 : GPR<13, "r13">;
-def R14 : GPR<14, "r14">;  def R15 : GPR<15, "r15">;
-def R16 : GPR<16, "r16">;  def R17 : GPR<17, "r17">;
-def R18 : GPR<18, "r18">;  def R19 : GPR<19, "r19">;
-def R20 : GPR<20, "r20">;  def R21 : GPR<21, "r21">;
-def R22 : GPR<22, "r22">;  def R23 : GPR<23, "r23">;
-def R24 : GPR<24, "r24">;  def R25 : GPR<25, "r25">;
-def R26 : GPR<26, "r26">;  def R27 : GPR<27, "r27">;
-def R28 : GPR<28, "r28">;  def R29 : GPR<29, "r29">;
-def R30 : GPR<30, "r30">;  def R31 : GPR<31, "r31">;
+def R0  : GPR< 0,  "r0">, DwarfRegNum<0>;
+def R1  : GPR< 1,  "r1">, DwarfRegNum<1>;
+def R2  : GPR< 2,  "r2">, DwarfRegNum<2>;
+def R3  : GPR< 3,  "r3">, DwarfRegNum<3>;
+def R4  : GPR< 4,  "r4">, DwarfRegNum<4>;
+def R5  : GPR< 5,  "r5">, DwarfRegNum<5>;
+def R6  : GPR< 6,  "r6">, DwarfRegNum<6>;
+def R7  : GPR< 7,  "r7">, DwarfRegNum<7>;
+def R8  : GPR< 8,  "r8">, DwarfRegNum<8>;
+def R9  : GPR< 9,  "r9">, DwarfRegNum<9>;
+def R10 : GPR<10, "r10">, DwarfRegNum<10>;
+def R11 : GPR<11, "r11">, DwarfRegNum<11>;
+def R12 : GPR<12, "r12">, DwarfRegNum<12>;
+def R13 : GPR<13, "r13">, DwarfRegNum<13>;
+def R14 : GPR<14, "r14">, DwarfRegNum<14>;
+def R15 : GPR<15, "r15">, DwarfRegNum<15>;
+def R16 : GPR<16, "r16">, DwarfRegNum<16>;
+def R17 : GPR<17, "r17">, DwarfRegNum<17>;
+def R18 : GPR<18, "r18">, DwarfRegNum<18>;
+def R19 : GPR<19, "r19">, DwarfRegNum<19>;
+def R20 : GPR<20, "r20">, DwarfRegNum<20>;
+def R21 : GPR<21, "r21">, DwarfRegNum<21>;
+def R22 : GPR<22, "r22">, DwarfRegNum<22>;
+def R23 : GPR<23, "r23">, DwarfRegNum<23>;
+def R24 : GPR<24, "r24">, DwarfRegNum<24>;
+def R25 : GPR<25, "r25">, DwarfRegNum<25>;
+def R26 : GPR<26, "r26">, DwarfRegNum<26>;
+def R27 : GPR<27, "r27">, DwarfRegNum<27>;
+def R28 : GPR<28, "r28">, DwarfRegNum<28>;
+def R29 : GPR<29, "r29">, DwarfRegNum<29>;
+def R30 : GPR<30, "r30">, DwarfRegNum<30>;
+def R31 : GPR<31, "r31">, DwarfRegNum<31>;
 
 // 64-bit General-purpose registers
-def X0  : GP8< R0>;  def X1  : GP8< R1>;
-def X2  : GP8< R2>;  def X3  : GP8< R3>;
-def X4  : GP8< R4>;  def X5  : GP8< R5>;
-def X6  : GP8< R6>;  def X7  : GP8< R7>;
-def X8  : GP8< R8>;  def X9  : GP8< R9>;
-def X10 : GP8<R10>;  def X11 : GP8<R11>;
-def X12 : GP8<R12>;  def X13 : GP8<R13>;
-def X14 : GP8<R14>;  def X15 : GP8<R15>;
-def X16 : GP8<R16>;  def X17 : GP8<R17>;
-def X18 : GP8<R18>;  def X19 : GP8<R19>;
-def X20 : GP8<R20>;  def X21 : GP8<R21>;
-def X22 : GP8<R22>;  def X23 : GP8<R23>;
-def X24 : GP8<R24>;  def X25 : GP8<R25>;
-def X26 : GP8<R26>;  def X27 : GP8<R27>;
-def X28 : GP8<R28>;  def X29 : GP8<R29>;
-def X30 : GP8<R30>;  def X31 : GP8<R31>;
+def X0  : GP8< R0>, DwarfRegNum<0>;
+def X1  : GP8< R1>, DwarfRegNum<1>;
+def X2  : GP8< R2>, DwarfRegNum<2>;
+def X3  : GP8< R3>, DwarfRegNum<3>;
+def X4  : GP8< R4>, DwarfRegNum<4>;
+def X5  : GP8< R5>, DwarfRegNum<5>;
+def X6  : GP8< R6>, DwarfRegNum<6>;
+def X7  : GP8< R7>, DwarfRegNum<7>;
+def X8  : GP8< R8>, DwarfRegNum<8>;
+def X9  : GP8< R9>, DwarfRegNum<9>;
+def X10 : GP8<R10>, DwarfRegNum<10>;
+def X11 : GP8<R11>, DwarfRegNum<11>;
+def X12 : GP8<R12>, DwarfRegNum<12>;
+def X13 : GP8<R13>, DwarfRegNum<13>;
+def X14 : GP8<R14>, DwarfRegNum<14>;
+def X15 : GP8<R15>, DwarfRegNum<15>;
+def X16 : GP8<R16>, DwarfRegNum<16>;
+def X17 : GP8<R17>, DwarfRegNum<17>;
+def X18 : GP8<R18>, DwarfRegNum<18>;
+def X19 : GP8<R19>, DwarfRegNum<19>;
+def X20 : GP8<R20>, DwarfRegNum<20>;
+def X21 : GP8<R21>, DwarfRegNum<21>;
+def X22 : GP8<R22>, DwarfRegNum<22>;
+def X23 : GP8<R23>, DwarfRegNum<23>;
+def X24 : GP8<R24>, DwarfRegNum<24>;
+def X25 : GP8<R25>, DwarfRegNum<25>;
+def X26 : GP8<R26>, DwarfRegNum<26>;
+def X27 : GP8<R27>, DwarfRegNum<27>;
+def X28 : GP8<R28>, DwarfRegNum<28>;
+def X29 : GP8<R29>, DwarfRegNum<29>;
+def X30 : GP8<R30>, DwarfRegNum<30>;
+def X31 : GP8<R31>, DwarfRegNum<31>;
 
 // Floating-point registers
-def F0  : FPR< 0,  "f0">;  def F1  : FPR< 1,  "f1">;
-def F2  : FPR< 2,  "f2">;  def F3  : FPR< 3,  "f3">;
-def F4  : FPR< 4,  "f4">;  def F5  : FPR< 5,  "f5">;
-def F6  : FPR< 6,  "f6">;  def F7  : FPR< 7,  "f7">;
-def F8  : FPR< 8,  "f8">;  def F9  : FPR< 9,  "f9">;
-def F10 : FPR<10, "f10">;  def F11 : FPR<11, "f11">;
-def F12 : FPR<12, "f12">;  def F13 : FPR<13, "f13">;
-def F14 : FPR<14, "f14">;  def F15 : FPR<15, "f15">;
-def F16 : FPR<16, "f16">;  def F17 : FPR<17, "f17">;
-def F18 : FPR<18, "f18">;  def F19 : FPR<19, "f19">;
-def F20 : FPR<20, "f20">;  def F21 : FPR<21, "f21">;
-def F22 : FPR<22, "f22">;  def F23 : FPR<23, "f23">;
-def F24 : FPR<24, "f24">;  def F25 : FPR<25, "f25">;
-def F26 : FPR<26, "f26">;  def F27 : FPR<27, "f27">;
-def F28 : FPR<28, "f28">;  def F29 : FPR<29, "f29">;
-def F30 : FPR<30, "f30">;  def F31 : FPR<31, "f31">;
+def F0  : FPR< 0,  "f0">, DwarfRegNum<32>;
+def F1  : FPR< 1,  "f1">, DwarfRegNum<33>;
+def F2  : FPR< 2,  "f2">, DwarfRegNum<34>;
+def F3  : FPR< 3,  "f3">, DwarfRegNum<35>;
+def F4  : FPR< 4,  "f4">, DwarfRegNum<36>;
+def F5  : FPR< 5,  "f5">, DwarfRegNum<37>;
+def F6  : FPR< 6,  "f6">, DwarfRegNum<38>;
+def F7  : FPR< 7,  "f7">, DwarfRegNum<39>;
+def F8  : FPR< 8,  "f8">, DwarfRegNum<40>;
+def F9  : FPR< 9,  "f9">, DwarfRegNum<41>;
+def F10 : FPR<10, "f10">, DwarfRegNum<42>;
+def F11 : FPR<11, "f11">, DwarfRegNum<43>;
+def F12 : FPR<12, "f12">, DwarfRegNum<44>;
+def F13 : FPR<13, "f13">, DwarfRegNum<45>;
+def F14 : FPR<14, "f14">, DwarfRegNum<46>;
+def F15 : FPR<15, "f15">, DwarfRegNum<47>;
+def F16 : FPR<16, "f16">, DwarfRegNum<48>;
+def F17 : FPR<17, "f17">, DwarfRegNum<49>;
+def F18 : FPR<18, "f18">, DwarfRegNum<50>;
+def F19 : FPR<19, "f19">, DwarfRegNum<51>;
+def F20 : FPR<20, "f20">, DwarfRegNum<52>;
+def F21 : FPR<21, "f21">, DwarfRegNum<53>;
+def F22 : FPR<22, "f22">, DwarfRegNum<54>;
+def F23 : FPR<23, "f23">, DwarfRegNum<55>;
+def F24 : FPR<24, "f24">, DwarfRegNum<56>;
+def F25 : FPR<25, "f25">, DwarfRegNum<57>;
+def F26 : FPR<26, "f26">, DwarfRegNum<58>;
+def F27 : FPR<27, "f27">, DwarfRegNum<59>;
+def F28 : FPR<28, "f28">, DwarfRegNum<60>;
+def F29 : FPR<29, "f29">, DwarfRegNum<61>;
+def F30 : FPR<30, "f30">, DwarfRegNum<62>;
+def F31 : FPR<31, "f31">, DwarfRegNum<63>;
 
 // Vector registers
-def V0  : VR< 0,  "v0">;  def V1  : VR< 1,  "v1">;
-def V2  : VR< 2,  "v2">;  def V3  : VR< 3,  "v3">;
-def V4  : VR< 4,  "v4">;  def V5  : VR< 5,  "v5">;
-def V6  : VR< 6,  "v6">;  def V7  : VR< 7,  "v7">;
-def V8  : VR< 8,  "v8">;  def V9  : VR< 9,  "v9">;
-def V10 : VR<10, "v10">;  def V11 : VR<11, "v11">;
-def V12 : VR<12, "v12">;  def V13 : VR<13, "v13">;
-def V14 : VR<14, "v14">;  def V15 : VR<15, "v15">;
-def V16 : VR<16, "v16">;  def V17 : VR<17, "v17">;
-def V18 : VR<18, "v18">;  def V19 : VR<19, "v19">;
-def V20 : VR<20, "v20">;  def V21 : VR<21, "v21">;
-def V22 : VR<22, "v22">;  def V23 : VR<23, "v23">;
-def V24 : VR<24, "v24">;  def V25 : VR<25, "v25">;
-def V26 : VR<26, "v26">;  def V27 : VR<27, "v27">;
-def V28 : VR<28, "v28">;  def V29 : VR<29, "v29">;
-def V30 : VR<30, "v30">;  def V31 : VR<31, "v31">;
+def V0  : VR< 0,  "v0">, DwarfRegNum<77>;
+def V1  : VR< 1,  "v1">, DwarfRegNum<78>;
+def V2  : VR< 2,  "v2">, DwarfRegNum<79>;
+def V3  : VR< 3,  "v3">, DwarfRegNum<80>;
+def V4  : VR< 4,  "v4">, DwarfRegNum<81>;
+def V5  : VR< 5,  "v5">, DwarfRegNum<82>;
+def V6  : VR< 6,  "v6">, DwarfRegNum<83>;
+def V7  : VR< 7,  "v7">, DwarfRegNum<84>;
+def V8  : VR< 8,  "v8">, DwarfRegNum<85>;
+def V9  : VR< 9,  "v9">, DwarfRegNum<86>;
+def V10 : VR<10, "v10">, DwarfRegNum<87>;
+def V11 : VR<11, "v11">, DwarfRegNum<88>;
+def V12 : VR<12, "v12">, DwarfRegNum<89>;
+def V13 : VR<13, "v13">, DwarfRegNum<90>;
+def V14 : VR<14, "v14">, DwarfRegNum<91>;
+def V15 : VR<15, "v15">, DwarfRegNum<92>;
+def V16 : VR<16, "v16">, DwarfRegNum<93>;
+def V17 : VR<17, "v17">, DwarfRegNum<94>;
+def V18 : VR<18, "v18">, DwarfRegNum<95>;
+def V19 : VR<19, "v19">, DwarfRegNum<96>;
+def V20 : VR<20, "v20">, DwarfRegNum<97>;
+def V21 : VR<21, "v21">, DwarfRegNum<98>;
+def V22 : VR<22, "v22">, DwarfRegNum<99>;
+def V23 : VR<23, "v23">, DwarfRegNum<100>;
+def V24 : VR<24, "v24">, DwarfRegNum<101>;
+def V25 : VR<25, "v25">, DwarfRegNum<102>;
+def V26 : VR<26, "v26">, DwarfRegNum<103>;
+def V27 : VR<27, "v27">, DwarfRegNum<104>;
+def V28 : VR<28, "v28">, DwarfRegNum<105>;
+def V29 : VR<29, "v29">, DwarfRegNum<106>;
+def V30 : VR<30, "v30">, DwarfRegNum<107>;
+def V31 : VR<31, "v31">, DwarfRegNum<108>;
 
 // Condition registers
-def CR0 : CR<0, "cr0">; def CR1 : CR<1, "cr1">;
-def CR2 : CR<2, "cr2">; def CR3 : CR<3, "cr3">;
-def CR4 : CR<4, "cr4">; def CR5 : CR<5, "cr5">;
-def CR6 : CR<6, "cr6">; def CR7 : CR<7, "cr7">;
+def CR0 : CR<0, "cr0">, DwarfRegNum<68>;
+def CR1 : CR<1, "cr1">, DwarfRegNum<69>;
+def CR2 : CR<2, "cr2">, DwarfRegNum<70>;
+def CR3 : CR<3, "cr3">, DwarfRegNum<71>;
+def CR4 : CR<4, "cr4">, DwarfRegNum<72>;
+def CR5 : CR<5, "cr5">, DwarfRegNum<73>;
+def CR6 : CR<6, "cr6">, DwarfRegNum<74>;
+def CR7 : CR<7, "cr7">, DwarfRegNum<75>;
 
 // Link register
-def LR  : SPR<8, "lr">;
+def LR  : SPR<8, "lr">, DwarfRegNum<65>;
 // Count register
-def CTR : SPR<9, "ctr">;
+def CTR : SPR<9, "ctr">, DwarfRegNum<66>;
 // VRsave register
-def VRSAVE: SPR<256, "VRsave">;
+def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<107>;
 
 /// Register classes
 // Allocate volatiles first
@@ -198,3 +266,4 @@ def VRRC : RegisterClass<"PPC", [v16i8,v4f32,v4i32], 128,
 
 def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, 
   CR3, CR4]>;
+  

diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td
index a20ebcfbc94d67f9c0154cd2e7e640768d5916c1..eb2049c969d0d11c57305a0d9a6ec8dc11373f24 100644 (file)
--- a/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/lib/Target/Sparc/SparcRegisterInfo.td
@@ -32,41 +32,90 @@ class Rd<bits<5> num, string n, list<Register> aliases> : SparcReg<n> {
 }
 
 // Integer registers
-def G0 : Ri< 0, "G0">; def G1 : Ri< 1, "G1">; def G2 : Ri< 2, "G2">; 
-def G3 : Ri< 3, "G3">; def G4 : Ri< 4, "G4">; def G5 : Ri< 5, "G5">; 
-def G6 : Ri< 6, "G6">; def G7 : Ri< 7, "G7">;
-def O0 : Ri< 8, "O0">; def O1 : Ri< 9, "O1">; def O2 : Ri<10, "O2">; 
-def O3 : Ri<11, "O3">; def O4 : Ri<12, "O4">; def O5 : Ri<13, "O5">; 
-def O6 : Ri<14, "O6">; def O7 : Ri<15, "O7">;
-def L0 : Ri<16, "L0">; def L1 : Ri<17, "L1">; def L2 : Ri<18, "L2">; 
-def L3 : Ri<19, "L3">; def L4 : Ri<20, "L4">; def L5 : Ri<21, "L5">; 
-def L6 : Ri<22, "L6">; def L7 : Ri<23, "L7">;
-def I0 : Ri<24, "I0">; def I1 : Ri<25, "I1">; def I2 : Ri<26, "I2">; 
-def I3 : Ri<27, "I3">; def I4 : Ri<28, "I4">; def I5 : Ri<29, "I5">; 
-def I6 : Ri<30, "I6">; def I7 : Ri<31, "I7">;
+def G0 : Ri< 0, "G0">, DwarfRegNum<0>;
+def G1 : Ri< 1, "G1">, DwarfRegNum<1>;
+def G2 : Ri< 2, "G2">, DwarfRegNum<2>; 
+def G3 : Ri< 3, "G3">, DwarfRegNum<3>;
+def G4 : Ri< 4, "G4">, DwarfRegNum<4>;
+def G5 : Ri< 5, "G5">, DwarfRegNum<5>; 
+def G6 : Ri< 6, "G6">, DwarfRegNum<6>;
+def G7 : Ri< 7, "G7">, DwarfRegNum<7>;
+def O0 : Ri< 8, "O0">, DwarfRegNum<8>;
+def O1 : Ri< 9, "O1">, DwarfRegNum<9>;
+def O2 : Ri<10, "O2">, DwarfRegNum<10>; 
+def O3 : Ri<11, "O3">, DwarfRegNum<11>;
+def O4 : Ri<12, "O4">, DwarfRegNum<12>;
+def O5 : Ri<13, "O5">, DwarfRegNum<13>; 
+def O6 : Ri<14, "O6">, DwarfRegNum<14>;
+def O7 : Ri<15, "O7">, DwarfRegNum<15>;
+def L0 : Ri<16, "L0">, DwarfRegNum<16>;
+def L1 : Ri<17, "L1">, DwarfRegNum<17>;
+def L2 : Ri<18, "L2">, DwarfRegNum<18>; 
+def L3 : Ri<19, "L3">, DwarfRegNum<19>;
+def L4 : Ri<20, "L4">, DwarfRegNum<20>;
+def L5 : Ri<21, "L5">, DwarfRegNum<21>; 
+def L6 : Ri<22, "L6">, DwarfRegNum<22>;
+def L7 : Ri<23, "L7">, DwarfRegNum<23>;
+def I0 : Ri<24, "I0">, DwarfRegNum<24>;
+def I1 : Ri<25, "I1">, DwarfRegNum<25>;
+def I2 : Ri<26, "I2">, DwarfRegNum<26>; 
+def I3 : Ri<27, "I3">, DwarfRegNum<27>;
+def I4 : Ri<28, "I4">, DwarfRegNum<28>;
+def I5 : Ri<29, "I5">, DwarfRegNum<29>; 
+def I6 : Ri<30, "I6">, DwarfRegNum<30>;
+def I7 : Ri<31, "I7">, DwarfRegNum<31>;
 
 // Floating-point registers
-def F0  : Rf< 0,  "F0">; def F1  : Rf< 1,  "F1">; def F2  : Rf< 2,  "F2">; 
-def F3  : Rf< 3,  "F3">; def F4  : Rf< 4,  "F4">; def F5  : Rf< 5,  "F5">; 
-def F6  : Rf< 6,  "F6">; def F7  : Rf< 7,  "F7">; def F8  : Rf< 8,  "F8">; 
-def F9  : Rf< 9,  "F9">; def F10 : Rf<10, "F10">; def F11 : Rf<11, "F11">; 
-def F12 : Rf<12, "F12">; def F13 : Rf<13, "F13">; def F14 : Rf<14, "F14">; 
-def F15 : Rf<15, "F15">; def F16 : Rf<16, "F16">; def F17 : Rf<17, "F17">; 
-def F18 : Rf<18, "F18">; def F19 : Rf<19, "F19">; def F20 : Rf<20, "F20">; 
-def F21 : Rf<21, "F21">; def F22 : Rf<22, "F22">; def F23 : Rf<23, "F23">;
-def F24 : Rf<24, "F24">; def F25 : Rf<25, "F25">; def F26 : Rf<26, "F26">; 
-def F27 : Rf<27, "F27">; def F28 : Rf<28, "F28">; def F29 : Rf<29, "F29">; 
-def F30 : Rf<30, "F30">; def F31 : Rf<31, "F31">;
+def F0  : Rf< 0,  "F0">, DwarfRegNum<32>;
+def F1  : Rf< 1,  "F1">, DwarfRegNum<33>;
+def F2  : Rf< 2,  "F2">, DwarfRegNum<34>; 
+def F3  : Rf< 3,  "F3">, DwarfRegNum<35>;
+def F4  : Rf< 4,  "F4">, DwarfRegNum<36>;
+def F5  : Rf< 5,  "F5">, DwarfRegNum<37>; 
+def F6  : Rf< 6,  "F6">, DwarfRegNum<38>;
+def F7  : Rf< 7,  "F7">, DwarfRegNum<39>;
+def F8  : Rf< 8,  "F8">, DwarfRegNum<40>; 
+def F9  : Rf< 9,  "F9">, DwarfRegNum<41>;
+def F10 : Rf<10, "F10">, DwarfRegNum<42>;
+def F11 : Rf<11, "F11">, DwarfRegNum<43>; 
+def F12 : Rf<12, "F12">, DwarfRegNum<44>;
+def F13 : Rf<13, "F13">, DwarfRegNum<45>;
+def F14 : Rf<14, "F14">, DwarfRegNum<46>; 
+def F15 : Rf<15, "F15">, DwarfRegNum<47>;
+def F16 : Rf<16, "F16">, DwarfRegNum<48>;
+def F17 : Rf<17, "F17">, DwarfRegNum<49>; 
+def F18 : Rf<18, "F18">, DwarfRegNum<50>;
+def F19 : Rf<19, "F19">, DwarfRegNum<51>;
+def F20 : Rf<20, "F20">, DwarfRegNum<52>; 
+def F21 : Rf<21, "F21">, DwarfRegNum<53>;
+def F22 : Rf<22, "F22">, DwarfRegNum<54>;
+def F23 : Rf<23, "F23">, DwarfRegNum<55>;
+def F24 : Rf<24, "F24">, DwarfRegNum<56>;
+def F25 : Rf<25, "F25">, DwarfRegNum<57>;
+def F26 : Rf<26, "F26">, DwarfRegNum<58>; 
+def F27 : Rf<27, "F27">, DwarfRegNum<59>;
+def F28 : Rf<28, "F28">, DwarfRegNum<60>;
+def F29 : Rf<29, "F29">, DwarfRegNum<61>; 
+def F30 : Rf<30, "F30">, DwarfRegNum<62>;
+def F31 : Rf<31, "F31">, DwarfRegNum<63>;
 
 // Aliases of the F* registers used to hold 64-bit fp values (doubles)
-def D0  : Rd< 0,  "F0", [F0,   F1]>; def D1  : Rd< 2,  "F2", [F2,   F3]>; 
-def D2  : Rd< 4,  "F4", [F4,   F5]>; def D3  : Rd< 6,  "F6", [F6,   F7]>; 
-def D4  : Rd< 8,  "F8", [F8,   F9]>; def D5  : Rd<10, "F10", [F10, F11]>;
-def D6  : Rd<12, "F12", [F12, F13]>; def D7  : Rd<14, "F14", [F14, F15]>; 
-def D8  : Rd<16, "F16", [F16, F17]>; def D9  : Rd<18, "F18", [F18, F19]>; 
-def D10 : Rd<20, "F20", [F20, F21]>; def D11 : Rd<22, "F22", [F22, F23]>;
-def D12 : Rd<24, "F24", [F24, F25]>; def D13 : Rd<26, "F26", [F26, F27]>; 
-def D14 : Rd<28, "F28", [F28, F29]>; def D15 : Rd<30, "F30", [F30, F31]>;
+def D0  : Rd< 0,  "F0", [F0,   F1]>, DwarfRegNum<32>;
+def D1  : Rd< 2,  "F2", [F2,   F3]>, DwarfRegNum<33>; 
+def D2  : Rd< 4,  "F4", [F4,   F5]>, DwarfRegNum<34>;
+def D3  : Rd< 6,  "F6", [F6,   F7]>, DwarfRegNum<35>; 
+def D4  : Rd< 8,  "F8", [F8,   F9]>, DwarfRegNum<36>;
+def D5  : Rd<10, "F10", [F10, F11]>, DwarfRegNum<37>;
+def D6  : Rd<12, "F12", [F12, F13]>, DwarfRegNum<38>;
+def D7  : Rd<14, "F14", [F14, F15]>, DwarfRegNum<39>; 
+def D8  : Rd<16, "F16", [F16, F17]>, DwarfRegNum<40>;
+def D9  : Rd<18, "F18", [F18, F19]>, DwarfRegNum<41>; 
+def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<42>;
+def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<43>;
+def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<44>;
+def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<45>; 
+def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<46>;
+def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<47>;
 
 // Register classes.
 //

diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 18c9417cb9d61fd070d040a4bc4391f5bed7e0f1..b7b5874717df3b9916e8ab3a6a7cca2af08f52c5 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -24,46 +24,73 @@ let Namespace = "X86" in {
   // AL aliases AX if we tell it that AX aliased AL (for example).
 
   // 32-bit registers
-  def EAX : Register<"EAX">; def ECX : Register<"ECX">;
-  def EDX : Register<"EDX">; def EBX : Register<"EBX">;
-  def ESP : Register<"ESP">; def EBP : Register<"EBP">;
-  def ESI : Register<"ESI">; def EDI : Register<"EDI">;
+  def EAX : Register<"EAX">, DwarfRegNum<0>;
+  def ECX : Register<"ECX">, DwarfRegNum<2>;
+  def EDX : Register<"EDX">, DwarfRegNum<1>;
+  def EBX : Register<"EBX">, DwarfRegNum<3>;
+  def ESP : Register<"ESP">, DwarfRegNum<7>;
+  def EBP : Register<"EBP">, DwarfRegNum<6>;
+  def ESI : Register<"ESI">, DwarfRegNum<4>;
+  def EDI : Register<"EDI">, DwarfRegNum<5>;
   
   // 16-bit registers
-  def AX : RegisterGroup<"AX", [EAX]>; def CX : RegisterGroup<"CX", [ECX]>;
-  def DX : RegisterGroup<"DX", [EDX]>; def BX : RegisterGroup<"BX", [EBX]>;
-  def SP : RegisterGroup<"SP", [ESP]>; def BP : RegisterGroup<"BP", [EBP]>;
-  def SI : RegisterGroup<"SI", [ESI]>; def DI : RegisterGroup<"DI", [EDI]>;
+  def AX : RegisterGroup<"AX", [EAX]>, DwarfRegNum<0>;
+  def CX : RegisterGroup<"CX", [ECX]>, DwarfRegNum<2>;
+  def DX : RegisterGroup<"DX", [EDX]>, DwarfRegNum<1>;
+  def BX : RegisterGroup<"BX", [EBX]>, DwarfRegNum<3>;
+  def SP : RegisterGroup<"SP", [ESP]>, DwarfRegNum<7>;
+  def BP : RegisterGroup<"BP", [EBP]>, DwarfRegNum<6>;
+  def SI : RegisterGroup<"SI", [ESI]>, DwarfRegNum<4>;
+  def DI : RegisterGroup<"DI", [EDI]>, DwarfRegNum<5>;
   
   // 8-bit registers
-  def AL : RegisterGroup<"AL", [AX,EAX]>; def CL : RegisterGroup<"CL",[CX,ECX]>;
-  def DL : RegisterGroup<"DL", [DX,EDX]>; def BL : RegisterGroup<"BL",[BX,EBX]>;
-  def AH : RegisterGroup<"AH", [AX,EAX]>; def CH : RegisterGroup<"CH",[CX,ECX]>;
-  def DH : RegisterGroup<"DH", [DX,EDX]>; def BH : RegisterGroup<"BH",[BX,EBX]>;
+  def AL : RegisterGroup<"AL", [AX,EAX]>, DwarfRegNum<0>;
+  def CL : RegisterGroup<"CL", [CX,ECX]>, DwarfRegNum<2>;
+  def DL : RegisterGroup<"DL", [DX,EDX]>, DwarfRegNum<1>;
+  def BL : RegisterGroup<"BL", [BX,EBX]>, DwarfRegNum<0>;
+  def AH : RegisterGroup<"AH", [AX,EAX]>, DwarfRegNum<2>;
+  def CH : RegisterGroup<"CH", [CX,ECX]>, DwarfRegNum<2>;
+  def DH : RegisterGroup<"DH", [DX,EDX]>, DwarfRegNum<1>;
+  def BH : RegisterGroup<"BH", [BX,EBX]>, DwarfRegNum<3>;
 
   // MMX Registers. These are actually aliased to ST0 .. ST7
-  def MM0 : Register<"MM0">; def MM1 : Register<"MM1">;
-  def MM2 : Register<"MM2">; def MM3 : Register<"MM3">;
-  def MM4 : Register<"MM4">; def MM5 : Register<"MM5">;
-  def MM6 : Register<"MM6">; def MM7 : Register<"MM7">;
+  def MM0 : Register<"MM0">, DwarfRegNum<29>;
+  def MM1 : Register<"MM1">, DwarfRegNum<30>;
+  def MM2 : Register<"MM2">, DwarfRegNum<31>;
+  def MM3 : Register<"MM3">, DwarfRegNum<32>;
+  def MM4 : Register<"MM4">, DwarfRegNum<33>;
+  def MM5 : Register<"MM5">, DwarfRegNum<34>;
+  def MM6 : Register<"MM6">, DwarfRegNum<35>;
+  def MM7 : Register<"MM7">, DwarfRegNum<36>;
   
   // Pseudo Floating Point registers
-  def FP0 : Register<"FP0">; def FP1 : Register<"FP1">;
-  def FP2 : Register<"FP2">; def FP3 : Register<"FP3">;
-  def FP4 : Register<"FP4">; def FP5 : Register<"FP5">;
-  def FP6 : Register<"FP6">; 
+  def FP0 : Register<"FP0">, DwarfRegNum<-1>;
+  def FP1 : Register<"FP1">, DwarfRegNum<-1>;
+  def FP2 : Register<"FP2">, DwarfRegNum<-1>;
+  def FP3 : Register<"FP3">, DwarfRegNum<-1>;
+  def FP4 : Register<"FP4">, DwarfRegNum<-1>;
+  def FP5 : Register<"FP5">, DwarfRegNum<-1>;
+  def FP6 : Register<"FP6">, DwarfRegNum<-1>; 
 
   // XMM Registers, used by the various SSE instruction set extensions
-  def XMM0: Register<"XMM0">; def XMM1: Register<"XMM1">;
-  def XMM2: Register<"XMM2">; def XMM3: Register<"XMM3">;
-  def XMM4: Register<"XMM4">; def XMM5: Register<"XMM5">;
-  def XMM6: Register<"XMM6">; def XMM7: Register<"XMM7">;
+  def XMM0: Register<"XMM0">, DwarfRegNum<21>;
+  def XMM1: Register<"XMM1">, DwarfRegNum<22>;
+  def XMM2: Register<"XMM2">, DwarfRegNum<23>;
+  def XMM3: Register<"XMM3">, DwarfRegNum<24>;
+  def XMM4: Register<"XMM4">, DwarfRegNum<25>;
+  def XMM5: Register<"XMM5">, DwarfRegNum<26>;
+  def XMM6: Register<"XMM6">, DwarfRegNum<27>;
+  def XMM7: Register<"XMM7">, DwarfRegNum<28>;
 
   // Floating point stack registers
-  def ST0 : Register<"ST(0)">; def ST1 : Register<"ST(1)">;
-  def ST2 : Register<"ST(2)">; def ST3 : Register<"ST(3)">;
-  def ST4 : Register<"ST(4)">; def ST5 : Register<"ST(5)">;
-  def ST6 : Register<"ST(6)">; def ST7 : Register<"ST(7)">; 
+  def ST0 : Register<"ST(0)">, DwarfRegNum<8>;
+  def ST1 : Register<"ST(1)">, DwarfRegNum<9>;
+  def ST2 : Register<"ST(2)">, DwarfRegNum<10>;
+  def ST3 : Register<"ST(3)">, DwarfRegNum<11>;
+  def ST4 : Register<"ST(4)">, DwarfRegNum<12>;
+  def ST5 : Register<"ST(5)">, DwarfRegNum<13>;
+  def ST6 : Register<"ST(6)">, DwarfRegNum<14>;
+  def ST7 : Register<"ST(7)">, DwarfRegNum<15>; 
 }
 
 //===----------------------------------------------------------------------===//

diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 2f9a7dded5b2119fa8b4a77e471599bfea293cea..4821dbe51571fd387b38e6fdc78add4a359f540d 100644 (file)
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -60,7 +60,8 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) {
      << "  " << ClassName
      << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
      << "  const unsigned* getCalleeSaveRegs() const;\n"
-     << "const TargetRegisterClass* const *getCalleeSaveRegClasses() const;\n"
+     << "  const TargetRegisterClass* const *getCalleeSaveRegClasses() const;\n"
+     << "  int getDwarfRegNum(unsigned RegNum) const;\n"
      << "};\n\n";
 
   const std::vector<CodeGenRegisterClass> &RegisterClasses =
@@ -277,6 +278,22 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
     OS << "&" << getQualifiedName(RC->TheDef) << "RegClass, ";
   }
   OS << " 0\n  };\n  return CalleeSaveRegClasses;\n}\n\n";
+ 
+  // Emit information about the dwarf register numbers.
+  OS << "int " << ClassName << "::getDwarfRegNum(unsigned RegNum) const {\n";
+  OS << "  static const int DwarfRegNums[] = { -1, // NoRegister";
+  for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
+    if (!(i % 16)) OS << "\n    ";
+    const CodeGenRegister &Reg = Registers[i];
+    int DwarfRegNum = Reg.TheDef->getValueAsInt("DwarfNumber");
+    OS << DwarfRegNum;
+    if ((i + 1) != e)  OS << ", ";
+  }
+  OS << "\n  };\n";
+  OS << "  assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) &&\n";
+  OS << "         \"RegNum exceeds number of registers\");\n";
+  OS << "  return DwarfRegNums[RegNum];\n";
+  OS << "}\n\n";
 
   OS << "} // End llvm namespace \n";
 }