rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3ff);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0e1);
- //cosa add for sd3's request 01/23/2008
- #if 0
- if(priv->chan == 3 || priv->chan == 9) //I need to set priv->chan whenever current channel changes
- rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b);
- else
- rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
- #endif
}
else
{
{
u32 TxAGC=0;
struct r8192_priv *priv = ieee80211_priv(dev);
-#ifdef RTL8190P
- u8 byte0, byte1;
-
- TxAGC |= ((powerlevel<<8)|powerlevel);
- TxAGC += priv->CCKTxPowerLevelOriginalOffset;
-
- if(priv->bDynamicTxLowPower == true //cosa 04282008 for cck long range
- /*pMgntInfo->bScanInProgress == TRUE*/ ) //cosa 05/22/2008 for scan
- {
- if(priv->CustomerID == RT_CID_819x_Netcore)
- TxAGC = 0x2222;
- else
- TxAGC += ((priv->CckPwEnl<<8)|priv->CckPwEnl);
- }
-
- byte0 = (u8)(TxAGC & 0xff);
- byte1 = (u8)((TxAGC & 0xff00)>>8);
- if(byte0 > 0x24)
- byte0 = 0x24;
- if(byte1 > 0x24)
- byte1 = 0x24;
- if(priv->rf_type == RF_2T4R) //Only 2T4R you have to care the Antenna Tx Power offset
- { // check antenna C over the max index 0x24
- if(priv->RF_C_TxPwDiff > 0)
- {
- if( (byte0 + (u8)priv->RF_C_TxPwDiff) > 0x24)
- byte0 = 0x24 - priv->RF_C_TxPwDiff;
- if( (byte1 + (u8)priv->RF_C_TxPwDiff) > 0x24)
- byte1 = 0x24 - priv->RF_C_TxPwDiff;
- }
- }
- TxAGC = (byte1<<8) |byte0;
- write_nic_dword(priv, CCK_TXAGC, TxAGC);
-#else
- #ifdef RTL8192E
TxAGC = powerlevel;
if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range
if(TxAGC > 0x24)
TxAGC = 0x24;
rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
- #endif
-#endif
}
void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
{
struct r8192_priv *priv = ieee80211_priv(dev);
- //Joseph TxPower for 8192 testing
-#ifdef RTL8190P
- u32 TxAGC1=0, TxAGC2=0, TxAGC2_tmp = 0;
- u8 i, byteVal1[4], byteVal2[4], byteVal3[4];
-
- if(priv->bDynamicTxHighPower == true) //Add by Jacken 2008/03/06
- {
- TxAGC1 |= ((powerlevel<<24)|(powerlevel<<16)|(powerlevel<<8)|powerlevel);
- //for tx power track
- TxAGC2_tmp = TxAGC1;
-
- TxAGC1 += priv->MCSTxPowerLevelOriginalOffset[0];
- TxAGC2 =0x03030303;
-
- //for tx power track
- TxAGC2_tmp += priv->MCSTxPowerLevelOriginalOffset[1];
- }
- else
- {
- TxAGC1 |= ((powerlevel<<24)|(powerlevel<<16)|(powerlevel<<8)|powerlevel);
- TxAGC2 = TxAGC1;
-
- TxAGC1 += priv->MCSTxPowerLevelOriginalOffset[0];
- TxAGC2 += priv->MCSTxPowerLevelOriginalOffset[1];
-
- TxAGC2_tmp = TxAGC2;
-
- }
- for(i=0; i<4; i++)
- {
- byteVal1[i] = (u8)( (TxAGC1 & (0xff<<(i*8))) >>(i*8) );
- if(byteVal1[i] > 0x24)
- byteVal1[i] = 0x24;
- byteVal2[i] = (u8)( (TxAGC2 & (0xff<<(i*8))) >>(i*8) );
- if(byteVal2[i] > 0x24)
- byteVal2[i] = 0x24;
-
- //for tx power track
- byteVal3[i] = (u8)( (TxAGC2_tmp & (0xff<<(i*8))) >>(i*8) );
- if(byteVal3[i] > 0x24)
- byteVal3[i] = 0x24;
- }
-
- if(priv->rf_type == RF_2T4R) //Only 2T4R you have to care the Antenna Tx Power offset
- { // check antenna C over the max index 0x24
- if(priv->RF_C_TxPwDiff > 0)
- {
- for(i=0; i<4; i++)
- {
- if( (byteVal1[i] + (u8)priv->RF_C_TxPwDiff) > 0x24)
- byteVal1[i] = 0x24 - priv->RF_C_TxPwDiff;
- if( (byteVal2[i] + (u8)priv->RF_C_TxPwDiff) > 0x24)
- byteVal2[i] = 0x24 - priv->RF_C_TxPwDiff;
- if( (byteVal3[i] + (u8)priv->RF_C_TxPwDiff) > 0x24)
- byteVal3[i] = 0x24 - priv->RF_C_TxPwDiff;
- }
- }
- }
-
- TxAGC1 = (byteVal1[3]<<24) | (byteVal1[2]<<16) |(byteVal1[1]<<8) |byteVal1[0];
- TxAGC2 = (byteVal2[3]<<24) | (byteVal2[2]<<16) |(byteVal2[1]<<8) |byteVal2[0];
- //for tx power track
- TxAGC2_tmp = (byteVal3[3]<<24) | (byteVal3[2]<<16) |(byteVal3[1]<<8) |byteVal3[0];
- priv->Pwr_Track = TxAGC2_tmp;
- //DbgPrint("TxAGC2_tmp = 0x%x\n", TxAGC2_tmp);
-
- //DbgPrint("TxAGC1/TxAGC2 = 0x%x/0x%x\n", TxAGC1, TxAGC2);
- write_nic_dword(priv, MCS_TXAGC, TxAGC1);
- write_nic_dword(priv, MCS_TXAGC+4, TxAGC2);
-#else
-#ifdef RTL8192E
u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
u8 index = 0;
u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
}
rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
}
-
-#endif
-#endif
}
#define MAX_DOZE_WAITING_TIMES_9x 64
//RXTX enable control: On
//for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
// PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x2);
-#ifdef RTL8190P
- if(priv->rf_type == RF_2T4R)
- {
- //enable RF-Chip A/B
- rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
- //enable RF-Chip C/D
- rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4]
- //analog to digital on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
- //digital to analog on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0xf); // 0x880[8:5]
- //rx antenna on
- rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0xf);// 0xc04[3:0]
- //rx antenna on
- rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0xf);// 0xd04[3:0]
- //analog to digital part2 on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0xf); // 0x880[12:9]
- }
- else if(priv->rf_type == RF_1T2R) //RF-C, RF-D
- {
- //enable RF-Chip C/D
- rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4]
- //analog to digital on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
- //digital to analog on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x180, 0x3); // 0x880[8:7]
- //rx antenna on
- rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xc, 0x3);// 0xc04[3:2]
- //rx antenna on
- rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xc, 0x3);// 0xd04[3:2]
- //analog to digital part2 on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1800, 0x3); // 0x880[12:11]
- }
- else if(priv->rf_type == RF_1T1R) //RF-C
- {
- //enable RF-Chip C/D
- rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4]
- //analog to digital on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x400, 0x1);// 0x88c[10]
- //digital to analog on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x80, 0x1); // 0x880[7]
- //rx antenna on
- rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x4, 0x1);// 0xc04[2]
- //rx antenna on
- rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x4, 0x1);// 0xd04[2]
- //analog to digital part2 on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x800, 0x1); // 0x880[11]
- }
-#elif defined RTL8192E
// turn on RF
if((priv->ieee80211->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
{ // The current RF state is OFF and the RF OFF level is halting the NIC, re-initialize the NIC.
}
- #endif
break;
//
}
}
- //if(Adapter->HardwareType == HARDWARE_TYPE_RTL8190P)
-#ifdef RTL8190P
- {
- PHY_SetRtl8190pRfOff(dev);
- }
- //else if(Adapter->HardwareType == HARDWARE_TYPE_RTL8192E)
-#elif defined RTL8192E
- {
- PHY_SetRtl8192eRfOff(dev);
- }
-#endif
+ PHY_SetRtl8192eRfOff(dev);
}
break;
}
}
- //if(Adapter->HardwareType == HARDWARE_TYPE_RTL8190P)
-#if defined RTL8190P
- {
- PHY_SetRtl8190pRfOff(dev);
- }
- //else if(Adapter->HardwareType == HARDWARE_TYPE_RTL8192E)
-#elif defined RTL8192E
{
//if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC) && priv->ieee80211->RfOffReason > RF_CHANGE_BY_PS)
if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
PHY_SetRtl8192eRfOff(dev);
}
}
-#else
- else
- {
- RT_TRACE(COMP_DBG,DBG_TRACE,("It is not 8190Pci and 8192PciE \n"));
- }
- #endif
-
- break;
+ break;
default:
bResult = false;
bool bResult = false;
RT_TRACE(COMP_RF,"---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
-#ifdef RTL8192E
if(eRFPowerState == priv->ieee80211->eRFPowerState && priv->bHwRfOffAction == 0)
-#else
- if(eRFPowerState == priv->ieee80211->eRFPowerState)
-#endif
{
RT_TRACE(COMP_POWER, "<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
return bResult;
#ifndef RTL8225_H
#define RTL8225_H
-#ifdef RTL8190P
-#define RTL819X_TOTAL_RF_PATH 4
-#else
#define RTL819X_TOTAL_RF_PATH 2 /* for 8192E */
-#endif
void PHY_SetRF8256Bandwidth(struct net_device *dev,
HT_CHANNEL_WIDTH Bandwidth);
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
- * Linux device driver for RTL8190P / RTL8192E
+ * Linux device driver for RTL8192E
*
* Based on the r8180 driver, which is:
* Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
COMP_ERR ; //always open err flags on
static DEFINE_PCI_DEVICE_TABLE(rtl8192_pci_id_tbl) = {
-#ifdef RTL8190P
- /* Realtek */
- /* Dlink */
- { PCI_DEVICE(0x10ec, 0x8190) },
- /* Corega */
- { PCI_DEVICE(0x07aa, 0x0045) },
- { PCI_DEVICE(0x07aa, 0x0046) },
-#else
/* Realtek */
{ PCI_DEVICE(0x10ec, 0x8192) },
/* Corega */
{ PCI_DEVICE(0x07aa, 0x0044) },
{ PCI_DEVICE(0x07aa, 0x0047) },
-#endif
{}
};
if (!reset) {
mdelay(150);
-#ifdef RTL8192E
priv->bHwRfOffAction = 2;
-#endif
/*
* Call MgntActSet_RF_State instead to
if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
if (tcb_desc->bPacketBW) {
pTxFwInfo->TxBandwidth = 1;
-#ifdef RTL8190P
- pTxFwInfo->TxSubCarrier = 3;
-#else
/* use duplicated mode */
pTxFwInfo->TxSubCarrier = 0;
-#endif
} else {
pTxFwInfo->TxBandwidth = 0;
pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
{
struct net_device *dev = priv->ieee80211->dev;
u8 tempval;
-#ifdef RTL8192E
u8 ICVer8192, ICVer8256;
-#endif
u16 i,usValue, IC_Version;
u16 EEPROMId;
-#ifdef RTL8190P
- u8 offset;
- u8 EepromTxPower[100];
-#endif
u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n");
priv->eeprom_ChannelPlan = usValue&0xff;
IC_Version = ((usValue&0xff00)>>8);
-#ifdef RTL8190P
- priv->card_8192_version = (VERSION_8190)(IC_Version);
-#else
- #ifdef RTL8192E
ICVer8192 = (IC_Version&0xf); //bit0~3; 1:A cut, 2:B cut, 3:C cut...
ICVer8256 = ((IC_Version&0xf0)>>4);//bit4~6, bit7 reserved for other RF chip; 1:A cut, 2:B cut, 3:C cut...
RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
if(ICVer8256 == 0x5) //E-cut
priv->card_8192_version= VERSION_8190_BE;
}
- #endif
-#endif
+
switch(priv->card_8192_version)
{
case VERSION_8190_BD:
RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i+1, priv->EEPROMTxPowerLevelOFDM24G[i+1]);
}
}
- else if(priv->epromtype== EPROM_93c56)
- {
- #ifdef RTL8190P
- // Read CrystalCap from EEPROM
- if(!priv->AutoloadFailFlag)
- {
- priv->EEPROMAntPwDiff = EEPROM_Default_AntTxPowerDiff;
- priv->EEPROMCrystalCap = (u8)(((eprom_read(dev, (EEPROM_C56_CrystalCap>>1))) & 0xf000)>>12);
- }
- else
- {
- priv->EEPROMAntPwDiff = EEPROM_Default_AntTxPowerDiff;
- priv->EEPROMCrystalCap = EEPROM_Default_TxPwDiff_CrystalCap;
- }
- RT_TRACE(COMP_INIT,"EEPROMAntPwDiff = %d\n", priv->EEPROMAntPwDiff);
- RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n", priv->EEPROMCrystalCap);
-
- // Get Tx Power Level by Channel
- if(!priv->AutoloadFailFlag)
- {
- // Read Tx power of Channel 1 ~ 14 from EEPROM.
- for(i = 0; i < 12; i+=2)
- {
- if (i <6)
- offset = EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex + i;
- else
- offset = EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex + i - 6;
- usValue = eprom_read(dev, (offset>>1));
- *((u16*)(&EepromTxPower[i])) = usValue;
- }
-
- for(i = 0; i < 12; i++)
- {
- if (i <= 2)
- priv->EEPROMRfACCKChnl1TxPwLevel[i] = EepromTxPower[i];
- else if ((i >=3 )&&(i <= 5))
- priv->EEPROMRfAOfdmChnlTxPwLevel[i-3] = EepromTxPower[i];
- else if ((i >=6 )&&(i <= 8))
- priv->EEPROMRfCCCKChnl1TxPwLevel[i-6] = EepromTxPower[i];
- else
- priv->EEPROMRfCOfdmChnlTxPwLevel[i-9] = EepromTxPower[i];
- }
- }
- else
- {
- priv->EEPROMRfACCKChnl1TxPwLevel[0] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfACCKChnl1TxPwLevel[1] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfACCKChnl1TxPwLevel[2] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfAOfdmChnlTxPwLevel[0] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfAOfdmChnlTxPwLevel[1] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfAOfdmChnlTxPwLevel[2] = EEPROM_Default_TxPowerLevel;
-
- priv->EEPROMRfCCCKChnl1TxPwLevel[0] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfCCCKChnl1TxPwLevel[1] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfCCCKChnl1TxPwLevel[2] = EEPROM_Default_TxPowerLevel;
-
- priv->EEPROMRfCOfdmChnlTxPwLevel[0] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfCOfdmChnlTxPwLevel[1] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfCOfdmChnlTxPwLevel[2] = EEPROM_Default_TxPowerLevel;
- }
- RT_TRACE(COMP_INIT, "priv->EEPROMRfACCKChnl1TxPwLevel[0] = 0x%x\n", priv->EEPROMRfACCKChnl1TxPwLevel[0]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfACCKChnl1TxPwLevel[1] = 0x%x\n", priv->EEPROMRfACCKChnl1TxPwLevel[1]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfACCKChnl1TxPwLevel[2] = 0x%x\n", priv->EEPROMRfACCKChnl1TxPwLevel[2]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfAOfdmChnlTxPwLevel[0] = 0x%x\n", priv->EEPROMRfAOfdmChnlTxPwLevel[0]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfAOfdmChnlTxPwLevel[1] = 0x%x\n", priv->EEPROMRfAOfdmChnlTxPwLevel[1]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfAOfdmChnlTxPwLevel[2] = 0x%x\n", priv->EEPROMRfAOfdmChnlTxPwLevel[2]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfCCCKChnl1TxPwLevel[0] = 0x%x\n", priv->EEPROMRfCCCKChnl1TxPwLevel[0]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfCCCKChnl1TxPwLevel[1] = 0x%x\n", priv->EEPROMRfCCCKChnl1TxPwLevel[1]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfCCCKChnl1TxPwLevel[2] = 0x%x\n", priv->EEPROMRfCCCKChnl1TxPwLevel[2]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfCOfdmChnlTxPwLevel[0] = 0x%x\n", priv->EEPROMRfCOfdmChnlTxPwLevel[0]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfCOfdmChnlTxPwLevel[1] = 0x%x\n", priv->EEPROMRfCOfdmChnlTxPwLevel[1]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfCOfdmChnlTxPwLevel[2] = 0x%x\n", priv->EEPROMRfCOfdmChnlTxPwLevel[2]);
-#endif
-
- }
//
// Update HAL variables.
//
switch(priv->CustomerID)
{
case RT_CID_DEFAULT:
- #ifdef RTL8190P
- priv->LedStrategy = HW_LED;
- #else
- #ifdef RTL8192E
priv->LedStrategy = SW_LED_MODE1;
- #endif
- #endif
break;
case RT_CID_819x_CAMEO:
//break;
default:
- #ifdef RTL8190P
- priv->LedStrategy = HW_LED;
- #else
- #ifdef RTL8192E
priv->LedStrategy = SW_LED_MODE1;
- #endif
- #endif
break;
}
RT_STATUS rtStatus = RT_STATUS_SUCCESS;
//u8 eRFPath;
u8 tmpvalue;
-#ifdef RTL8192E
u8 ICVersion,SwitchingRegulatorOutput;
-#endif
bool bfirmwareok = true;
-#ifdef RTL8190P
- u8 ucRegRead;
-#endif
u32 tmpRegA, tmpRegC, TempCCk;
int i =0;
rtl8192_pci_resetdescring(dev);
// 2007/11/02 MH Before initalizing RF. We can not use FW to do RF-R/W.
priv->Rf_Mode = RF_OP_By_SW_3wire;
-#ifdef RTL8192E
+
//dPLL on
if(priv->ResetProgress == RESET_TYPE_NORESET)
{
// Joseph increae the time to prevent firmware download fail
mdelay(500);
}
-#endif
+
//PlatformSleepUs(10000);
// For any kind of InitializeAdapter process, we shall use system now!!
priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
else
RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)\n", __FUNCTION__, priv->pFirmware->firmware_status);
-#ifdef RTL8190P
- //2008.06.03, for WOL 90 hw bug
- ulRegRead &= (~(CPU_GEN_GPIO_UART));
-#endif
-
write_nic_dword(priv, CPU_GEN, ulRegRead);
//mdelay(100);
-#ifdef RTL8192E
-
//3//
//3 //Fix the issue of E-cut high temperature issue
//3//
write_nic_byte(priv, SWREGULATOR, 0xb8);
}
}
-#endif
-
//3//
//3// Initialize BB before MAC
write_nic_byte(priv, CMDR, CR_RE|CR_TE);
//2Set Tx dma burst
-#ifdef RTL8190P
- write_nic_byte(priv, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
- (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) |
- (1<<MULRW_SHIFT)));
-#else
- #ifdef RTL8192E
write_nic_byte(priv, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
(MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) ));
- #endif
-#endif
+
//set IDR0 here
write_nic_dword(priv, MAC0, ((u32*)dev->dev_addr)[0]);
write_nic_word(priv, MAC4, ((u16*)(dev->dev_addr + 4))[0]);
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
-#ifdef RTL8192E
//Enable Led
write_nic_byte(priv, 0x87, 0x0);
-#endif
-#ifdef RTL8190P
- //2008.06.03, for WOL
- ucRegRead = read_nic_byte(priv, GPE);
- ucRegRead |= BIT0;
- write_nic_byte(priv, GPE, ucRegRead);
-
- ucRegRead = read_nic_byte(priv, GPO);
- ucRegRead &= ~BIT0;
- write_nic_byte(priv, GPO, ucRegRead);
-#endif
//2=======================================================
// RF Power Save
}
}
#endif
- if(1){
-#ifdef RTL8192E
- // We can force firmware to do RF-R/W
- if(priv->ieee80211->FwRWRF)
- priv->Rf_Mode = RF_OP_By_FW;
- else
- priv->Rf_Mode = RF_OP_By_SW_3wire;
-#else
- priv->Rf_Mode = RF_OP_By_SW_3wire;
-#endif
- }
-#ifdef RTL8190P
- if(priv->ResetProgress == RESET_TYPE_NORESET)
- {
- dm_initialize_txpower_tracking(dev);
-
- tmpRegA= rtl8192_QueryBBReg(dev,rOFDM0_XATxIQImbalance,bMaskDWord);
- tmpRegC= rtl8192_QueryBBReg(dev,rOFDM0_XCTxIQImbalance,bMaskDWord);
-
- if(priv->rf_type == RF_2T4R){
- for(i = 0; i<TxBBGainTableLength; i++)
- {
- if(tmpRegA == priv->txbbgain_table[i].txbbgain_value)
- {
- priv->rfa_txpowertrackingindex= (u8)i;
- priv->rfa_txpowertrackingindex_real= (u8)i;
- priv->rfa_txpowertracking_default = priv->rfa_txpowertrackingindex;
- break;
- }
- }
- }
- for(i = 0; i<TxBBGainTableLength; i++)
- {
- if(tmpRegC == priv->txbbgain_table[i].txbbgain_value)
- {
- priv->rfc_txpowertrackingindex= (u8)i;
- priv->rfc_txpowertrackingindex_real= (u8)i;
- priv->rfc_txpowertracking_default = priv->rfc_txpowertrackingindex;
- break;
- }
- }
- TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
+ // We can force firmware to do RF-R/W
+ if(priv->ieee80211->FwRWRF)
+ priv->Rf_Mode = RF_OP_By_FW;
+ else
+ priv->Rf_Mode = RF_OP_By_SW_3wire;
- for(i=0 ; i<CCKTxBBGainTableLength ; i++)
- {
- if(TempCCk == priv->cck_txbbgain_table[i].ccktxbb_valuearray[0])
- {
- priv->CCKPresentAttentuation_20Mdefault =(u8) i;
- break;
- }
- }
- priv->CCKPresentAttentuation_40Mdefault = 0;
- priv->CCKPresentAttentuation_difference = 0;
- priv->CCKPresentAttentuation = priv->CCKPresentAttentuation_20Mdefault;
- RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_initial = %d\n", priv->rfa_txpowertrackingindex);
- RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real__initial = %d\n", priv->rfa_txpowertrackingindex_real);
- RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_initial = %d\n", priv->rfc_txpowertrackingindex);
- RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real_initial = %d\n", priv->rfc_txpowertrackingindex_real);
- RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference_initial = %d\n", priv->CCKPresentAttentuation_difference);
- RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_initial = %d\n", priv->CCKPresentAttentuation);
- }
-#else
- #ifdef RTL8192E
if(priv->ResetProgress == RESET_TYPE_NORESET)
{
dm_initialize_txpower_tracking(dev);
priv->btxpower_tracking = FALSE;//TEMPLY DISABLE
}
}
- #endif
-#endif
+
rtl8192_irq_enable(dev);
priv->being_init_adapter = false;
return rtStatus;
return -1;
}
RT_TRACE(COMP_INIT, "start adapter finished\n");
-#ifdef RTL8192E
+
if(priv->ieee80211->eRFPowerState!=eRfOn)
MgntActSet_RF_State(dev, eRfOn, priv->ieee80211->RfOffReason);
-#endif
+
if(priv->ieee80211->state != IEEE80211_LINKED)
ieee80211_softmac_start_protocol(priv->ieee80211);
ieee80211_reset_queue(priv->ieee80211);
return signal_power;
}
-static void
-rtl8190_process_cck_rxpathsel(
- struct r8192_priv * priv,
- struct ieee80211_rx_stats * pprevious_stats
- )
-{
-#ifdef RTL8190P //Only 90P 2T4R need to check
- char last_cck_adc_pwdb[4]={0,0,0,0};
- u8 i;
-//cosa add for Rx path selection
- if(priv->rf_type == RF_2T4R && DM_RxPathSelTable.Enable)
- {
- if(pprevious_stats->bIsCCK &&
- (pprevious_stats->bPacketToSelf ||pprevious_stats->bPacketBeacon))
- {
- /* record the cck adc_pwdb to the sliding window. */
- if(priv->stats.cck_adc_pwdb.TotalNum++ >= PHY_RSSI_SLID_WIN_MAX)
- {
- priv->stats.cck_adc_pwdb.TotalNum = PHY_RSSI_SLID_WIN_MAX;
- for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
- {
- last_cck_adc_pwdb[i] = priv->stats.cck_adc_pwdb.elements[i][priv->stats.cck_adc_pwdb.index];
- priv->stats.cck_adc_pwdb.TotalVal[i] -= last_cck_adc_pwdb[i];
- }
- }
- for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
- {
- priv->stats.cck_adc_pwdb.TotalVal[i] += pprevious_stats->cck_adc_pwdb[i];
- priv->stats.cck_adc_pwdb.elements[i][priv->stats.cck_adc_pwdb.index] = pprevious_stats->cck_adc_pwdb[i];
- }
- priv->stats.cck_adc_pwdb.index++;
- if(priv->stats.cck_adc_pwdb.index >= PHY_RSSI_SLID_WIN_MAX)
- priv->stats.cck_adc_pwdb.index = 0;
-
- for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
- {
- DM_RxPathSelTable.cck_pwdb_sta[i] = priv->stats.cck_adc_pwdb.TotalVal[i]/priv->stats.cck_adc_pwdb.TotalNum;
- }
-
- for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
- {
- if(pprevious_stats->cck_adc_pwdb[i] > (char)priv->undecorated_smoothed_cck_adc_pwdb[i])
- {
- priv->undecorated_smoothed_cck_adc_pwdb[i] =
- ( (priv->undecorated_smoothed_cck_adc_pwdb[i]*(Rx_Smooth_Factor-1)) +
- (pprevious_stats->cck_adc_pwdb[i])) /(Rx_Smooth_Factor);
- priv->undecorated_smoothed_cck_adc_pwdb[i] = priv->undecorated_smoothed_cck_adc_pwdb[i] + 1;
- }
- else
- {
- priv->undecorated_smoothed_cck_adc_pwdb[i] =
- ( (priv->undecorated_smoothed_cck_adc_pwdb[i]*(Rx_Smooth_Factor-1)) +
- (pprevious_stats->cck_adc_pwdb[i])) /(Rx_Smooth_Factor);
- }
- }
- }
- }
-#endif
-}
-
-
/* 2008/01/22 MH We can not delcare RSSI/EVM total value of sliding window to
be a local static. Otherwise, it may increase when we return from S3/S4. The
value will be kept in memory or disk. We must delcare the value in adapter
if(!bcheck)
return;
- rtl8190_process_cck_rxpathsel(priv,pprevious_stats);
-
// <2> Showed on UI for engineering
// hardware does not provide rssi information for each rf path in CCK
if(!pprevious_stats->bIsCCK && pprevious_stats->bPacketToSelf)
// (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
//
u8 report;//, cck_agc_rpt;
-#ifdef RTL8190P
- u8 tmp_pwdb;
- char cck_adc_pwdb[4];
-#endif
-
-#ifdef RTL8190P //Only 90P 2T4R need to check
- if(priv->rf_type == RF_2T4R && DM_RxPathSelTable.Enable && bpacket_match_bssid)
- {
- for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
- {
- tmp_pwdb = pcck_buf->adc_pwdb_X[i];
- cck_adc_pwdb[i] = (char)tmp_pwdb;
- cck_adc_pwdb[i] /= 2;
- pstats->cck_adc_pwdb[i] = precord_stats->cck_adc_pwdb[i] = cck_adc_pwdb[i];
- }
- }
-#endif
if (!priv->phy_reg824_bit9)
{
//Fixed by Jacken from Bryant 2008-03-20
//Original value is 106
-#ifdef RTL8190P //Modify by Jacken 2008/03/31
- rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 106;
-#else
rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 110;
-#endif
//Get Rx snr value in DB
tmp_rxsnr = pofdm_buf->rxsnr_X[i];
cancel_delayed_work(&priv->update_beacon_wq);
cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
-#ifdef RTL8192E
cancel_delayed_work(&priv->gpio_change_rf_wq);
-#endif
cancel_work_sync(&priv->reset_wq);
cancel_work_sync(&priv->qos_activate);
//cancel_work_sync(&priv->SetBWModeWorkItem);
//
// Indicate different AP vendor for IOT issue.
//
-#ifdef RTL8190P
-static const u32 edca_setting_DL[HT_IOT_PEER_MAX] =
-{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322, 0x5e4322};
-static const u32 edca_setting_UL[HT_IOT_PEER_MAX] =
-{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322, 0x5e4322};
-#else
-#ifdef RTL8192E
static const u32 edca_setting_DL[HT_IOT_PEER_MAX] =
{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322, 0x5e4322};
static const u32 edca_setting_UL[HT_IOT_PEER_MAX] =
{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322, 0x5e4322};
-#else
-static const u32 edca_setting_DL[HT_IOT_PEER_MAX] =
-{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f, 0x5e4322};
-static const u32 edca_setting_UL[HT_IOT_PEER_MAX] =
-{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f, 0x5e4322};
-#endif
-#endif
#define RTK_UL_EDCA 0xa44f
#define RTK_DL_EDCA 0x5e4322
extern void dm_check_fsync(struct net_device *dev);
extern void dm_initialize_txpower_tracking(struct net_device *dev);
-#ifdef RTL8192E
extern void dm_gpio_change_rf_callback(struct work_struct *work);
-#endif
// DM --> Rate Adaptive
// DM --> TX power control
static void dm_check_txpower_tracking(struct net_device *dev);
-// DM --> BB init gain restore
-#ifndef RTL8192U
-static void dm_bb_initialgain_restore(struct net_device *dev);
-
-// DM --> BB init gain backup
-static void dm_bb_initialgain_backup(struct net_device *dev);
-#endif
-
// DM --> Dynamic Init Gain by RSSI
static void dm_dig_init(struct net_device *dev);
static void dm_ctrl_initgain_byrssi(struct net_device *dev);
dm_init_fsync(dev);
dm_init_rxpath_selection(dev);
dm_init_ctstoself(dev);
-#ifdef RTL8192E
INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, dm_gpio_change_rf_callback);
-#endif
}
}
//OFDM default at 0db, index=6.
-#ifndef RTL8190P
static const u32 OFDMSwingTable[OFDM_Table_Length] = {
0x7f8001fe, // 0, +6db
0x71c001c7, // 1, +5db
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 10, -10db
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} // 11, -11db
};
-#endif
+
#define Pw_Track_Flag 0x11d
#define Tssi_Mea_Value 0x13c
#define Tssi_Report_Value1 0x134
u32 Value;
u8 Pwr_Flag;
u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver=0;
-#ifdef RTL8192U
- RT_STATUS rtStatus = RT_STATUS_SUCCESS;
-#endif
// bool rtStatus = true;
u32 delta=0;
RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING;
tx_cmd.Length = 4;
tx_cmd.Value = Value;
-#ifdef RTL8192U
- rtStatus = SendTxCommandPacket(dev, &tx_cmd, 12);
- if (rtStatus == RT_STATUS_FAILURE)
- {
- RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
- }
-#else
cmpk_message_handle_tx(dev, (u8*)&tx_cmd, DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
-#endif
mdelay(1);
for(i = 0;i <= 30; i++)
RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
-#ifdef RTL8190P
- RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
- RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
-#endif
RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
return;
}
RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
-#ifdef RTL8190P
- RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
- RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
-#endif
RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
priv->ieee80211->bdynamic_txpower_enable = TRUE;
write_nic_byte(priv, Pw_Track_Flag, 0);
}
-#ifndef RTL8190P
+
static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
{
#define ThermalMeterVal 9
}
priv->txpower_count = 0;
}
-#endif
+
void dm_txpower_trackingcallback(struct work_struct *work)
{
struct delayed_work *dwork = container_of(work,struct delayed_work,work);
struct r8192_priv *priv = container_of(dwork,struct r8192_priv,txpower_tracking_wq);
struct net_device *dev = priv->ieee80211->dev;
-#ifdef RTL8190P
- dm_TXPowerTrackingCallback_TSSI(dev);
-#else
- //if(priv->bDcut == TRUE)
if(priv->IC_Cut >= IC_VersionCut_D)
dm_TXPowerTrackingCallback_TSSI(dev);
else
dm_TXPowerTrackingCallback_ThermalMeter(dev);
-#endif
}
priv->btxpower_trackingInit = FALSE;
}
-#ifndef RTL8190P
+
static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
priv->txpower_count = 0;
priv->btxpower_trackingInit = FALSE;
}
-#endif
void dm_initialize_txpower_tracking(struct net_device *dev)
{
-#ifndef RTL8190P
struct r8192_priv *priv = ieee80211_priv(dev);
-#endif
-#ifdef RTL8190P
- dm_InitializeTXPowerTracking_TSSI(dev);
-#else
+
if(priv->IC_Cut >= IC_VersionCut_D)
dm_InitializeTXPowerTracking_TSSI(dev);
else
dm_InitializeTXPowerTracking_ThermalMeter(dev);
-#endif
}
}
}
-#ifndef RTL8190P
static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
TM_Trigger = 0;
}
}
-#endif
static void dm_check_txpower_tracking(struct net_device *dev)
{
-#ifndef RTL8190P
struct r8192_priv *priv = ieee80211_priv(dev);
- //static u32 tx_power_track_counter = 0;
-#endif
-#ifdef RTL8190P
- dm_CheckTXPowerTracking_TSSI(dev);
-#else
- //if(priv->bDcut == TRUE)
+
if(priv->IC_Cut >= IC_VersionCut_D)
dm_CheckTXPowerTracking_TSSI(dev);
else
dm_CheckTXPowerTracking_ThermalMeter(dev);
-#endif
-
}
}
-#ifndef RTL8190P
+
static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14)
{
u32 TempVal;
rCCK0_DebugPort, TempVal);
}
}
-#endif
-
void dm_cck_txpower_adjust(struct net_device *dev, bool binch14)
{
-#ifndef RTL8190P
struct r8192_priv *priv = ieee80211_priv(dev);
-#endif
-#ifdef RTL8190P
- dm_CCKTxPowerAdjust_TSSI(dev, binch14);
-#else
+
if(priv->IC_Cut >= IC_VersionCut_D)
dm_CCKTxPowerAdjust_TSSI(dev, binch14);
else
dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14);
-#endif
-}
-
-
-#ifndef RTL8192U
-static void dm_txpower_reset_recovery(
- struct net_device *dev
-)
-{
- struct r8192_priv *priv = ieee80211_priv(dev);
-
- RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
- rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
- RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
- RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",priv->rfa_txpowertrackingindex);
- RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);
- RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n",priv->CCKPresentAttentuation);
- dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
-
- rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
- RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
- RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv->rfc_txpowertrackingindex);
- RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);
-
}
-void dm_restore_dynamic_mechanism_state(struct net_device *dev)
-{
- struct r8192_priv *priv = ieee80211_priv(dev);
- u32 reg_ratr = priv->rate_adaptive.last_ratr;
-
- if(!priv->up)
- {
- RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
- return;
- }
-
- //
- // Restore previous state for rate adaptive
- //
- if(priv->rate_adaptive.rate_adaptive_disabled)
- return;
- // TODO: Only 11n mode is implemented currently,
- if( !(priv->ieee80211->mode==WIRELESS_MODE_N_24G ||
- priv->ieee80211->mode==WIRELESS_MODE_N_5G))
- return;
- {
- /* 2007/11/15 MH Copy from 8190PCI. */
- u32 ratr_value;
- ratr_value = reg_ratr;
- if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled
- {
- ratr_value &=~ (RATE_ALL_OFDM_2SS);
- }
- write_nic_dword(priv, RATR0, ratr_value);
- write_nic_byte(priv, UFWP, 1);
- }
- //Resore TX Power Tracking Index
- if(priv->btxpower_trackingInit && priv->btxpower_tracking){
- dm_txpower_reset_recovery(dev);
- }
-
- //
- //Restore BB Initial Gain
- //
- dm_bb_initialgain_restore(dev);
-
-}
-
-static void dm_bb_initialgain_restore(struct net_device *dev)
-{
- struct r8192_priv *priv = ieee80211_priv(dev);
- u32 bit_mask = 0x7f; //Bit0~ Bit6
-
- if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
- return;
-
- //Disable Initial Gain
- //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
- rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
- rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
- rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
- rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);
- rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
- bit_mask = bMaskByte2;
- rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);
-
- RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
- RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
- RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
- RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
- RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
- //Enable Initial Gain
- //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);
- rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
-
-}
-
-
-void dm_backup_dynamic_mechanism_state(struct net_device *dev)
-{
- struct r8192_priv *priv = ieee80211_priv(dev);
-
- // Fsync to avoid reset
- priv->bswitch_fsync = false;
- //Backup BB InitialGain
- dm_bb_initialgain_backup(dev);
-
-}
-
-
-static void dm_bb_initialgain_backup(struct net_device *dev)
-{
- struct r8192_priv *priv = ieee80211_priv(dev);
- u32 bit_mask = bMaskByte0; //Bit0~ Bit6
-
- if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
- return;
-
- //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
- rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
- priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
- priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
- priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);
- priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
- bit_mask = bMaskByte2;
- priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);
-
- RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
- RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
- RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
- RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
- RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
-
-}
-
-#endif
void dm_change_dynamic_initgain_thresh(struct net_device *dev, u32 dm_type, u32 dm_value)
{
{
/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
- #ifdef RTL8190P
- write_nic_byte(priv, rOFDM0_RxDetector1, 0x40);
- #else
- write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);
- #endif
- /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
- write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
- */
- //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
-
-
- //else
- //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);
}
else
write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
{
/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
- #ifdef RTL8190P
- write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
- #else
- write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
- #endif
- /*
- else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
- */
- //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
-
- //else
- //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
}
else
write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);
// 3.1 Higher PD_TH for OFDM for high power state.
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
{
- #ifdef RTL8190P
- write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
- #else
- write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);
- #endif
-
- /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
- write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
- */
-
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);
}
else
write_nic_byte(priv, rOFDM0_RxDetector1, 0x43);
// 3.2 Recover PD_TH for OFDM for normal power region.
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
{
- #ifdef RTL8190P
- write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
- #else
- write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
- #endif
- /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
- write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
- */
-
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
}
else
write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);
{
/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
- #ifdef RTL8190P
- write_nic_byte(priv, rOFDM0_RxDetector1, 0x40);
- #else
- write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);
- #endif
- /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
- */
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);
}
else
write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
{
/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
- #ifdef RTL8190P
- write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
- #else
- write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
- #endif
- /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
- write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
- */
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
}
else
write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);
// Higher PD_TH for OFDM for high power state.
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
{
- #ifdef RTL8190P
- write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
- #else
- write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);
- #endif
- /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
- write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
- */
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);
}
else
write_nic_byte(priv, rOFDM0_RxDetector1, 0x43);
/* Copy 8187B template for 9xseries */
static void dm_check_rfctrl_gpio(struct net_device * dev)
{
-#ifdef RTL8192E
struct r8192_priv *priv = ieee80211_priv(dev);
-#endif
// Walk around for DTM test, we will not enable HW - radio on/off because r/w
// page 1 register before Lextra bus is enabled cause system fails when resuming
// from S4. 20080218, Emily
// Stop to execute workitem to prevent S3/S4 bug.
-#ifdef RTL8190P
- return;
-#endif
-#ifdef RTL8192U
- return;
-#endif
-#ifdef RTL8192E
- queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0);
-#endif
-
+ queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0);
}
/* Check if PBC button is pressed. */
static void dm_check_pbc_gpio(struct net_device *dev)
{
-#ifdef RTL8192U
- struct r8192_priv *priv = ieee80211_priv(dev);
- u8 tmp1byte;
-
-
- tmp1byte = read_nic_byte(priv, GPI);
- if(tmp1byte == 0xff)
- return;
-
- if (tmp1byte&BIT6 || tmp1byte&BIT0)
- {
- // Here we only set bPbcPressed to TRUE
- // After trigger PBC, the variable will be set to FALSE
- RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
- }
-#endif
-
}
-#ifdef RTL8192E
-
/* PCI will not support workitem call back HW radio on-off control. */
void dm_gpio_change_rf_callback(struct work_struct *work)
{
}
}
-#endif
-
/* Check if Current RF RX path is enabled */
void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
{
priv->ieee80211->fsync_time_interval = 500;
priv->ieee80211->fsync_rate_bitmap = 0x0f000800;
priv->ieee80211->fsync_rssi_threshold = 30;
-#ifdef RTL8190P
- priv->ieee80211->bfsync_enable = true;
-#else
priv->ieee80211->bfsync_enable = false;
-#endif
priv->ieee80211->fsync_multiple_timeinterval = 3;
priv->ieee80211->fsync_firstdiff_ratethreshold= 100;
priv->ieee80211->fsync_seconddiff_ratethreshold= 200;
priv->bswitch_fsync = !priv->bswitch_fsync;
if(priv->bswitch_fsync)
{
- #ifdef RTL8190P
- write_nic_byte(priv,0xC36, 0x00);
- #else
write_nic_byte(priv,0xC36, 0x1c);
- #endif
write_nic_byte(priv, 0xC3e, 0x90);
}
else
{
- #ifdef RTL8190P
- write_nic_byte(priv, 0xC36, 0x40);
- #else
write_nic_byte(priv, 0xC36, 0x5c);
- #endif
write_nic_byte(priv, 0xC3e, 0x96);
}
}
if(priv->bswitch_fsync)
{
priv->bswitch_fsync = false;
- #ifdef RTL8190P
- write_nic_byte(priv, 0xC36, 0x40);
- #else
write_nic_byte(priv, 0xC36, 0x5c);
- #endif
write_nic_byte(priv, 0xC3e, 0x96);
}
}
if(priv->bswitch_fsync)
{
priv->bswitch_fsync = false;
- #ifdef RTL8190P
- write_nic_byte(priv, 0xC36, 0x40);
- #else
write_nic_byte(priv, 0xC36, 0x5c);
- #endif
write_nic_byte(priv, 0xC3e, 0x96);
}
priv->ContiuneDiffCount = 0;
- #ifdef RTL8190P
- write_nic_dword(priv, rOFDM0_RxDetector2, 0x164052cd);
- #else
write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);
- #endif
}
RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount);
RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
{
priv->bswitch_fsync = false;
- #ifdef RTL8190P
- write_nic_byte(priv, 0xC36, 0x40);
- #else
- write_nic_byte(priv, 0xC36, 0x5c);
-#endif
+ write_nic_byte(priv, 0xC36, 0x40);
write_nic_byte(priv, 0xC3e, 0x96);
}
priv->ContiuneDiffCount = 0;
-#ifndef RTL8190P
- write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);
-#endif
+ write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);
}
static void dm_StartSWFsync(struct net_device *dev)
priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
add_timer(&priv->fsync_timer);
-#ifndef RTL8190P
write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c12cd);
-#endif
-
}
static void dm_EndHWFsync(struct net_device *dev)
{
if(reg_c38_State != RegC38_Fsync_AP_BCM)
{ //For broadcom AP we write different default value
- #ifdef RTL8190P
- write_nic_byte(priv, rOFDM0_RxDetector3, 0x15);
- #else
- write_nic_byte(priv, rOFDM0_RxDetector3, 0x95);
- #endif
+ write_nic_byte(priv, rOFDM0_RxDetector3, 0x95);
reg_c38_State = RegC38_Fsync_AP_BCM;
}
{
if(reg_c38_State != RegC38_NonFsync_Other_AP)
{
- #ifdef RTL8190P
- write_nic_byte(priv, rOFDM0_RxDetector3, 0x10);
- #else
- write_nic_byte(priv, rOFDM0_RxDetector3, 0x90);
- #endif
+ write_nic_byte(priv, rOFDM0_RxDetector3, 0x90);
reg_c38_State = RegC38_NonFsync_Other_AP;
}
#define EEPROM_Default_TxPower 0x1010
#define EEPROM_ICVersion_ChannelPlan 0x7C //0x7C:ChannelPlan, 0x7D:IC_Version
#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID
-#ifdef RTL8190P
-#define EEPROM_RFInd_PowerDiff 0x14
-#define EEPROM_ThermalMeter 0x15
-#define EEPROM_TxPwDiff_CrystalCap 0x16
-#define EEPROM_TxPwIndex_CCK 0x18 //0x18~0x25
-#define EEPROM_TxPwIndex_OFDM_24G 0x26 //0x26~0x33
-#define EEPROM_TxPwIndex_OFDM_5G 0x34 //0x34~0x7B
-#define EEPROM_C56_CrystalCap 0x17 //0x17
-#define EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex 0x80 //0x80
-#define EEPROM_C56_RfA_HT_OFDM_TxPwIndex 0x81 //0x81~0x83
-#define EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex 0xbc //0xb8
-#define EEPROM_C56_RfC_HT_OFDM_TxPwIndex 0xb9 //0xb9~0xbb
-#else
-#ifdef RTL8192E
+
#define EEPROM_RFInd_PowerDiff 0x28
#define EEPROM_ThermalMeter 0x29
#define EEPROM_TxPwDiff_CrystalCap 0x2A //0x2A~0x2B
#define EEPROM_TxPwIndex_CCK 0x2C //0x23
#define EEPROM_TxPwIndex_OFDM_24G 0x3A //0x24~0x26
-#endif
-#endif
+
#define EEPROM_Default_TxPowerLevel 0x10
//#define EEPROM_ChannelPlan 0x7c //0x7C
#define EEPROM_IC_VER 0x7d //0x7D
{
struct net_device *dev = pci_get_drvdata(pdev);
struct r8192_priv *priv = ieee80211_priv(dev);
-#ifdef RTL8190P
- u8 ucRegRead;
-#endif
u32 ulRegRead;
RT_TRACE(COMP_POWER, "============> r8192E suspend call.\n");
write_nic_dword(priv, WFCRC0, 0xffffffff);
write_nic_dword(priv, WFCRC1, 0xffffffff);
write_nic_dword(priv, WFCRC2, 0xffffffff);
-#ifdef RTL8190P
- //GPIO 0 = TRUE
- ucRegRead = read_nic_byte(priv, GPO);
- ucRegRead |= BIT0;
- write_nic_byte(priv, GPO, ucRegRead);
-#endif
//Write PMR register
write_nic_byte(priv, PMR, 0x5);
//Disable tx, enanble rx
{
RT_STATUS rt_status = RT_STATUS_SUCCESS;
-#ifdef RTL8192U
- return rt_status;
-#else
struct r8192_priv *priv = ieee80211_priv(dev);
u16 frag_threshold;
u16 frag_length = 0, frag_offset = 0;
/* Allocate skb buffer to contain firmware info and tx descriptor info
* add 4 to avoid packet appending overflow.
* */
-#ifdef RTL8192U
- skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + frag_length + 4);
-#else
skb = dev_alloc_skb(frag_length + priv->ieee80211->tx_headroom + 4);
-#endif
if(skb == NULL) {
rt_status = RT_STATUS_FAILURE;
goto Failed;
tcb_desc->bLastIniPkt = bLastIniPkt;
tcb_desc->pkt_size = frag_length;
-#ifdef RTL8192U
- skb_reserve(skb, USB_HWDESC_HEADER_LEN);
-#endif
-
//seg_ptr = skb_put(skb, frag_length + priv->ieee80211->tx_headroom);
seg_ptr = skb_put(skb, priv->ieee80211->tx_headroom);
Failed:
//spin_unlock_irqrestore(&priv->tx_lock,flags);
return rt_status;
-
-
-#endif
}
static void
0x0e5c, //2472 13
0x0f72, //2484
};
-#ifdef RTL8190P
-u32 Rtl8190PciMACPHY_Array[] = {
-0x03c,0xffff0000,0x00000f0f,
-0x340,0xffffffff,0x161a1a1a,
-0x344,0xffffffff,0x12121416,
-0x348,0x0000ffff,0x00001818,
-0x12c,0xffffffff,0x04000802,
-0x318,0x00000fff,0x00000800,
-};
-u32 Rtl8190PciMACPHY_Array_PG[] = {
-0x03c,0xffff0000,0x00000f0f,
-0x340,0xffffffff,0x0a0c0d0f,
-0x344,0xffffffff,0x06070809,
-0x344,0xffffffff,0x06070809,
-0x348,0x0000ffff,0x00000000,
-0x12c,0xffffffff,0x04000802,
-0x318,0x00000fff,0x00000800,
-};
-
-u32 Rtl8190PciAGCTAB_Array[AGCTAB_ArrayLength] = {
-0xc78,0x7d000001,
-0xc78,0x7d010001,
-0xc78,0x7d020001,
-0xc78,0x7d030001,
-0xc78,0x7c040001,
-0xc78,0x7b050001,
-0xc78,0x7a060001,
-0xc78,0x79070001,
-0xc78,0x78080001,
-0xc78,0x77090001,
-0xc78,0x760a0001,
-0xc78,0x750b0001,
-0xc78,0x740c0001,
-0xc78,0x730d0001,
-0xc78,0x720e0001,
-0xc78,0x710f0001,
-0xc78,0x70100001,
-0xc78,0x6f110001,
-0xc78,0x6e120001,
-0xc78,0x6d130001,
-0xc78,0x6c140001,
-0xc78,0x6b150001,
-0xc78,0x6a160001,
-0xc78,0x69170001,
-0xc78,0x68180001,
-0xc78,0x67190001,
-0xc78,0x661a0001,
-0xc78,0x651b0001,
-0xc78,0x641c0001,
-0xc78,0x491d0001,
-0xc78,0x481e0001,
-0xc78,0x471f0001,
-0xc78,0x46200001,
-0xc78,0x45210001,
-0xc78,0x44220001,
-0xc78,0x43230001,
-0xc78,0x28240001,
-0xc78,0x27250001,
-0xc78,0x26260001,
-0xc78,0x25270001,
-0xc78,0x24280001,
-0xc78,0x23290001,
-0xc78,0x222a0001,
-0xc78,0x212b0001,
-0xc78,0x202c0001,
-0xc78,0x0a2d0001,
-0xc78,0x082e0001,
-0xc78,0x062f0001,
-0xc78,0x05300001,
-0xc78,0x04310001,
-0xc78,0x03320001,
-0xc78,0x02330001,
-0xc78,0x01340001,
-0xc78,0x00350001,
-0xc78,0x00360001,
-0xc78,0x00370001,
-0xc78,0x00380001,
-0xc78,0x00390001,
-0xc78,0x003a0001,
-0xc78,0x003b0001,
-0xc78,0x003c0001,
-0xc78,0x003d0001,
-0xc78,0x003e0001,
-0xc78,0x003f0001,
-0xc78,0x7d400001,
-0xc78,0x7d410001,
-0xc78,0x7d420001,
-0xc78,0x7d430001,
-0xc78,0x7c440001,
-0xc78,0x7b450001,
-0xc78,0x7a460001,
-0xc78,0x79470001,
-0xc78,0x78480001,
-0xc78,0x77490001,
-0xc78,0x764a0001,
-0xc78,0x754b0001,
-0xc78,0x744c0001,
-0xc78,0x734d0001,
-0xc78,0x724e0001,
-0xc78,0x714f0001,
-0xc78,0x70500001,
-0xc78,0x6f510001,
-0xc78,0x6e520001,
-0xc78,0x6d530001,
-0xc78,0x6c540001,
-0xc78,0x6b550001,
-0xc78,0x6a560001,
-0xc78,0x69570001,
-0xc78,0x68580001,
-0xc78,0x67590001,
-0xc78,0x665a0001,
-0xc78,0x655b0001,
-0xc78,0x645c0001,
-0xc78,0x495d0001,
-0xc78,0x485e0001,
-0xc78,0x475f0001,
-0xc78,0x46600001,
-0xc78,0x45610001,
-0xc78,0x44620001,
-0xc78,0x43630001,
-0xc78,0x28640001,
-0xc78,0x27650001,
-0xc78,0x26660001,
-0xc78,0x25670001,
-0xc78,0x24680001,
-0xc78,0x23690001,
-0xc78,0x226a0001,
-0xc78,0x216b0001,
-0xc78,0x206c0001,
-0xc78,0x0a6d0001,
-0xc78,0x086e0001,
-0xc78,0x066f0001,
-0xc78,0x05700001,
-0xc78,0x04710001,
-0xc78,0x03720001,
-0xc78,0x02730001,
-0xc78,0x01740001,
-0xc78,0x00750001,
-0xc78,0x00760001,
-0xc78,0x00770001,
-0xc78,0x00780001,
-0xc78,0x00790001,
-0xc78,0x007a0001,
-0xc78,0x007b0001,
-0xc78,0x007c0001,
-0xc78,0x007d0001,
-0xc78,0x007e0001,
-0xc78,0x007f0001,
-0xc78,0x3600001e,
-0xc78,0x3601001e,
-0xc78,0x3602001e,
-0xc78,0x3603001e,
-0xc78,0x3604001e,
-0xc78,0x3605001e,
-0xc78,0x3a06001e,
-0xc78,0x3c07001e,
-0xc78,0x3e08001e,
-0xc78,0x4209001e,
-0xc78,0x430a001e,
-0xc78,0x450b001e,
-0xc78,0x470c001e,
-0xc78,0x480d001e,
-0xc78,0x490e001e,
-0xc78,0x4b0f001e,
-0xc78,0x4c10001e,
-0xc78,0x4d11001e,
-0xc78,0x4d12001e,
-0xc78,0x4e13001e,
-0xc78,0x4f14001e,
-0xc78,0x5015001e,
-0xc78,0x5116001e,
-0xc78,0x5117001e,
-0xc78,0x5218001e,
-0xc78,0x5219001e,
-0xc78,0x531a001e,
-0xc78,0x541b001e,
-0xc78,0x541c001e,
-0xc78,0x551d001e,
-0xc78,0x561e001e,
-0xc78,0x561f001e,
-0xc78,0x5720001e,
-0xc78,0x5821001e,
-0xc78,0x5822001e,
-0xc78,0x5923001e,
-0xc78,0x5924001e,
-0xc78,0x5a25001e,
-0xc78,0x5b26001e,
-0xc78,0x5b27001e,
-0xc78,0x5c28001e,
-0xc78,0x5c29001e,
-0xc78,0x5d2a001e,
-0xc78,0x5d2b001e,
-0xc78,0x5e2c001e,
-0xc78,0x5e2d001e,
-0xc78,0x5f2e001e,
-0xc78,0x602f001e,
-0xc78,0x6030001e,
-0xc78,0x6131001e,
-0xc78,0x6132001e,
-0xc78,0x6233001e,
-0xc78,0x6234001e,
-0xc78,0x6335001e,
-0xc78,0x6336001e,
-0xc78,0x6437001e,
-0xc78,0x6538001e,
-0xc78,0x6639001e,
-0xc78,0x663a001e,
-0xc78,0x673b001e,
-0xc78,0x683c001e,
-0xc78,0x693d001e,
-0xc78,0x6a3e001e,
-0xc78,0x6b3f001e,
-};
-
-u32 Rtl8190PciPHY_REGArray[PHY_REGArrayLength] = {
-0x800,0x00050060,
-0x804,0x00000005,
-0x808,0x0000fc00,
-0x80c,0x0000001c,
-0x810,0x801010aa,
-0x814,0x000908c0,
-0x818,0x00000000,
-0x81c,0x00000000,
-0x820,0x00000004,
-0x824,0x00690000,
-0x828,0x00000004,
-0x82c,0x00e90000,
-0x830,0x00000004,
-0x834,0x00690000,
-0x838,0x00000004,
-0x83c,0x00e90000,
-0x840,0x00000000,
-0x844,0x00000000,
-0x848,0x00000000,
-0x84c,0x00000000,
-0x850,0x00000000,
-0x854,0x00000000,
-0x858,0x65a965a9,
-0x85c,0x65a965a9,
-0x860,0x001f0010,
-0x864,0x007f0010,
-0x868,0x001f0010,
-0x86c,0x007f0010,
-0x870,0x0f100f70,
-0x874,0x0f100f70,
-0x878,0x00000000,
-0x87c,0x00000000,
-0x880,0x5c385eb8,
-0x884,0x6357060d,
-0x888,0x0460c341,
-0x88c,0x0000ff00,
-0x890,0x00000000,
-0x894,0xfffffffe,
-0x898,0x4c42382f,
-0x89c,0x00656056,
-0x8b0,0x00000000,
-0x8e0,0x00000000,
-0x8e4,0x00000000,
-0x900,0x00000000,
-0x904,0x00000023,
-0x908,0x00000000,
-0x90c,0x35541545,
-0xa00,0x00d0c7d8,
-0xa04,0xab1f0008,
-0xa08,0x80cd8300,
-0xa0c,0x2e62740f,
-0xa10,0x95009b78,
-0xa14,0x11145008,
-0xa18,0x00881117,
-0xa1c,0x89140fa0,
-0xa20,0x1a1b0000,
-0xa24,0x090e1317,
-0xa28,0x00000204,
-0xa2c,0x00000000,
-0xc00,0x00000040,
-0xc04,0x0000500f,
-0xc08,0x000000e4,
-0xc0c,0x6c6c6c6c,
-0xc10,0x08000000,
-0xc14,0x40000100,
-0xc18,0x08000000,
-0xc1c,0x40000100,
-0xc20,0x08000000,
-0xc24,0x40000100,
-0xc28,0x08000000,
-0xc2c,0x40000100,
-0xc30,0x6de9ac44,
-0xc34,0x164052cd,
-0xc38,0x00070a14,
-0xc3c,0x0a969764,
-0xc40,0x1f7c403f,
-0xc44,0x000100b7,
-0xc48,0xec020000,
-0xc4c,0x00000300,
-0xc50,0x69543420,
-0xc54,0x433c0094,
-0xc58,0x69543420,
-0xc5c,0x433c0094,
-0xc60,0x69543420,
-0xc64,0x433c0094,
-0xc68,0x69543420,
-0xc6c,0x433c0094,
-0xc70,0x2c7f000d,
-0xc74,0x0186175b,
-0xc78,0x0000001f,
-0xc7c,0x00b91612,
-0xc80,0x40000100,
-0xc84,0x00000000,
-0xc88,0x40000100,
-0xc8c,0x08000000,
-0xc90,0x40000100,
-0xc94,0x00000000,
-0xc98,0x40000100,
-0xc9c,0x00000000,
-0xca0,0x00492492,
-0xca4,0x00000000,
-0xca8,0x00000000,
-0xcac,0x00000000,
-0xcb0,0x00000000,
-0xcb4,0x00000000,
-0xcb8,0x00000000,
-0xcbc,0x00492492,
-0xcc0,0x00000000,
-0xcc4,0x00000000,
-0xcc8,0x00000000,
-0xccc,0x00000000,
-0xcd0,0x00000000,
-0xcd4,0x00000000,
-0xcd8,0x64b22427,
-0xcdc,0x00766932,
-0xce0,0x00222222,
-0xd00,0x00000740,
-0xd04,0x0000040f,
-0xd08,0x0000803f,
-0xd0c,0x00000001,
-0xd10,0xa0633333,
-0xd14,0x33333c63,
-0xd18,0x6a8f5b6b,
-0xd1c,0x00000000,
-0xd20,0x00000000,
-0xd24,0x00000000,
-0xd28,0x00000000,
-0xd2c,0xcc979975,
-0xd30,0x00000000,
-0xd34,0x00000000,
-0xd38,0x00000000,
-0xd3c,0x00027293,
-0xd40,0x00000000,
-0xd44,0x00000000,
-0xd48,0x00000000,
-0xd4c,0x00000000,
-0xd50,0x6437140a,
-0xd54,0x024dbd02,
-0xd58,0x00000000,
-0xd5c,0x14032064,
-};
-u32 Rtl8190PciPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
-0x800,0x00050060,
-0x804,0x00000004,
-0x808,0x0000fc00,
-0x80c,0x0000001c,
-0x810,0x801010aa,
-0x814,0x000908c0,
-0x818,0x00000000,
-0x81c,0x00000000,
-0x820,0x00000004,
-0x824,0x00690000,
-0x828,0x00000004,
-0x82c,0x00e90000,
-0x830,0x00000004,
-0x834,0x00690000,
-0x838,0x00000004,
-0x83c,0x00e90000,
-0x840,0x00000000,
-0x844,0x00000000,
-0x848,0x00000000,
-0x84c,0x00000000,
-0x850,0x00000000,
-0x854,0x00000000,
-0x858,0x65a965a9,
-0x85c,0x65a965a9,
-0x860,0x001f0000,
-0x864,0x007f0000,
-0x868,0x001f0010,
-0x86c,0x007f0010,
-0x870,0x0f100f70,
-0x874,0x0f100f70,
-0x878,0x00000000,
-0x87c,0x00000000,
-0x880,0x5c385898,
-0x884,0x6357060d,
-0x888,0x0460c341,
-0x88c,0x0000fc00,
-0x890,0x00000000,
-0x894,0xfffffffe,
-0x898,0x4c42382f,
-0x89c,0x00656056,
-0x8b0,0x00000000,
-0x8e0,0x00000000,
-0x8e4,0x00000000,
-0x900,0x00000000,
-0x904,0x00000023,
-0x908,0x00000000,
-0x90c,0x34441444,
-0xa00,0x00d0c7d8,
-0xa04,0x2b1f0008,
-0xa08,0x80cd8300,
-0xa0c,0x2e62740f,
-0xa10,0x95009b78,
-0xa14,0x11145008,
-0xa18,0x00881117,
-0xa1c,0x89140fa0,
-0xa20,0x1a1b0000,
-0xa24,0x090e1317,
-0xa28,0x00000204,
-0xa2c,0x00000000,
-0xc00,0x00000040,
-0xc04,0x0000500c,
-0xc08,0x000000e4,
-0xc0c,0x6c6c6c6c,
-0xc10,0x08000000,
-0xc14,0x40000100,
-0xc18,0x08000000,
-0xc1c,0x40000100,
-0xc20,0x08000000,
-0xc24,0x40000100,
-0xc28,0x08000000,
-0xc2c,0x40000100,
-0xc30,0x6de9ac44,
-0xc34,0x164052cd,
-0xc38,0x00070a14,
-0xc3c,0x0a969764,
-0xc40,0x1f7c403f,
-0xc44,0x000100b7,
-0xc48,0xec020000,
-0xc4c,0x00000300,
-0xc50,0x69543420,
-0xc54,0x433c0094,
-0xc58,0x69543420,
-0xc5c,0x433c0094,
-0xc60,0x69543420,
-0xc64,0x433c0094,
-0xc68,0x69543420,
-0xc6c,0x433c0094,
-0xc70,0x2c7f000d,
-0xc74,0x0186175b,
-0xc78,0x0000001f,
-0xc7c,0x00b91612,
-0xc80,0x40000100,
-0xc84,0x00000000,
-0xc88,0x40000100,
-0xc8c,0x08000000,
-0xc90,0x40000100,
-0xc94,0x00000000,
-0xc98,0x40000100,
-0xc9c,0x00000000,
-0xca0,0x00492492,
-0xca4,0x00000000,
-0xca8,0x00000000,
-0xcac,0x00000000,
-0xcb0,0x00000000,
-0xcb4,0x00000000,
-0xcb8,0x00000000,
-0xcbc,0x00492492,
-0xcc0,0x00000000,
-0xcc4,0x00000000,
-0xcc8,0x00000000,
-0xccc,0x00000000,
-0xcd0,0x00000000,
-0xcd4,0x00000000,
-0xcd8,0x64b22427,
-0xcdc,0x00766932,
-0xce0,0x00222222,
-0xd00,0x00000740,
-0xd04,0x0000040c,
-0xd08,0x0000803f,
-0xd0c,0x00000001,
-0xd10,0xa0633333,
-0xd14,0x33333c63,
-0xd18,0x6a8f5b6b,
-0xd1c,0x00000000,
-0xd20,0x00000000,
-0xd24,0x00000000,
-0xd28,0x00000000,
-0xd2c,0xcc979975,
-0xd30,0x00000000,
-0xd34,0x00000000,
-0xd38,0x00000000,
-0xd3c,0x00027293,
-0xd40,0x00000000,
-0xd44,0x00000000,
-0xd48,0x00000000,
-0xd4c,0x00000000,
-0xd50,0x6437140a,
-0xd54,0x024dbd02,
-0xd58,0x00000000,
-0xd5c,0x14032064,
-};
-
-u32 Rtl8190PciRadioA_Array[RadioA_ArrayLength] = {
-0x019,0x00000003,
-0x000,0x000000bf,
-0x001,0x00000ee0,
-0x002,0x0000004c,
-0x003,0x000007f1,
-0x004,0x00000975,
-0x005,0x00000c58,
-0x006,0x00000ae6,
-0x007,0x000000ca,
-0x008,0x00000e1c,
-0x009,0x000007f0,
-0x00a,0x000009d0,
-0x00b,0x000001ba,
-0x00c,0x00000240,
-0x00e,0x00000020,
-0x00f,0x00000990,
-0x012,0x00000806,
-0x014,0x000005ab,
-0x015,0x00000f80,
-0x016,0x00000020,
-0x017,0x00000597,
-0x018,0x0000050a,
-0x01a,0x00000f80,
-0x01b,0x00000f5e,
-0x01c,0x00000008,
-0x01d,0x00000607,
-0x01e,0x000006cc,
-0x01f,0x00000000,
-0x020,0x000001a5,
-0x01f,0x00000001,
-0x020,0x00000165,
-0x01f,0x00000002,
-0x020,0x000000c6,
-0x01f,0x00000003,
-0x020,0x00000086,
-0x01f,0x00000004,
-0x020,0x00000046,
-0x01f,0x00000005,
-0x020,0x000001e6,
-0x01f,0x00000006,
-0x020,0x000001a6,
-0x01f,0x00000007,
-0x020,0x00000166,
-0x01f,0x00000008,
-0x020,0x000000c7,
-0x01f,0x00000009,
-0x020,0x00000087,
-0x01f,0x0000000a,
-0x020,0x000000f7,
-0x01f,0x0000000b,
-0x020,0x000000d7,
-0x01f,0x0000000c,
-0x020,0x000000b7,
-0x01f,0x0000000d,
-0x020,0x00000097,
-0x01f,0x0000000e,
-0x020,0x00000077,
-0x01f,0x0000000f,
-0x020,0x00000057,
-0x01f,0x00000010,
-0x020,0x00000037,
-0x01f,0x00000011,
-0x020,0x000000fb,
-0x01f,0x00000012,
-0x020,0x000000db,
-0x01f,0x00000013,
-0x020,0x000000bb,
-0x01f,0x00000014,
-0x020,0x000000ff,
-0x01f,0x00000015,
-0x020,0x000000e3,
-0x01f,0x00000016,
-0x020,0x000000c3,
-0x01f,0x00000017,
-0x020,0x000000a3,
-0x01f,0x00000018,
-0x020,0x00000083,
-0x01f,0x00000019,
-0x020,0x00000063,
-0x01f,0x0000001a,
-0x020,0x00000043,
-0x01f,0x0000001b,
-0x020,0x00000023,
-0x01f,0x0000001c,
-0x020,0x00000003,
-0x01f,0x0000001d,
-0x020,0x000001e3,
-0x01f,0x0000001e,
-0x020,0x000001c3,
-0x01f,0x0000001f,
-0x020,0x000001a3,
-0x01f,0x00000020,
-0x020,0x00000183,
-0x01f,0x00000021,
-0x020,0x00000163,
-0x01f,0x00000022,
-0x020,0x00000143,
-0x01f,0x00000023,
-0x020,0x00000123,
-0x01f,0x00000024,
-0x020,0x00000103,
-0x023,0x00000203,
-0x024,0x00000200,
-0x00b,0x000001ba,
-0x02c,0x000003d7,
-0x02d,0x00000ff0,
-0x000,0x00000037,
-0x004,0x00000160,
-0x007,0x00000080,
-0x002,0x0000088d,
-0x0fe,0x00000000,
-0x0fe,0x00000000,
-0x016,0x00000200,
-0x016,0x00000380,
-0x016,0x00000020,
-0x016,0x000001a0,
-0x000,0x000000bf,
-0x00d,0x0000001f,
-0x00d,0x00000c9f,
-0x002,0x0000004d,
-0x000,0x00000cbf,
-0x004,0x00000975,
-0x007,0x00000700,
-};
-u32 Rtl8190PciRadioB_Array[RadioB_ArrayLength] = {
-0x019,0x00000003,
-0x000,0x000000bf,
-0x001,0x000006e0,
-0x002,0x0000004c,
-0x003,0x000007f1,
-0x004,0x00000975,
-0x005,0x00000c58,
-0x006,0x00000ae6,
-0x007,0x000000ca,
-0x008,0x00000e1c,
-0x000,0x000000b7,
-0x00a,0x00000850,
-0x000,0x000000bf,
-0x00b,0x000001ba,
-0x00c,0x00000240,
-0x00e,0x00000020,
-0x015,0x00000f80,
-0x016,0x00000020,
-0x017,0x00000597,
-0x018,0x0000050a,
-0x01a,0x00000e00,
-0x01b,0x00000f5e,
-0x01d,0x00000607,
-0x01e,0x000006cc,
-0x00b,0x000001ba,
-0x023,0x00000203,
-0x024,0x00000200,
-0x000,0x00000037,
-0x004,0x00000160,
-0x016,0x00000200,
-0x016,0x00000380,
-0x016,0x00000020,
-0x016,0x000001a0,
-0x00d,0x00000ccc,
-0x000,0x000000bf,
-0x002,0x0000004d,
-0x000,0x00000cbf,
-0x004,0x00000975,
-0x007,0x00000700,
-};
-u32 Rtl8190PciRadioC_Array[RadioC_ArrayLength] = {
-0x019,0x00000003,
-0x000,0x000000bf,
-0x001,0x00000ee0,
-0x002,0x0000004c,
-0x003,0x000007f1,
-0x004,0x00000975,
-0x005,0x00000c58,
-0x006,0x00000ae6,
-0x007,0x000000ca,
-0x008,0x00000e1c,
-0x009,0x000007f0,
-0x00a,0x000009d0,
-0x00b,0x000001ba,
-0x00c,0x00000240,
-0x00e,0x00000020,
-0x00f,0x00000990,
-0x012,0x00000806,
-0x014,0x000005ab,
-0x015,0x00000f80,
-0x016,0x00000020,
-0x017,0x00000597,
-0x018,0x0000050a,
-0x01a,0x00000f80,
-0x01b,0x00000f5e,
-0x01c,0x00000008,
-0x01d,0x00000607,
-0x01e,0x000006cc,
-0x01f,0x00000000,
-0x020,0x000001a5,
-0x01f,0x00000001,
-0x020,0x00000165,
-0x01f,0x00000002,
-0x020,0x000000c6,
-0x01f,0x00000003,
-0x020,0x00000086,
-0x01f,0x00000004,
-0x020,0x00000046,
-0x01f,0x00000005,
-0x020,0x000001e6,
-0x01f,0x00000006,
-0x020,0x000001a6,
-0x01f,0x00000007,
-0x020,0x00000166,
-0x01f,0x00000008,
-0x020,0x000000c7,
-0x01f,0x00000009,
-0x020,0x00000087,
-0x01f,0x0000000a,
-0x020,0x000000f7,
-0x01f,0x0000000b,
-0x020,0x000000d7,
-0x01f,0x0000000c,
-0x020,0x000000b7,
-0x01f,0x0000000d,
-0x020,0x00000097,
-0x01f,0x0000000e,
-0x020,0x00000077,
-0x01f,0x0000000f,
-0x020,0x00000057,
-0x01f,0x00000010,
-0x020,0x00000037,
-0x01f,0x00000011,
-0x020,0x000000fb,
-0x01f,0x00000012,
-0x020,0x000000db,
-0x01f,0x00000013,
-0x020,0x000000bb,
-0x01f,0x00000014,
-0x020,0x000000ff,
-0x01f,0x00000015,
-0x020,0x000000e3,
-0x01f,0x00000016,
-0x020,0x000000c3,
-0x01f,0x00000017,
-0x020,0x000000a3,
-0x01f,0x00000018,
-0x020,0x00000083,
-0x01f,0x00000019,
-0x020,0x00000063,
-0x01f,0x0000001a,
-0x020,0x00000043,
-0x01f,0x0000001b,
-0x020,0x00000023,
-0x01f,0x0000001c,
-0x020,0x00000003,
-0x01f,0x0000001d,
-0x020,0x000001e3,
-0x01f,0x0000001e,
-0x020,0x000001c3,
-0x01f,0x0000001f,
-0x020,0x000001a3,
-0x01f,0x00000020,
-0x020,0x00000183,
-0x01f,0x00000021,
-0x020,0x00000163,
-0x01f,0x00000022,
-0x020,0x00000143,
-0x01f,0x00000023,
-0x020,0x00000123,
-0x01f,0x00000024,
-0x020,0x00000103,
-0x023,0x00000203,
-0x024,0x00000200,
-0x00b,0x000001ba,
-0x02c,0x000003d7,
-0x02d,0x00000ff0,
-0x000,0x00000037,
-0x004,0x00000160,
-0x007,0x00000080,
-0x002,0x0000088d,
-0x0fe,0x00000000,
-0x0fe,0x00000000,
-0x016,0x00000200,
-0x016,0x00000380,
-0x016,0x00000020,
-0x016,0x000001a0,
-0x000,0x000000bf,
-0x00d,0x0000001f,
-0x00d,0x00000c9f,
-0x002,0x0000004d,
-0x000,0x00000cbf,
-0x004,0x00000975,
-0x007,0x00000700,
-};
-u32 Rtl8190PciRadioD_Array[RadioD_ArrayLength] = {
-0x019,0x00000003,
-0x000,0x000000bf,
-0x001,0x000006e0,
-0x002,0x0000004c,
-0x003,0x000007f1,
-0x004,0x00000975,
-0x005,0x00000c58,
-0x006,0x00000ae6,
-0x007,0x000000ca,
-0x008,0x00000e1c,
-0x000,0x000000b7,
-0x00a,0x00000850,
-0x000,0x000000bf,
-0x00b,0x000001ba,
-0x00c,0x00000240,
-0x00e,0x00000020,
-0x015,0x00000f80,
-0x016,0x00000020,
-0x017,0x00000597,
-0x018,0x0000050a,
-0x01a,0x00000e00,
-0x01b,0x00000f5e,
-0x01d,0x00000607,
-0x01e,0x000006cc,
-0x00b,0x000001ba,
-0x023,0x00000203,
-0x024,0x00000200,
-0x000,0x00000037,
-0x004,0x00000160,
-0x016,0x00000200,
-0x016,0x00000380,
-0x016,0x00000020,
-0x016,0x000001a0,
-0x00d,0x00000ccc,
-0x000,0x000000bf,
-0x002,0x0000004d,
-0x000,0x00000cbf,
-0x004,0x00000975,
-0x007,0x00000700,
-};
-#endif
-#ifdef RTL8192E
+
static u32 Rtl8192PciEMACPHY_Array[] = {
0x03c,0xffff0000,0x00000f0f,
0x340,0xffffffff,0x161a1a1a,
0x0, };
static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = {
0x0, };
-#endif
/*************************Define local function prototype**********************/
{
u8 ret = 1;
struct r8192_priv *priv = ieee80211_priv(dev);
-#ifdef RTL8190P
- if(priv->rf_type == RF_2T4R)
- {
- ret= 1;
- }
- else if (priv->rf_type == RF_1T2R)
- {
- if(eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
- ret = 0;
- else if(eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
- ret = 1;
- }
-#else
- #ifdef RTL8192E
+
if (priv->rf_type == RF_2T4R)
ret = 0;
else if (priv->rf_type == RF_1T2R)
else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
ret = 0;
}
- #endif
-#endif
+
return ret;
}
/******************************************************************************
//switch page for 8256 RF IC
if (priv->rf_chip == RF_8256)
{
-#ifdef RTL8190P
- //analog to digital off, for protection
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
-#else
- #ifdef RTL8192E
//analog to digital off, for protection
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
- #endif
-#endif
if (Offset >= 31)
{
priv->RfReg0Value[eRFPath] |= 0x140;
bMaskDWord,
(priv->RfReg0Value[eRFPath] << 16));
-#ifdef RTL8190P
- if(priv->rf_type == RF_2T4R)
- {
- //analog to digital on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
- }
- else if(priv->rf_type == RF_1T2R)
- {
- //analog to digital on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
- }
-#else
- #ifdef RTL8192E
//analog to digital on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
- #endif
-#endif
}
if (priv->rf_chip == RF_8256)
{
-#ifdef RTL8190P
- //analog to digital off, for protection
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
-#else
- #ifdef RTL8192E
//analog to digital off, for protection
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
- #endif
-#endif
if (Offset >= 31)
{
bMaskDWord,
(priv->RfReg0Value[eRFPath] << 16));
}
-#ifdef RTL8190P
- if(priv->rf_type == RF_2T4R)
- {
- //analog to digital on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
- }
- else if(priv->rf_type == RF_1T2R)
- {
- //analog to digital on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
- }
-#else
- #ifdef RTL8192E
//analog to digital on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
- #endif
-#endif
}
}
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
return;
-#ifdef RTL8192E
if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
return;
-#endif
//down(&priv->rf_sem);
RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
struct r8192_priv *priv = ieee80211_priv(dev);
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
return 0;
-#ifdef RTL8192E
if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
return 0;
-#endif
down(&priv->rf_sem);
if (priv->Rf_Mode == RF_OP_By_FW)
{
//XSTALLCap
-#ifdef RTL8190P
- dwRegValue = priv->CrystalCap & 0x3; // bit0~1 of crystal cap
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue);
- dwRegValue = ((priv->CrystalCap & 0xc)>>2); // bit2~3 of crystal cap
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, bXtalCap23, dwRegValue);
-#else
- #ifdef RTL8192E
dwRegValue = priv->CrystalCap;
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
- #endif
-#endif
-
}
// Check if the CCK HighPower is turned ON.
void rtl8192_phy_getTxPower(struct net_device* dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
-#ifdef RTL8190P
- priv->MCSTxPowerLevelOriginalOffset[0] =
- read_nic_dword(priv, MCS_TXAGC);
- priv->MCSTxPowerLevelOriginalOffset[1] =
- read_nic_dword(priv, (MCS_TXAGC+4));
- priv->CCKTxPowerLevelOriginalOffset =
- read_nic_dword(priv, CCK_TXAGC);
-#else
- #ifdef RTL8192E
+
priv->MCSTxPowerLevelOriginalOffset[0] =
read_nic_dword(priv, rTxAGC_Rate18_06);
priv->MCSTxPowerLevelOriginalOffset[1] =
read_nic_dword(priv, rTxAGC_Mcs11_Mcs08);
priv->MCSTxPowerLevelOriginalOffset[5] =
read_nic_dword(priv, rTxAGC_Mcs15_Mcs12);
- #endif
-#endif
// read rx initial gain
priv->DefaultInitialGain[0] = read_nic_byte(priv, rOFDM0_XAAGCCore1);
}
}
-#ifndef RTL8190P
static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
}
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
}
-#endif
static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
{
-#ifdef RTL8192E
struct r8192_priv *priv = ieee80211_priv(dev);
-#endif
-#ifdef RTL8190P
- CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
-#else
//if(pHalData->bDcut == TRUE)
if(priv->IC_Cut >= IC_VersionCut_D)
CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
else
CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
-#endif
}
else
CCK_Tx_Power_Track_BW_Switch(dev);
-#ifdef RTL8190P
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
- rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x44); // 0xc30 is for 8190 only, Emily
-#else
- #ifdef RTL8192E
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
- #endif
-#endif
-
break;
case HT_CHANNEL_WIDTH_20_40:
// Add by Vivi 20071119
rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
-#ifdef RTL8190P
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
- rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x42); // 0xc30 is for 8190 only, Emily
-
- // Set whether CCK should be sent in upper or lower channel. Suggest by YN. 20071207
- // It is set in Tx descriptor for 8192x series
- if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
- {
- rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x01);
- }else if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
- {
- rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x02);
- }
-
-#else
- #ifdef RTL8192E
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
- #endif
-#endif
break;
default:
RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
}
//Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
-#if 1
//<3>Set RF related register
switch( priv->rf_chip )
{
RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
break;
}
-#endif
+
atomic_dec(&(priv->ieee80211->atm_swbw));
priv->SetBWModeInProgress= false;
#define MAX_RFDEPENDCMD_CNT 16
#define MAX_POSTCMD_CNT 16
-#ifdef RTL8190P
-#define MACPHY_Array_PGLength 21
-#define Rtl819XMACPHY_Array_PG Rtl8190PciMACPHY_Array_PG
-#define Rtl819XMACPHY_Array Rtl8190PciMACPHY_Array
-#define RadioC_ArrayLength 246
-#define RadioD_ArrayLength 78
-#define Rtl819XRadioA_Array Rtl8190PciRadioA_Array
-#define Rtl819XRadioB_Array Rtl8190PciRadioB_Array
-#define Rtl819XRadioC_Array Rtl8190PciRadioC_Array
-#define Rtl819XRadioD_Array Rtl8190PciRadioD_Array
-#define Rtl819XAGCTAB_Array Rtl8190PciAGCTAB_Array
-#define PHY_REGArrayLength 280
-#define Rtl819XPHY_REGArray Rtl8190PciPHY_REGArray
-#define PHY_REG_1T2RArrayLength 280
-#define Rtl819XPHY_REG_1T2RArray Rtl8190PciPHY_REG_1T2RArray
-#endif
-
-
-#ifdef RTL8192E
#define MACPHY_Array_PGLength 30
#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
#define PHY_REG_1T2RArrayLength 296
#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
-#endif
#define AGCTAB_ArrayLength 384
#define MACPHY_ArrayLength 18
projects / firefly-linux-kernel-4.4.55.git / commitdiff