AMDGPU: Fix parsing of 32-bit literals with sign bit set

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251132 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index ad50003213d73ecdf17076ce2892ffc214e30b7a..7a2951686459a559dd1beab2d51bb12b6fb8f2c7 100644 (file)
--- a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -987,13 +987,11 @@ AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
       int64_t IntVal;
       if (getParser().parseAbsoluteExpression(IntVal))
         return MatchOperand_ParseFail;
-      APInt IntVal32(32, IntVal);
-      if (IntVal32.getSExtValue() != IntVal) {
+      if (!isInt<32>(IntVal) && !isUInt<32>(IntVal)) {
         Error(S, "invalid immediate: only 32-bit values are legal");
         return MatchOperand_ParseFail;
       }
 
-      IntVal = IntVal32.getSExtValue();
       if (Negate)
         IntVal *= -1;
       Operands.push_back(AMDGPUOperand::CreateImm(IntVal, S));

diff --git a/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp b/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
index d64ac3f6265cc687e33dace4d68539a95193fd38..870b632c30627d9d012f6c7c0a2876e1eb896deb 100644 (file)
--- a/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
+++ b/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
@@ -283,8 +283,13 @@ void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, raw_ostream &O) {
     O << "4.0";
   else if (Imm == DoubleToBits(-4.0))
     O << "-4.0";
-  else
-    llvm_unreachable("64-bit literal constants not supported");
+  else {
+    assert(isUInt<32>(Imm));
+
+    // In rare situations, we will have a 32-bit literal in a 64-bit
+    // operand. This is technically allowed for the encoding of s_mov_b64.
+    O << formatHex(static_cast<uint64_t>(Imm));
+  }
 }
 
 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,

diff --git a/test/MC/AMDGPU/sop1-err.s b/test/MC/AMDGPU/sop1-err.s
index f892356b623dd676521eaeaf0ae5cebd41d242d1..c54b357791a4eac714b33789c0ec1e2dc884a0a4 100644 (file)
--- a/test/MC/AMDGPU/sop1-err.s
+++ b/test/MC/AMDGPU/sop1-err.s
@@ -33,5 +33,14 @@ s_mov_b32 s1, 0xfffffffff
 s_mov_b64 s[0:1], 0xfffffffff
 // CHECK: error: invalid immediate: only 32-bit values are legal
 
+s_mov_b64 s[0:1], 0xfffffffff
+// CHECK: error: invalid immediate: only 32-bit values are legal
+
+s_mov_b64 s[0:1], 0xfffffffff
+// CHECK: error: invalid immediate: only 32-bit values are legal
+
+s_mov_b64 s[0:1], 0x0000000200000000
+// CHECK: error: invalid immediate: only 32-bit values are legal
+
 // Out of range register
 s_mov_b32 s

diff --git a/test/MC/AMDGPU/sop1.s b/test/MC/AMDGPU/sop1.s
index 92ca73f250045261186aef2f58aed22122a6a550..a99bc9ab1cd642c51b71dc4f0d47b6f8c3e3b17c 100644 (file)
--- a/test/MC/AMDGPU/sop1.s
+++ b/test/MC/AMDGPU/sop1.s
@@ -10,12 +10,26 @@ s_mov_b32 s1, 1
 s_mov_b32 s1, 100
 // CHECK: s_mov_b32 s1, 0x64 ; encoding: [0xff,0x03,0x81,0xbe,0x64,0x00,0x00,0x00]
 
+// Literal constant sign bit
+s_mov_b32 s1, 0x80000000
+// CHECK: s_mov_b32 s1, 0x80000000 ; encoding: [0xff,0x03,0x81,0xbe,0x00,0x00,0x00,0x80]
+
+// Negative 32-bit constant
+s_mov_b32 s0, 0xfe5163ab
+// CHECK: s_mov_b32 s0, 0xfe5163ab ; encoding: [0xff,0x03,0x80,0xbe,0xab,0x63,0x51,0xfe]
+
 s_mov_b64 s[2:3], s[4:5]
 // CHECK: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x04,0x82,0xbe]
 
 s_mov_b64 s[2:3], 0xffffffffffffffff
 // CHECK: s_mov_b64 s[2:3], -1 ; encoding: [0xc1,0x04,0x82,0xbe]
 
+s_mov_b64 s[2:3], 0xffffffff
+// CHECK: s_mov_b64 s[2:3], 0xffffffff ; encoding: [0xff,0x04,0x82,0xbe,0xff,0xff,0xff,0xff]
+
+s_mov_b64 s[0:1], 0x80000000
+// CHECK: s_mov_b64 s[0:1], 0x80000000 ; encoding: [0xff,0x04,0x80,0xbe,0x00,0x00,0x00,0x80]
+
 s_cmov_b32 s1, 200
 // CHECK: s_cmov_b32 s1, 0xc8 ; encoding: [0xff,0x05,0x81,0xbe,0xc8,0x00,0x00,0x00]