rk312x lvds: fix ttl rgb mode no output

diff --git a/drivers/video/rockchip/transmitter/rk31xx_lvds.c b/drivers/video/rockchip/transmitter/rk31xx_lvds.c
index 13f64df8c828b601a52b91e02092f3497fcafc8a..4ef13e4dfec594eb262ec555d4325e71be51d81c 100755 (executable)
--- a/drivers/video/rockchip/transmitter/rk31xx_lvds.c
+++ b/drivers/video/rockchip/transmitter/rk31xx_lvds.c
@@ -186,20 +186,24 @@ static void rk31xx_output_lvttl(struct rk_lvds_device *lvds,
 
        val |= v_LVDSMODE_EN(0) | v_MIPIPHY_TTL_EN(1);  /* enable lvds mode */
        val |= v_LVDS_DATA_SEL(LVDS_DATA_FROM_LCDC);    /* config data source */
-       grf_writel(val, RK312X_GRF_LVDS_CON0);
+       grf_writel(0xffff0380, RK312X_GRF_LVDS_CON0);
 
-        /* set pll prediv and fbdiv */
-       lvds_writel(lvds, MIPIPHY_REG3, v_PREDIV(1) | v_FBDIV_MSB(0));
-       lvds_writel(lvds, MIPIPHY_REG4, v_FBDIV_LSB(7));
+        val = v_MIPITTL_CLK_EN(1) | v_MIPITTL_LANE0_EN(1) |
+                v_MIPITTL_LANE1_EN(1) | v_MIPITTL_LANE2_EN(1) |
+                v_MIPITTL_LANE3_EN(1);
+        grf_writel(val, RK312X_GRF_SOC_CON1);
+
+        /* enable lane */
+        lvds_writel(lvds, MIPIPHY_REG0, 0x7f);
+        val = v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | v_LANE3_EN(1) |
+                v_LANECLK_EN(1) | v_PLL_PWR_OFF(1);
+        lvds_writel(lvds, MIPIPHY_REGEB, val);
 
         /* set ttl mode and reset phy config */
         val = v_LVDS_MODE_EN(0) | v_TTL_MODE_EN(1) | v_MIPI_MODE_EN(0) |
                 v_MSB_SEL(1) | v_DIG_INTER_RST(1);
        lvds_writel(lvds, MIPIPHY_REGE0, val);
 
-        lvds_writel(lvds, MIPIPHY_REGE1, 0x92);
-
-        /* enable ttl */
        rk31xx_lvds_pwr_on();
                
 }

diff --git a/drivers/video/rockchip/transmitter/rk31xx_lvds.h b/drivers/video/rockchip/transmitter/rk31xx_lvds.h
index 818901a716df7ece003a35e87b57697501fc46f5..7178bf9c1d54d63262e16abd7004c853c923868d 100755 (executable)
--- a/drivers/video/rockchip/transmitter/rk31xx_lvds.h
+++ b/drivers/video/rockchip/transmitter/rk31xx_lvds.h
@@ -27,6 +27,26 @@ enum {
         LVDS_MSB_D7,
 };
 
+/* RK312X_GRF_SOC_CON1 */
+#define v_MIPITTL_CLK_EN(x)     (BITS_MASK(x, 1, 7) | BITS_EN(1, 7))
+#define v_MIPITTL_LANE0_EN(x)   (BITS_MASK(x, 1, 11) | BITS_EN(1, 11))
+#define v_MIPITTL_LANE1_EN(x)   (BITS_MASK(x, 1, 12) | BITS_EN(1, 12))
+#define v_MIPITTL_LANE2_EN(x)   (BITS_MASK(x, 1, 13) | BITS_EN(1, 13))
+#define v_MIPITTL_LANE3_EN(x)   (BITS_MASK(x, 1, 14) | BITS_EN(1, 14))
+
+
+#define MIPIPHY_REG0            0x0000
+#define m_LANE_EN_0             BITS(1, 2)
+#define m_LANE_EN_1             BITS(1, 3)
+#define m_LANE_EN_2             BITS(1, 4)
+#define m_LANE_EN_3             BITS(1, 5)
+#define m_LANE_EN_CLK           BITS(1, 5)
+#define v_LANE_EN_0(x)          BITS(1, 2)
+#define v_LANE_EN_1(x)          BITS(1, 3)
+#define v_LANE_EN_2(x)          BITS(1, 4)
+#define v_LANE_EN_3(x)          BITS(1, 5)
+#define v_LANE_EN_CLK(x)        BITS(1, 5)
+
 #define MIPIPHY_REG1            0x0004
 #define m_SYNC_RST              BITS(1, 0)
 #define m_LDO_PWR_DOWN          BITS(1, 1)