OS << "(setlocal @" << TargetRegisterInfo::virtReg2Index(Reg) << ' ';
}
- OS << '(' << OpcodeName(TII, MI);
- for (const MachineOperand &MO : MI->uses())
- switch (MO.getType()) {
- default:
- llvm_unreachable("unexpected machine operand type");
- case MachineOperand::MO_Register: {
- if (MO.isImplicit())
- continue;
- unsigned Reg = MO.getReg();
- OS << " @" << TargetRegisterInfo::virtReg2Index(Reg);
- } break;
- case MachineOperand::MO_Immediate: {
- OS << ' ' << MO.getImm();
- } break;
- case MachineOperand::MO_FPImmediate: {
- OS << ' ' << toString(MO.getFPImm()->getValueAPF());
- } break;
- case MachineOperand::MO_GlobalAddress: {
- OS << ' ' << toSymbol(MO.getGlobal()->getName());
- } break;
- }
- OS << ')';
+ if (MI->getOpcode() == WebAssembly::COPY) {
+ OS << '@' << TargetRegisterInfo::virtReg2Index(MI->getOperand(1).getReg());
+ } else {
+ OS << '(' << OpcodeName(TII, MI);
+ for (const MachineOperand &MO : MI->uses())
+ switch (MO.getType()) {
+ default:
+ llvm_unreachable("unexpected machine operand type");
+ case MachineOperand::MO_Register: {
+ if (MO.isImplicit())
+ continue;
+ unsigned Reg = MO.getReg();
+ OS << " @" << TargetRegisterInfo::virtReg2Index(Reg);
+ } break;
+ case MachineOperand::MO_Immediate: {
+ OS << ' ' << MO.getImm();
+ } break;
+ case MachineOperand::MO_FPImmediate: {
+ OS << ' ' << toString(MO.getFPImm()->getValueAPF());
+ } break;
+ case MachineOperand::MO_GlobalAddress: {
+ OS << ' ' << toSymbol(MO.getGlobal()->getName());
+ } break;
+ }
+ OS << ')';
+ }
if (NumDefs != 0)
OS << ')';
WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
: RI(STI.getTargetTriple()) {}
+
+void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ DebugLoc DL, unsigned DestReg,
+ unsigned SrcReg, bool KillSrc) const {
+ BuildMI(MBB, I, DL, get(WebAssembly::COPY), DestReg)
+ .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
+}
explicit WebAssemblyInstrInfo(const WebAssemblySubtarget &STI);
const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; }
+
+ void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+ DebugLoc DL, unsigned DestReg, unsigned SrcReg,
+ bool KillSrc) const override;
};
} // end namespace llvm
target datalayout = "e-p:32:32-i64:64-v128:8:128-n32:64-S128"
target triple = "wasm32-unknown-unknown"
+; Basic phi triangle.
+
; CHECK-LABEL: test0
; CHECK: (setlocal [[REG:@.*]] (argument 0))
; CHECK: (setlocal [[REG]] (sdiv [[REG]] {{.*}}))
%s = phi i32 [ %a, %true ], [ %p, %entry ]
ret i32 %s
}
+
+; Swap phis.
+
+; CHECK-LABEL: test1
+; CHECK: BB0_1:
+; CHECK: (setlocal [[REG0:@.*]] [[REG1:@.*]])
+; CHECK: (setlocal [[REG1]] [[REG2:@.*]])
+; CHECK: (setlocal [[REG2]] [[REG0]])
+define i32 @test1(i32 %n) {
+entry:
+ br label %loop
+
+loop:
+ %a = phi i32 [ 0, %entry ], [ %b, %loop ]
+ %b = phi i32 [ 1, %entry ], [ %a, %loop ]
+ %i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
+
+ %i.next = add i32 %i, 1
+ %t = icmp slt i32 %i.next, %n
+ br i1 %t, label %loop, label %exit
+
+exit:
+ ret i32 %a
+}