rename SDTRet -> SDTNone.

Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 2709fc83509d1c65031c5debaba5952ba6cb1239..1027b6c3d45a718747b86fe9a8383e73deda0eb2 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -57,7 +57,7 @@ def ARMcall_pred    : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
 def ARMcall_nolink   : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
                               [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
-def ARMretflag       : SDNode<"ARMISD::RET_FLAG", SDTRet,
+def ARMretflag       : SDNode<"ARMISD::RET_FLAG", SDTNone,
                               [SDNPHasChain, SDNPOptInFlag]>;
 
 def ARMcmov          : SDNode<"ARMISD::CMOV", SDT_ARMCMov,

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index ea87889c1c4da27bc75afaeb90b54d250a138c4d..011819839ba1aed4bc7ccd45d63c6afc5946f1a0 100644 (file)
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -79,7 +79,7 @@ def arm_ftoui  : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
 def arm_ftosi  : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
 def arm_sitof  : SDNode<"ARMISD::SITOF", SDT_ITOF>;
 def arm_uitof  : SDNode<"ARMISD::UITOF", SDT_ITOF>;
-def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTRet, [SDNPInFlag,SDNPOutFlag]>;
+def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
 def arm_cmpfp  : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>;
 def arm_fmdrr  : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;

diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index 5aaed81db217600a00c72e08cbe9a89a3b17c754..474180f9154a0b4a274fdde3487b3599503e7887 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -26,7 +26,7 @@ def Alpha_gprello : SDNode<"AlphaISD::GPRelLo",   SDTIntBinOp, []>;
 def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi",   SDTIntBinOp, []>;
 def Alpha_rellit  : SDNode<"AlphaISD::RelLit",    SDTIntBinOp, [SDNPMayLoad]>;
 
-def retflag       : SDNode<"AlphaISD::RET_FLAG", SDTRet,
+def retflag       : SDNode<"AlphaISD::RET_FLAG", SDTNone,
                           [SDNPHasChain, SDNPOptInFlag]>;
 
 // These are target-independent nodes, but have target-specific formats.

diff --git a/lib/Target/CellSPU/SPUNodes.td b/lib/Target/CellSPU/SPUNodes.td
index ae513d226637fd3df9702678e21b94ae05b74857..b176fc98c7fb24e0d837d6d45377756d7d3d9a8a 100644 (file)
--- a/lib/Target/CellSPU/SPUNodes.td
+++ b/lib/Target/CellSPU/SPUNodes.td
@@ -222,5 +222,5 @@ class NoEncode<string E> {
 // instruction scheduling doesn't disassociate them.)
 //===----------------------------------------------------------------------===//
 
-def retflag     : SDNode<"SPUISD::RET_FLAG", SDTRet,
+def retflag     : SDNode<"SPUISD::RET_FLAG", SDTNone,
                          [SDNPHasChain, SDNPOptInFlag]>;

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 495a1fd422400185a7e5a54cdcece795bf98bf5d..616c0e7b4c82e8cea64a428d52bcd7103099c110 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -105,13 +105,13 @@ def PPCcall_ELF   : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
                            [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 def PPCmtctr      : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
                            [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
-def PPCbctrl_Macho  : SDNode<"PPCISD::BCTRL_Macho", SDTRet,
+def PPCbctrl_Macho  : SDNode<"PPCISD::BCTRL_Macho", SDTNone,
                           [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
-def PPCbctrl_ELF  : SDNode<"PPCISD::BCTRL_ELF", SDTRet,
+def PPCbctrl_ELF  : SDNode<"PPCISD::BCTRL_ELF", SDTNone,
                           [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
-def retflag       : SDNode<"PPCISD::RET_FLAG", SDTRet,
+def retflag       : SDNode<"PPCISD::RET_FLAG", SDTNone,
                           [SDNPHasChain, SDNPOptInFlag]>;
 
 def PPCvcmp       : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;

diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
index 091438a4abc005174c870ad284c261a06701dc6c..696f815d02a8a3865a4c154c818c07ac6279364a 100644 (file)
--- a/lib/Target/TargetSelectionDAG.td
+++ b/lib/Target/TargetSelectionDAG.td
@@ -154,7 +154,7 @@ def SDTBrind : SDTypeProfile<0, 1, [ // brind
   SDTCisPtrTy<0>
 ]>;
 
-def SDTRet : SDTypeProfile<0, 0, []>; // ret
+def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
 
 def SDTLoad : SDTypeProfile<1, 1, [ // load
   SDTCisPtrTy<1>  
@@ -311,7 +311,9 @@ def selectcc   : SDNode<"ISD::SELECT_CC"  , SDTSelectCC>;
 def brcond     : SDNode<"ISD::BRCOND"     , SDTBrcond, [SDNPHasChain]>;
 def brind      : SDNode<"ISD::BRIND"      , SDTBrind,  [SDNPHasChain]>;
 def br         : SDNode<"ISD::BR"         , SDTBr,     [SDNPHasChain]>;
-def ret        : SDNode<"ISD::RET"        , SDTRet,    [SDNPHasChain]>;
+def ret        : SDNode<"ISD::RET"        , SDTNone,   [SDNPHasChain]>;
+def trap       : SDNode<"ISD::TRAP"       , SDTNone,
+                        [SDNPHasChain, SDNPSideEffect]>;
 
 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
 // and truncst (see below).

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 037fc2f16e1e8789304d2c87d0bb6bb116dcdb29..de705de390d4a1148ceba2c68046e792773909a0 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -107,10 +107,6 @@ def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 
                         [SDNPHasChain,  SDNPOptInFlag]>;
 
-def SDT_TRAP  : SDTypeProfile<0, 0, []>;
-def trap  : SDNode<"ISD::TRAP", SDT_TRAP,
-                   [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
-
 //===----------------------------------------------------------------------===//
 // X86 Operand Definitions.
 //