Implement shifts properly (hopefilly - finally!)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76005 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index 952f4edb6317ae91f41585cffb57307494e227d1..6dea471dd9589c53e2a65a8d337154204857e3a7 100644 (file)
--- a/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -52,7 +52,7 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
 
   // Set shifts properties
   setShiftAmountFlavor(Extend);
-  setShiftAmountType(MVT::i32);
+  setShiftAmountType(MVT::i64);
 
   // Provide all sorts of operation actions
   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index a1202aa2e1afd8257902a10cafd27ba5b4896a4b..1784331e3be3ffe2cafafd513ebb50d8f224565c 100644 (file)
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -627,10 +627,7 @@ def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
                       [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
 def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
                       "srlg\t{$dst, $src, $amt}",
-                      [(set GR64:$dst, (srl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
-def SRLA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
-                      "srlg\t{$dst, $src, $amt}",
-                      [(set GR64:$dst, (srl GR64:$src, (i32 imm:$amt)))]>;
+                      [(set GR64:$dst, (srl GR64:$src, riaddr:$amt))]>;
 
 let isTwoAddress = 1 in
 def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
@@ -638,10 +635,7 @@ def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
                       [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
 def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
                       "sllg\t{$dst, $src, $amt}",
-                      [(set GR64:$dst, (shl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
-def SHL64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
-                      "sllg\t{$dst, $src, $amt}",
-                      [(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>;
+                      [(set GR64:$dst, (shl GR64:$src, riaddr:$amt))]>;
 
 let Defs = [PSW] in {
 let isTwoAddress = 1 in
@@ -649,13 +643,10 @@ def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
                       "sra\t{$src, $amt}",
                       [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
                        (implicit PSW)]>;
+
 def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
                       "srag\t{$dst, $src, $amt}",
-                      [(set GR64:$dst, (sra GR64:$src, (i32 (trunc riaddr:$amt)))),
-                       (implicit PSW)]>;
-def SRA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
-                      "srag\t{$dst, $src, $amt}",
-                      [(set GR64:$dst, (sra GR64:$src, (i32 imm:$amt))),
+                      [(set GR64:$dst, (sra GR64:$src, riaddr:$amt)),
                        (implicit PSW)]>;
 } // Defs = [PSW]
 
@@ -664,10 +655,7 @@ def ROTL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
                        [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>;
 def ROTL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
                        "rllg\t{$dst, $src, $amt}",
-                       [(set GR64:$dst, (rotl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
-def ROTL64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
-                       "rllg\t{$dst, $src, $amt}",
-                       [(set GR64:$dst, (rotl GR64:$src, (i32 imm:$amt)))]>;
+                       [(set GR64:$dst, (rotl GR64:$src, riaddr:$amt))]>;
 
 //===----------------------------------------------------------------------===//
 // Test instructions (like AND but do not produce any result)

diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td
index d783050358d6de005a27d8f83dc86fa28cf51520..8eccd3a4edf9fbae96461c2adb0aa0b10fd9b1ad 100644 (file)
--- a/lib/Target/SystemZ/SystemZOperands.td
+++ b/lib/Target/SystemZ/SystemZOperands.td
@@ -251,10 +251,10 @@ def s32imm64 : Operand<i64> {
 // Address operands
 
 // riaddr := reg + imm
-def riaddr32 : Operand<i32>,
-               ComplexPattern<i32, 2, "SelectAddrRI12Only", []> {
+def riaddr32 : Operand<i64>,
+               ComplexPattern<i64, 2, "SelectAddrRI12Only", []> {
   let PrintMethod = "printRIAddrOperand";
-  let MIOperandInfo = (ops ADDR32:$base, u12imm:$disp);
+  let MIOperandInfo = (ops ADDR64:$base, u12imm:$disp);
 }
 
 def riaddr12 : Operand<i64>,

diff --git a/test/CodeGen/SystemZ/2009-07-05-Shifts.ll b/test/CodeGen/SystemZ/2009-07-05-Shifts.ll
new file mode 100644 (file)
index 0000000..6e33737
--- /dev/null
+++ b/test/CodeGen/SystemZ/2009-07-05-Shifts.ll
@@ -0,0 +1,25 @@
+; RUN: llvm-as < %s | llc
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+
+define signext i32 @bit_place_piece(i32 signext %col, i32 signext %player, i64* nocapture %b1, i64* nocapture %b2) nounwind {
+entry:
+       br i1 undef, label %for.body, label %return
+
+for.body:              ; preds = %entry
+       %add = add i32 0, %col          ; <i32> [#uses=1]
+       %sh_prom = zext i32 %add to i64         ; <i64> [#uses=1]
+       %shl = shl i64 1, %sh_prom              ; <i64> [#uses=1]
+       br i1 undef, label %if.then13, label %if.else
+
+if.then13:             ; preds = %for.body
+       ret i32 0
+
+if.else:               ; preds = %for.body
+       %or34 = or i64 undef, %shl              ; <i64> [#uses=0]
+       ret i32 0
+
+return:                ; preds = %entry
+       ret i32 1
+}