Ignore IMPLICIT_DEF instructions when computing physreg liveness.

While they appear to provide a normal clobbering def, they don't
in the case of the awkward IMPLICIT_DEF+INSERT_SUBREG idiom. It
would be good to change INSERT_SUBREG; until then, this change
allows post-regalloc scheduling to cope in a mildly conservative
way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60583 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index ec56feaff9648335a17fd902f8bda5a0c482cb69..b19525cbaa82de70416c3f83f3fe25835d2eba67 100644 (file)
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -353,6 +353,13 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
        I != E; ++I, --Count) {
     MachineInstr *MI = &*I;
 
+    // After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
+    // dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF
+    // is left behind appearing to clobber the super-register, while the
+    // subregister needs to remain live. So we just ignore them.
+    if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
+      continue;
+
     // Check if this instruction has an anti-dependence that we're
     // interested in.
     DenseMap<MachineInstr *, unsigned>::iterator C = CriticalAntiDeps.find(MI);