Enable generation of AssertSext and AssertZext in the PPC backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23168 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index dad4c9fd2ec8ec023f192c04992593aa1a7c4e9b..fd9233f229c8b101695ea10dd081829885d11d34 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -214,8 +214,13 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         MF.addLiveIn(GPR[GPR_idx]);
         argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
                                             GPR[GPR_idx], MVT::i32);
-        if (ObjectVT != MVT::i32)
-          argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
+        if (ObjectVT != MVT::i32) {
+          unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 
+                                                       : ISD::AssertZext;
+          argt = DAG.getNode(AssertOp, MVT::i32, argt, 
+                             DAG.getValueType(ObjectVT));
+          argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
+        }
       } else {
         needsLoad = true;
       }