#ifdef CONFIG_ARCH_TEGRA
unsigned long timeout;
#define FSL_UDC_RUN_TIMEOUT 1000
- /* If OTG transceiver is available, then it handles the VBUS detection */
- if (!udc_controller->transceiver) {
- /* Enable cable detection interrupt, without setting the
- * USB_SYS_VBUS_WAKEUP_INT bit. USB_SYS_VBUS_WAKEUP_INT is
- * clear on write */
- temp = fsl_readl(&usb_sys_regs->vbus_wakeup);
- temp |= (USB_SYS_VBUS_WAKEUP_INT_ENABLE | USB_SYS_VBUS_WAKEUP_ENABLE);
- temp &= ~USB_SYS_VBUS_WAKEUP_INT_STATUS;
- fsl_writel(temp, &usb_sys_regs->vbus_wakeup);
- }
#endif
/* Clear stopped bit */
udc->stopped = 0;
}
/* disable ep on controller */
-#ifdef CONFIG_ARCH_TEGRA
- /* Touch the registers if cable is connected and phy is on */
- if (fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_VBUS_STATUS)
-#endif
- {
- ep_num = ep_index(ep);
- epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
- if (ep_is_in(ep))
- epctrl &= ~EPCTRL_TX_ENABLE;
- else
- epctrl &= ~EPCTRL_RX_ENABLE;
- fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
- }
+ ep_num = ep_index(ep);
+ epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+ if (ep_is_in(ep))
+ epctrl &= ~EPCTRL_TX_ENABLE;
+ else
+ epctrl &= ~EPCTRL_RX_ENABLE;
+ fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
udc = (struct fsl_udc *)ep->udc;
spin_lock_irqsave(&udc->lock, flags);
unsigned long timeout;
#define FSL_UDC_FLUSH_TIMEOUT 1000
-#ifdef CONFIG_ARCH_TEGRA
- /* Touch the registers if cable is connected and phy is on */
- if (!(fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_VBUS_STATUS))
- return;
-#endif
-
if (!_ep) {
return;
} else {