uint <-> double conversion

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30862 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index f219b2aaddd044ae973f961600f187426232ed62..f629bc3f80c4c73c1ab25ff6ca1cfc98b6469a0c 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -52,6 +52,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
   setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
   setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
 
+  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
   setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
 
   setOperationAction(ISD::RET,           MVT::Other, Custom);
@@ -103,8 +104,10 @@ namespace llvm {
       FTOSID,
 
       FUITOS,
+      FTOUIS,
 
       FUITOD,
+      FTOUID,
 
       FMRRD,
 
@@ -155,7 +158,9 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case ARMISD::FSITOD:        return "ARMISD::FSITOD";
   case ARMISD::FTOSID:        return "ARMISD::FTOSID";
   case ARMISD::FUITOS:        return "ARMISD::FUITOS";
+  case ARMISD::FTOUIS:        return "ARMISD::FTOUIS";
   case ARMISD::FUITOD:        return "ARMISD::FUITOD";
+  case ARMISD::FTOUID:        return "ARMISD::FTOUID";
   case ARMISD::FMRRD:         return "ARMISD::FMRRD";
   case ARMISD::FMDRR:         return "ARMISD::FMDRR";
   case ARMISD::FMSTAT:        return "ARMISD::FMSTAT";
@@ -614,6 +619,17 @@ static SDOperand LowerUINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
   return DAG.getNode(op, vt, Tmp);
 }
 
+static SDOperand LowerFP_TO_UINT(SDOperand Op, SelectionDAG &DAG) {
+  assert(Op.getValueType() == MVT::i32);
+  SDOperand FloatVal = Op.getOperand(0);
+  MVT::ValueType  vt = FloatVal.getValueType();
+  assert(vt == MVT::f32 || vt == MVT::f64);
+
+  ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FTOUIS : ARMISD::FTOUID;
+  SDOperand Tmp = DAG.getNode(op, MVT::f32, FloatVal);
+  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Tmp);
+}
+
 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   switch (Op.getOpcode()) {
   default:
@@ -627,6 +643,8 @@ SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     return LowerFP_TO_SINT(Op, DAG);
   case ISD::SINT_TO_FP:
     return LowerSINT_TO_FP(Op, DAG);
+  case ISD::FP_TO_UINT:
+    return LowerFP_TO_UINT(Op, DAG);
   case ISD::UINT_TO_FP:
     return LowerUINT_TO_FP(Op, DAG);
   case ISD::FORMAL_ARGUMENTS:

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 59657743406284770f1d925f02425b7c696e71a2..3281e975bcd24b266a511275f928def43ae34432 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -81,7 +81,9 @@ def armftosis      : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
 def armfsitod      : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
 def armftosid      : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
 def armfuitos      : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
+def armftouis      : SDNode<"ARMISD::FTOUIS", SDTUnaryOp>;
 def armfuitod      : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
+def armftouid      : SDNode<"ARMISD::FTOUID", SDTUnaryOp>;
 
 def SDTarmfmrrd    : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
 def armfmrrd       : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
@@ -215,9 +217,15 @@ def FTOSID  : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
 def FUITOS  : InstARM<(ops FPRegs:$dst, FPRegs:$src),
                        "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
 
+def FTOUIS  : InstARM<(ops FPRegs:$dst, FPRegs:$src),
+                       "ftouis $dst, $src", [(set FPRegs:$dst, (armftouis FPRegs:$src))]>;
+
 def FUITOD  : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
                        "fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>;
 
+def FTOUID  : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
+                       "ftouid $dst, $src", [(set FPRegs:$dst, (armftouid DFPRegs:$src))]>;
+
 def FCVTDS  : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
                        "fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
 

diff --git a/test/CodeGen/ARM/fpconv.ll b/test/CodeGen/ARM/fpconv.ll
index c20cf62f6a6195ef5ce26959258e742ca7970ec5..863c2e957b64721bd4fdac301a558f579592d488 100644 (file)
--- a/test/CodeGen/ARM/fpconv.ll
+++ b/test/CodeGen/ARM/fpconv.ll
@@ -25,3 +25,15 @@ entry:
         %tmp = cast double %x to int
         ret int %tmp
 }
+
+uint %f5(float %x) {
+entry:
+        %tmp = cast float %x to uint
+        ret uint %tmp
+}
+
+uint %f6(double %x) {
+entry:
+        %tmp = cast double %x to uint
+        ret uint %tmp
+}