media: video: tegra: Correct mclk settings for ov5650

Change-Id: I6d18b25fd88927c7ac4311fa73504badede54dd3
Signed-off-by: John Kramer <john.kramer@motorola.com>

diff --git a/drivers/media/video/tegra/ov5650.c b/drivers/media/video/tegra/ov5650.c
index 545e6db3952c15899e997e592937119a2351ec9f..c423fd8b911d722da3bdc50003bbddca4d3a566d 100644 (file)
--- a/drivers/media/video/tegra/ov5650.c
+++ b/drivers/media/video/tegra/ov5650.c
@@ -301,7 +301,7 @@ static struct ov5650_reg mode_2080x1164[] = {
 
        {0x300f, 0x8f}, // PLL control00 R_SELD5 [7:6] div by 4 R_DIVL [2] two lane div 1 SELD2P5 [1:0] div 2.5 pg 99
        {0x3010, 0x10}, // PLL control01 DIVM [3:0] DIVS [7:4] div 1 pg 99
-       {0x3011, 0x14}, // PLL control02 R_DIVP [5:0] div 20 pg 99
+       {0x3011, 0x18}, // PLL control02 R_DIVP [5:0] div 24 pg 99 (20Mhz Mclk)
        {0x3012, 0x02}, // PLL CTR 03, default
        {0x3503, 0x33}, // AEC auto AGC auto gain has delay of 2 frames. pg 38