[ARM] tegra: clocks: Set all SDMMC clocks to 48MHz at boot

48MHz is the max speed reported by present-day Tegra2 SDHCI controllers
and is the max speed we can run without adjusting for DVFS changes.

Change-Id: I3f2c23ffdfc40aebe8211688077003f09f599f1a
Signed-off-by: Todd Poynor <toddpoynor@google.com>

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index d834347d21b75b05a01d708dc5a2699da2fe2b47..3304e92b5fe15f7301639bc32c3f76a2cd81124d 100644 (file)
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-tegra/board-harmony.c
+ * arch/arm/mach-tegra/common.c
  *
  * Copyright (C) 2010 Google, Inc.
  *
@@ -46,6 +46,10 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
        { "hclk",       "sclk",         108000000,      true },
        { "pclk",       "hclk",         54000000,       true },
        { "pll_u",      "clk_m",        480000000,      false },
+       { "sdmmc1",     "pll_p",        48000000,       false},
+       { "sdmmc2",     "pll_p",        48000000,       false},
+       { "sdmmc3",     "pll_p",        48000000,       false},
+       { "sdmmc4",     "pll_p",        48000000,       false},
        { NULL,         NULL,           0,              0},
 };