// Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
//===----------------------------------------------------------------------===//
-class FRR16<bits<5> op, bits<5> _funct, dag outs, dag ins, string asmstr,
+class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
{
bits<3> ry;
bits<5> funct;
- let Opcode = op;
+ let Opcode = 0b11101;
let funct = _funct;
let Inst{10-8} = rx;
--- /dev/null
+//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes Mips16 instructions.
+//
+//===----------------------------------------------------------------------===//
+
+let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
+ isBarrier=1, hasCtrlDep=1, rx=0b000, ry=0b001 in
+def RET16 : FRR16 <0, (outs), (ins CPURAReg:$target),
+ "jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>,
+ Requires<[InMips16Mode]>;
AssemblerPredicate<"FeatureN64">;
def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
AssemblerPredicate<"!FeatureN64">;
+def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
+ AssemblerPredicate<"FeatureMips16">;
def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
AssemblerPredicate<"FeatureMips32">;
def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
AssemblerPredicate<"FeatureMips32">;
def HasStandardEncoding:
- Predicate<"Subtarget.hasStandardEncoding()">,
- AssemblerPredicate<"FeatureMips32,FeatureMips32r2,FeatureMips64"> ;
+ Predicate<"Subtarget.hasStandardEncoding()">,
+ AssemblerPredicate<"FeatureMips32,FeatureMips32r2,FeatureMips64"> ;
//===----------------------------------------------------------------------===//
// Instruction format superclass
// Mips Address Mode! SDNode frameindex could possibily be a match
// since load and store instructions from stack used it.
-def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
+def addr :
+ ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
//===----------------------------------------------------------------------===//
// Pattern fragment for load/store
// Mips16
include "Mips16InstrFormats.td"
-
+include "Mips16InstrInfo.td"
// Callee save
S0, S1)>;
+def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>;
+
// 64bit fp:
// * FGR64 - 32 64-bit registers
--- /dev/null
+; RUN: llc -march=mipsel -mcpu=mips16 < %s | FileCheck %s -check-prefix=16
+
+
+define i32 @main() nounwind {
+entry:
+ ret i32 0
+
+; 16: jr $ra
+
+}