rk3288.dtsi : fix error in commit ca55a92fcb
authorxxm <xxm@rock-chips.com>
Wed, 19 Mar 2014 06:36:05 +0000 (14:36 +0800)
committerCody Xie <Cody.Xie@rock-chips.com>
Wed, 19 Mar 2014 06:37:37 +0000 (14:37 +0800)
arch/arm/boot/dts/rk3288.dtsi

index 9de1b75582710a7e07a3a64557c94ad650fcab3c..424499669f234c6f28850fd1c2723809e8d1a78e 100755 (executable)
                pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
        };
     gpu{
-        compatible = "arm,malit764", 
-                     "arm,malit76x", 
-                     "arm,malit7xx", 
-                     "arm,mali-midgard"; 
+        compatible = "arm,malit764",
+                     "arm,malit76x",
+                     "arm,malit7xx",
+                     "arm,mali-midgard";
         reg = <0xffa40000 0x1000>;
-        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 
-                     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 
-                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-        interrupt-names = "JOB", 
-                          "MMU", 
+        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "JOB",
+                          "MMU",
                           "GPU";
     };
 
         dbgname = "iep";
         compatible = "iommu,iep_mmu";
         reg = <0xffa40000 0x10000>;
-        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
         interrupt-names = "iep_mmu";
     };
 
         dbgname = "vip";
         compatible = "iommu,vip_mmu";
         reg = <0xffa40000 0x10000>;
-        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+        interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
         interrupt-names = "vip_mmu";
     };
 
         dbgname = "isp0";
         compatible = "iommu,isp0_mmu";
         reg = <0xffa40000 0x10000>;
-        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+        interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
         interrupt-names = "isp0_mmu";
     };
 
         dbgname = "isp1";
         compatible = "iommu,isp1_mmu";
         reg = <0xffa40000 0x10000>;
-        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+        interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
         interrupt-names = "isp1_mmu";
     };
 
         dbgname = "vopb";
         compatible = "iommu,vopb_mmu";
         reg = <0xffa40000 0x10000>;
-        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+        interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
         interrupt-names = "vopb_mmu";
     };
 
         dbgname = "vopl";
         compatible = "iommu,vopl_mmu";
         reg = <0xffa40000 0x10000>;
-        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
-        interrupt-names = "vopl_mmu";};
+        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "vopl_mmu";
+    };
+
     rockchip_suspend {     
                     rockchip,ctrbits = <    
                                     (0