/* bit 0 is free */
#define RATE_FIXED (1 << 1) /* Fixed clock rate */
#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
-#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
#define cru_readl(offset) readl(RK29_CRU_BASE + offset)
#define cru_writel(v, offset) writel(v, RK29_CRU_BASE + offset)
CLK(NULL, "pclk_periph", &pclk_periph),
CLK1(vip),
- CLK("rk29_otgphy.0", "otgphy", &clk_otgphy0),
- CLK("rk29_otgphy.1", "otgphy", &clk_otgphy1),
- CLK(NULL, "uhost", &clk_uhost),
- CLK(NULL, "mac_ref_div", &clk_mac_ref_div),
- CLK(NULL, "mac_ref", &clk_mac_ref),
+ CLK1(otgphy0),
+ CLK1(otgphy1),
+ CLK1(uhost),
+ CLK1(mac_ref_div),
+ CLK1(mac_ref),
CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
CLK(NULL, "spdif", &clk_spdif),
CLK1(spi_src),
- CLK("rk29xx_spim.0", "spi0", &clk_spi0),
- CLK("rk29xx_spim.1", "spi1", &clk_spi1),
+ CLK("rk29xx_spim.0", "spi", &clk_spi0),
+ CLK("rk29xx_spim.1", "spi", &clk_spi1),
CLK1(saradc),
CLK1(timer0),
return 0;
}
-static void clk_enable_init_clocks(void)
-{
- struct clk *clkp;
-
- list_for_each_entry(clkp, &clocks, node) {
- if (clkp->flags & ENABLE_ON_INIT)
- clk_enable(clkp);
- }
-}
-
static void rk29_clock_common_init(void)
{
/* periph pll */
clk_set_rate_nolock(&arm_pll_clk, 624 * MHZ);
}
+static void clk_enable_init_clocks(void)
+{
+ clk_enable_nolock(&clk_cpu_display_ahb);
+ clk_enable_nolock(&clk_cpu_vcodec_ahb);
+ clk_enable_nolock(&clk_ddr_gpu_axi);
+ clk_enable_nolock(&clk_ddr_vdpu_axi);
+ clk_enable_nolock(&clk_ddr_vepu_axi);
+ clk_enable_nolock(&clk_display_matrix_ahb);
+ clk_enable_nolock(&clk_display_matrix_axi);
+ clk_enable_nolock(&clk_ipp_ahb);
+ clk_enable_nolock(&clk_ipp_axi);
+ clk_enable_nolock(&clk_ddr_lcdc_axi);
+ clk_enable_nolock(&clk_uhost_ahb);
+ clk_enable_nolock(&clk_usbotg1);
+ clk_enable_nolock(&clk_usbotg0);
+ clk_enable_nolock(&clk_nandc);
+ clk_enable_nolock(&clk_smc);
+ clk_enable_nolock(&clk_smc_axi);
+ clk_enable_nolock(&clk_periph_cpu);
+ clk_enable_nolock(&clk_ddr_periph);
+ clk_enable_nolock(&clk_usb);
+ clk_enable_nolock(&clk_grf);
+ clk_enable_nolock(&clk_pmu);
+ clk_enable_nolock(&clk_ddr_cpu);
+ clk_enable_nolock(&clk_ddr_reg);
+ clk_enable_nolock(&clk_ddr_phy);
+ clk_enable_nolock(&clk_gic);
+ clk_enable_nolock(&clk_dma2);
+ clk_enable_nolock(&clk_dma1);
+ clk_enable_nolock(&clk_dma0);
+ clk_enable_nolock(&clk_spdif);
+ clk_enable_nolock(&clk_i2s0);
+ /* backlight */
+ clk_enable_nolock(&clk_pwm);
+ /* vpu */
+ clk_enable_nolock(&aclk_vdpu);
+ clk_enable_nolock(&hclk_vdpu);
+ clk_enable_nolock(&clk_ddr_vdpu_axi);
+ clk_enable_nolock(&aclk_vepu);
+ clk_enable_nolock(&hclk_vepu);
+ clk_enable_nolock(&clk_ddr_vepu_axi);
+ clk_enable_nolock(&clk_cpu_vcodec_ahb);
+}
+
+static int __init clk_disable_unused(void)
+{
+ struct clk *ck;
+
+ list_for_each_entry(ck, &clocks, node) {
+ if (ck->usecount > 0 || ck->mode == NULL)
+ continue;
+
+printk("disable %s\n", ck->name);
+ LOCK();
+ clk_enable_nolock(ck);
+ clk_disable_nolock(ck);
+ UNLOCK();
+ }
+ mutex_unlock(&clocks_mutex);
+
+ return 0;
+}
+
void __init rk29_clock_init(void)
{
struct clk_lookup *lk;
* enable other clocks as necessary
*/
clk_enable_init_clocks();
+
+ /*
+ * Disable any unused clocks left on by the bootloader
+ */
+ clk_disable_unused();
}
#ifdef CONFIG_PROC_FS
int irq; \r
int ret;\r
struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
- char szBuf[8];\r
\r
if (pdata && pdata->io_init) {\r
ret = pdata->io_init(pdata->chipselect_gpios, pdata->num_chipselect);\r
\r
platform_set_drvdata(pdev, master);\r
dws = spi_master_get_devdata(master);\r
- memset(szBuf, 0, sizeof(szBuf));\r
- sprintf(szBuf, "%s%d", "spi", pdev->id);\r
- dws->clock_spim = clk_get(&pdev->dev, szBuf);\r
+ dws->clock_spim = clk_get(&pdev->dev, "spi");\r
clk_enable(dws->clock_spim);\r
if (IS_ERR(dws->clock_spim)) {\r
- dev_err(&pdev->dev, "clk_get for %s fail(%p)\n", szBuf, dws->clock_spim);\r
+ dev_err(&pdev->dev, "clk_get for spi fail(%p)\n", dws->clock_spim);\r
return PTR_ERR(dws->clock_spim);\r
}\r
\r
fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__);
+ inf->clk = clk_get(NULL, "hclk_lcdc");
+ if (IS_ERR(inf->clk))
+ {
+ printk(KERN_ERR "failed to get lcdc_hclk source\n");
+ return inf->clk;
+ }
+ clk_enable(inf->clk);
+
// set AHB access rule and disable all windows
LcdWrReg(inf, SYS_CONFIG, 0x20000000);
LcdWrReg(inf, SWAP_CTRL, 0);
// let above to take effect
LcdWrReg(inf, REG_CFG_DONE, 0x01);
- inf->clk = clk_get(&g_pdev->dev, "hclk_lcdc");
- if (!inf->clk || IS_ERR(inf->clk))
+ inf->dclk = clk_get(NULL, "dclk_lcdc");
+ if (IS_ERR(inf->dclk))
{
- printk(KERN_ERR "failed to get lcdc_hclk source\n");
+ printk(KERN_ERR "failed to get lcd dclock source\n");
return ;
}
-
- inf->dclk = clk_get(&g_pdev->dev, "dclk_lcdc");
- if (!inf->dclk || IS_ERR(inf->dclk))
+ inf->dclk_divider= clk_get(NULL, "dclk_lcdc_div");
+ if (IS_ERR(inf->dclk_divider))
{
- printk(KERN_ERR "failed to get lcd dclock source\n");
+ printk(KERN_ERR "failed to get lcd clock lcdc_divider source \n");
return ;
- }
- inf->dclk_divider= clk_get(&g_pdev->dev, "dclk_lcdc_div");
- if (!inf->dclk_divider || IS_ERR(inf->dclk_divider))
- {
- printk(KERN_ERR "failed to get lcd clock lcdc_divider source \n");
- return ;
- }
+ }
if(inf->cur_screen == &inf->panel1_info) {
- inf->dclk_parent = clk_get(&g_pdev->dev, "periph_pll");
+ inf->dclk_parent = clk_get(NULL, "periph_pll");
} else {
- inf->dclk_parent = clk_get(&g_pdev->dev, "codec_pll");
+ inf->dclk_parent = clk_get(NULL, "codec_pll");
clk_set_rate(inf->dclk_parent, 297000000);
}
- if (!inf->dclk_parent || IS_ERR(inf->dclk_parent))
+ if (IS_ERR(inf->dclk_parent))
{
- printk(KERN_ERR "failed to get lcd dclock parent source\n");
- return ;
- }
+ printk(KERN_ERR "failed to get lcd dclock parent source\n");
+ return;
+ }
- inf->aclk = clk_get(&g_pdev->dev, "aclk_lcdc");
- if (!inf->aclk || IS_ERR(inf->aclk))
+ inf->aclk = clk_get(NULL, "aclk_lcdc");
+ if (IS_ERR(inf->aclk))
{
- printk(KERN_ERR "failed to get lcd clock clk_share_mem source \n");
- return ;
- }
- inf->aclk_parent = clk_get(&g_pdev->dev, "periph_pll");
- if (!inf->dclk_parent || IS_ERR(inf->dclk_parent))
+ printk(KERN_ERR "failed to get lcd clock clk_share_mem source \n");
+ return;
+ }
+ inf->aclk_parent = clk_get(NULL, "periph_pll");
+ if (IS_ERR(inf->dclk_parent))
{
- printk(KERN_ERR "failed to get lcd dclock parent source\n");
- return ;
- }
+ printk(KERN_ERR "failed to get lcd dclock parent source\n");
+ return ;
+ }
// set lcdc clk
if(SCREEN_MCU==screen->type) screen->pixclock = 150000000; //mcu fix to 150 MHz
}
clk_enable(inf->dclk);
- clk_enable(inf->clk);
clk_enable(inf->aclk);
// init screen panel