Tests for NEON encoding of vshr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117396 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/MC/ARM/neon-shift-encoding.ll b/test/MC/ARM/neon-shift-encoding.ll
index 0c45b1480c168aec106bd32a592240243a5642c7..4c2d94fe000827b297c95894b27a5647a367e945 100644 (file)
--- a/test/MC/ARM/neon-shift-encoding.ll
+++ b/test/MC/ARM/neon-shift-encoding.ll
@@ -134,3 +134,131 @@ define <2 x i64> @vshli_2xi64(<2 x i64>* %A) nounwind {
        %tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >
        ret <2 x i64> %tmp2
 }
+
+; CHECK: vshru_8xi8
+define <8 x i8> @vshru_8xi8(<8 x i8>* %A) nounwind {
+       %tmp1 = load <8 x i8>* %A
+; CHECK: vshr.u8       d16, d16, #8            @ encoding: [0x30,0x00,0xc8,0xf3]
+       %tmp2 = lshr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+       ret <8 x i8> %tmp2
+}
+
+; CHECK: vshru_4xi16
+define <4 x i16> @vshru_4xi16(<4 x i16>* %A) nounwind {
+       %tmp1 = load <4 x i16>* %A
+; CHECK: vshr.u16      d16, d16, #16   @ encoding: [0x30,0x00,0xd0,0xf3]
+       %tmp2 = lshr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
+       ret <4 x i16> %tmp2
+}
+
+; CHECK: vshru_2xi32
+define <2 x i32> @vshru_2xi32(<2 x i32>* %A) nounwind {
+       %tmp1 = load <2 x i32>* %A
+; CHECK: vshr.u32      d16, d16, #32   @ encoding: [0x30,0x00,0xe0,0xf3]
+       %tmp2 = lshr <2 x i32> %tmp1, < i32 32, i32 32 >
+       ret <2 x i32> %tmp2
+}
+
+; CHECK: vshru_1xi64
+define <1 x i64> @vshru_1xi64(<1 x i64>* %A) nounwind {
+       %tmp1 = load <1 x i64>* %A
+; CHECK: vshr.u64      d16, d16, #64   @ encoding: [0xb0,0x00,0xc0,0xf3]
+       %tmp2 = lshr <1 x i64> %tmp1, < i64 64 >
+       ret <1 x i64> %tmp2
+}
+
+; CHECK: vshru_16xi8
+define <16 x i8> @vshru_16xi8(<16 x i8>* %A) nounwind {
+       %tmp1 = load <16 x i8>* %A
+; CHECK: vshr.u8       q8, q8, #8              @ encoding: [0x70,0x00,0xc8,0xf3]
+       %tmp2 = lshr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+       ret <16 x i8> %tmp2
+}
+
+; CHECK: vshru_8xi16
+define <8 x i16> @vshru_8xi16(<8 x i16>* %A) nounwind {
+       %tmp1 = load <8 x i16>* %A
+; CHECK: vshr.u16      q8, q8, #16     @ encoding: [0x70,0x00,0xd0,0xf3]
+       %tmp2 = lshr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+       ret <8 x i16> %tmp2
+}
+
+; CHECK: vshru_4xi32
+define <4 x i32> @vshru_4xi32(<4 x i32>* %A) nounwind {
+       %tmp1 = load <4 x i32>* %A
+; CHECK: vshr.u32      q8, q8, #32     @ encoding: [0x70,0x00,0xe0,0xf3]
+       %tmp2 = lshr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
+       ret <4 x i32> %tmp2
+}
+
+; CHECK: vshru_2xi64
+define <2 x i64> @vshru_2xi64(<2 x i64>* %A) nounwind {
+       %tmp1 = load <2 x i64>* %A
+; CHECK: vshr.u64      q8, q8, #64     @ encoding: [0xf0,0x00,0xc0,0xf3]
+       %tmp2 = lshr <2 x i64> %tmp1, < i64 64, i64 64 >
+       ret <2 x i64> %tmp2
+}
+
+; CHECK: vshrs_8xi8
+define <8 x i8> @vshrs_8xi8(<8 x i8>* %A) nounwind {
+       %tmp1 = load <8 x i8>* %A
+; CHECK: vshr.s8       d16, d16, #8            @ encoding: [0x30,0x00,0xc8,0xf2
+       %tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+       ret <8 x i8> %tmp2
+}
+
+; CHECK: vshrs_4xi16
+define <4 x i16> @vshrs_4xi16(<4 x i16>* %A) nounwind {
+       %tmp1 = load <4 x i16>* %A
+; CHECK: vshr.s16      d16, d16, #16   @ encoding: [0x30,0x00,0xd0,0xf2]
+       %tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
+       ret <4 x i16> %tmp2
+}
+
+; CHECK: vshrs_2xi32
+define <2 x i32> @vshrs_2xi32(<2 x i32>* %A) nounwind {
+       %tmp1 = load <2 x i32>* %A
+; CHECK: vshr.s32      d16, d16, #32   @ encoding: [0x30,0x00,0xe0,0xf2]
+       %tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 >
+       ret <2 x i32> %tmp2
+}
+
+; CHECK: vshrs_1xi64
+define <1 x i64> @vshrs_1xi64(<1 x i64>* %A) nounwind {
+       %tmp1 = load <1 x i64>* %A
+; CHECK: vshr.s64      d16, d16, #64   @ encoding: [0xb0,0x00,0xc0,0xf2]
+       %tmp2 = ashr <1 x i64> %tmp1, < i64 64 >
+       ret <1 x i64> %tmp2
+}
+
+; CHECK: vshrs_16xi8
+define <16 x i8> @vshrs_16xi8(<16 x i8>* %A) nounwind {
+       %tmp1 = load <16 x i8>* %A
+; CHECK: vshr.s8       q8, q8, #8              @ encoding: [0x70,0x00,0xc8,0xf2]
+       %tmp2 = ashr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+       ret <16 x i8> %tmp2
+}
+
+; CHECK: vshrs_8xi16
+define <8 x i16> @vshrs_8xi16(<8 x i16>* %A) nounwind {
+       %tmp1 = load <8 x i16>* %A
+; CHECK: vshr.s16      q8, q8, #16     @ encoding: [0x70,0x00,0xd0,0xf2]
+       %tmp2 = ashr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+       ret <8 x i16> %tmp2
+}
+
+; CHECK: vshrs_4xi32
+define <4 x i32> @vshrs_4xi32(<4 x i32>* %A) nounwind {
+       %tmp1 = load <4 x i32>* %A
+; CHECK: vshr.s32      q8, q8, #32     @ encoding: [0x70,0x00,0xe0,0xf2]
+       %tmp2 = ashr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
+       ret <4 x i32> %tmp2
+}
+
+; CHECK: vshrs_2xi64
+define <2 x i64> @vshrs_2xi64(<2 x i64>* %A) nounwind {
+       %tmp1 = load <2 x i64>* %A
+; CHECK: vshr.s64      q8, q8, #64     @ encoding: [0xf0,0x00,0xc0,0xf2]
+       %tmp2 = ashr <2 x i64> %tmp1, < i64 64, i64 64 >
+       ret <2 x i64> %tmp2
+}