#include <linux/regulator/consumer.h>\r
#include <linux/delay.h>\r
\r
-#define DVFS_DBG(fmt, args...) {while(0);}//pr_debug(fmt, ##args)\r
+#define DVFS_DBG(fmt, args...) {while(0);} //pr_debug(fmt, ##args)\r
#define DVFS_ERR(fmt, args...) pr_err(fmt, ##args)\r
#define DVFS_LOG(fmt, args...) pr_debug(fmt, ##args)//while(0)\r
\r
#define dvfs_regulator_get(dev,id) regulator_get((dev),(id))\r
-#define dvfs_regulator_put(regu) regulator_get((regu))\r
+#define dvfs_regulator_put(regu) regulator_put((regu))\r
#define dvfs_regulator_set_voltage(regu,min_uV,max_uV) regulator_set_voltage((regu),(min_uV),(max_uV))\r
#define dvfs_regulator_get_voltage(regu) regulator_get_voltage((regu))\r
\r
\r
int is_support_dvfs(struct clk_node *dvfs_info)\r
{\r
- return (dvfs_info->vd && dvfs_info->vd->vd_dvfs_target && dvfs_info->enable_dvfs);\r
+ return (dvfs_info->vd && dvfs_info->vd->vd_dvfs_target && dvfs_info->enable_dvfs);\r
}\r
+\r
int dvfs_set_rate(struct clk *clk, unsigned long rate)\r
{\r
- int ret = 0;\r
- struct vd_node *vd;\r
- DVFS_DBG("%s(%s(%lu))\n",__func__,clk->name,rate);\r
- if(!clk->dvfs_info) {\r
- DVFS_ERR("%s :This clk do not support dvfs!\n", __func__);\r
- ret = -1;\r
- } else {\r
- vd = clk->dvfs_info->vd;\r
- mutex_lock(&vd->dvfs_mutex);\r
- ret = vd->vd_dvfs_target(clk, rate);\r
- mutex_unlock(&vd->dvfs_mutex);\r
- }\r
- DVFS_DBG("%s(%s(%lu)),is end\n",__func__,clk->name,rate);\r
- return ret;\r
+ int ret = 0;\r
+ struct vd_node *vd;\r
+ DVFS_DBG("%s(%s(%lu))\n", __func__, clk->name, rate);\r
+ if (!clk->dvfs_info) {\r
+ DVFS_ERR("%s :This clk do not support dvfs!\n", __func__);\r
+ ret = -1;\r
+ } else {\r
+ vd = clk->dvfs_info->vd;\r
+ mutex_lock(&vd->dvfs_mutex);\r
+ ret = vd->vd_dvfs_target(clk, rate);\r
+ mutex_unlock(&vd->dvfs_mutex);\r
+ }\r
+ DVFS_DBG("%s(%s(%lu)),is end\n", __func__, clk->name, rate);\r
+ return ret;\r
}\r
\r
-static int dvfs_clk_get_ref_volt(struct clk_node *dvfs_clk,int rate_khz,\r
- struct cpufreq_frequency_table *clk_fv)\r
+static int dvfs_clk_get_ref_volt(struct clk_node *dvfs_clk, int rate_khz,\r
+ struct cpufreq_frequency_table *clk_fv)\r
{\r
- int i = 0;\r
- if (rate_khz == 0||!dvfs_clk||!dvfs_clk->dvfs_table) {\r
- /* since no need*/\r
- return -1;\r
- }\r
- clk_fv->frequency = rate_khz;\r
- clk_fv->index = 0;\r
- \r
- for(i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
- if(dvfs_clk->dvfs_table[i].frequency >= rate_khz) {\r
- clk_fv->frequency = dvfs_clk->dvfs_table[i].frequency;\r
- clk_fv->index = dvfs_clk->dvfs_table[i].index;\r
- // DVFS_DBG("%s,%s rate=%ukhz(vol=%d)\n",__func__,dvfs_clk->name, clk_fv->frequency, clk_fv->index);\r
- return 0;\r
- }\r
- }\r
- clk_fv->frequency = 0;\r
- clk_fv->index = 0;\r
- // DVFS_DBG("%s get corresponding voltage error! out of bound\n", dvfs_clk->name);\r
- return -1;\r
+ int i = 0;\r
+ if (rate_khz == 0 || !dvfs_clk || !dvfs_clk->dvfs_table) {\r
+ /* since no need*/\r
+ return -1;\r
+ }\r
+ clk_fv->frequency = rate_khz;\r
+ clk_fv->index = 0;\r
+\r
+ for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
+ if (dvfs_clk->dvfs_table[i].frequency >= rate_khz) {\r
+ clk_fv->frequency = dvfs_clk->dvfs_table[i].frequency;\r
+ clk_fv->index = dvfs_clk->dvfs_table[i].index;\r
+ // DVFS_DBG("%s,%s rate=%ukhz(vol=%d)\n",__func__,dvfs_clk->name, \r
+ // clk_fv->frequency, clk_fv->index);\r
+ return 0;\r
+ }\r
+ }\r
+ clk_fv->frequency = 0;\r
+ clk_fv->index = 0;\r
+ // DVFS_DBG("%s get corresponding voltage error! out of bound\n", dvfs_clk->name);\r
+ return -1;\r
}\r
\r
-static int dvfs_pd_get_newvolt_for_clk(struct pd_node *pd,struct clk_node *dvfs_clk)\r
+static int dvfs_pd_get_newvolt_byclk(struct pd_node *pd, struct clk_node *dvfs_clk)\r
{\r
struct clk_list *child;\r
int volt_max = 0;\r
- \r
- if(!pd||!dvfs_clk)\r
+\r
+ if (!pd || !dvfs_clk)\r
return 0;\r
\r
- if(dvfs_clk->set_volt>=pd->cur_volt)\r
- {\r
+ if (dvfs_clk->set_volt >= pd->cur_volt) {\r
return dvfs_clk->set_volt;\r
}\r
- \r
- list_for_each_entry(child, &pd->clk_list, node){\r
- //DVFS_DBG("%s ,pd(%s),dvfs(%s),volt(%u)\n",__func__,pd->name,dvfs_clk->name,dvfs_clk->set_volt);\r
- volt_max = max(volt_max,child->dvfs_clk->set_volt);\r
+\r
+ list_for_each_entry(child, &pd->clk_list, node) {\r
+ //DVFS_DBG("%s ,pd(%s),dvfs(%s),volt(%u)\n",__func__,pd->name,\r
+ //dvfs_clk->name,dvfs_clk->set_volt);\r
+ volt_max = max(volt_max, child->dvfs_clk->set_volt);\r
}\r
return volt_max;\r
}\r
{\r
struct pd_node *pd;\r
int i;\r
- if(!dvfs_clk)\r
- return;\r
- for(i = 0; (dvfs_clk->pds[i].pd != NULL); i++) {\r
- pd = dvfs_clk->pds[i].pd;\r
+ if (!dvfs_clk)\r
+ return;\r
+ for (i = 0; (dvfs_clk->pds[i].pd != NULL); i++) {\r
+ pd = dvfs_clk->pds[i].pd;\r
// DVFS_DBG("%s dvfs(%s),pd(%s)\n",__func__,dvfs_clk->name,pd->name);\r
- pd->cur_volt=dvfs_pd_get_newvolt_for_clk(pd,dvfs_clk);\r
+ pd->cur_volt = dvfs_pd_get_newvolt_byclk(pd, dvfs_clk);\r
}\r
}\r
\r
-static int dvfs_get_vd_volt_bypd(struct vd_node *vd)\r
+static int dvfs_vd_get_newvolt_bypd(struct vd_node *vd)\r
{\r
struct pd_node *pd;\r
- int volt_max_vd=0; \r
+ int volt_max_vd = 0;\r
list_for_each_entry(pd, &vd->pd_list, node) {\r
//DVFS_DBG("%s pd(%s,%u)\n",__func__,pd->name,pd->cur_volt);\r
- volt_max_vd = max(volt_max_vd, pd->cur_volt);\r
+ volt_max_vd = max(volt_max_vd, pd->cur_volt);\r
}\r
return volt_max_vd;\r
}\r
-static int dvfs_vd_get_newvolt_for_clk(struct clk_node *dvfs_clk)\r
+\r
+static int dvfs_vd_get_newvolt_byclk(struct clk_node *dvfs_clk)\r
{\r
- if(!dvfs_clk)\r
+ if (!dvfs_clk)\r
return -1;\r
dvfs_update_clk_pds_volt(dvfs_clk);\r
- return dvfs_get_vd_volt_bypd(dvfs_clk->vd);\r
+ return dvfs_vd_get_newvolt_bypd(dvfs_clk->vd);\r
}\r
+\r
void dvfs_clk_register_set_rate_callback(struct clk *clk, clk_dvfs_target_callback clk_dvfs_target)\r
{\r
- struct clk_node *dvfs_clk = clk_get_dvfs_info(clk);\r
- dvfs_clk->clk_dvfs_target = clk_dvfs_target;\r
+ struct clk_node *dvfs_clk = clk_get_dvfs_info(clk);\r
+ dvfs_clk->clk_dvfs_target = clk_dvfs_target;\r
}\r
-struct cpufreq_frequency_table *dvfs_get_freq_volt_table(struct clk *clk)\r
+\r
+struct cpufreq_frequency_table *dvfs_get_freq_volt_table(struct clk *clk) \r
{\r
struct clk_node *info = clk_get_dvfs_info(clk);\r
\r
- if(!info||!info->dvfs_table) {\r
- return NULL;\r
+ if (!info || !info->dvfs_table) {\r
+ return NULL;\r
}\r
mutex_lock(&mutex);\r
return info->dvfs_table;\r
mutex_unlock(&mutex);\r
}\r
+\r
int dvfs_set_freq_volt_table(struct clk *clk, struct cpufreq_frequency_table *table)\r
{\r
struct clk_node *info = clk_get_dvfs_info(clk);\r
- if(!table || !info)\r
- return -1;\r
+ if (!table || !info)\r
+ return -1;\r
\r
mutex_lock(&mutex);\r
info->dvfs_table = table;\r
mutex_unlock(&mutex);\r
return 0;\r
}\r
+\r
int clk_enable_dvfs(struct clk *clk)\r
{\r
- struct regulator *regulator;\r
- struct clk_node *dvfs_clk;\r
+ struct regulator *regulator;\r
+ struct clk_node *dvfs_clk;\r
struct cpufreq_frequency_table clk_fv;\r
- if(!clk){\r
- DVFS_ERR("clk enable dvfs error\n");\r
- return -1;\r
- } \r
- dvfs_clk=clk_get_dvfs_info(clk);\r
- if(!dvfs_clk||!dvfs_clk->vd) {\r
- DVFS_ERR("%s clk(%s) not support dvfs!\n",__func__,clk->name);\r
- return -1;\r
- }\r
- if(dvfs_clk->enable_dvfs==0){\r
- \r
- if(!dvfs_clk->vd->regulator) {\r
- regulator=NULL;\r
- if(dvfs_clk->vd->regulator_name)\r
- regulator = dvfs_regulator_get(NULL,dvfs_clk->vd->regulator_name);\r
- if(regulator)\r
- { \r
+ if (!clk) {\r
+ DVFS_ERR("clk enable dvfs error\n");\r
+ return -1;\r
+ }\r
+ dvfs_clk = clk_get_dvfs_info(clk);\r
+ if (!dvfs_clk || !dvfs_clk->vd) {\r
+ DVFS_ERR("%s clk(%s) not support dvfs!\n", __func__, clk->name);\r
+ return -1;\r
+ }\r
+ if (dvfs_clk->enable_dvfs == 0) {\r
+\r
+ if (!dvfs_clk->vd->regulator) {\r
+ regulator = NULL;\r
+ if (dvfs_clk->vd->regulator_name)\r
+ regulator = dvfs_regulator_get(NULL, dvfs_clk->vd->regulator_name);\r
+ if (regulator) {\r
//DVFS_DBG("dvfs_regulator_get(%s)\n",dvfs_clk->vd->regulator_name);\r
dvfs_clk->vd->regulator = regulator;\r
- }\r
- else\r
- {\r
+ } else {\r
dvfs_clk->vd->regulator = NULL;\r
- dvfs_clk->enable_dvfs=0;\r
- DVFS_ERR("%s can't get regulator in %s\n",dvfs_clk->name,__func__);\r
+ dvfs_clk->enable_dvfs = 0;\r
+ DVFS_ERR("%s can't get regulator in %s\n", dvfs_clk->name, __func__);\r
return -1;\r
- } \r
- }\r
- else\r
- {\r
+ }\r
+ } else {\r
dvfs_clk->vd->cur_volt = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);\r
//DVFS_DBG("%s(%s) vd volt=%u\n",__func__,dvfs_clk->name,dvfs_clk->vd->cur_volt);\r
}\r
- \r
- dvfs_clk->set_freq=dvfs_clk_get_rate_kz(clk);\r
+\r
+ dvfs_clk->set_freq = dvfs_clk_get_rate_kz(clk);\r
//DVFS_DBG("%s ,%s get freq%u!\n",__func__,dvfs_clk->name,dvfs_clk->set_freq);\r
\r
- if(dvfs_clk_get_ref_volt(dvfs_clk,dvfs_clk->set_freq,&clk_fv))\r
- {\r
- dvfs_clk->enable_dvfs=0;\r
+ if (dvfs_clk_get_ref_volt(dvfs_clk, dvfs_clk->set_freq, &clk_fv)) {\r
+ dvfs_clk->enable_dvfs = 0;\r
return -1;\r
}\r
- dvfs_clk->set_volt=clk_fv.index;\r
+ dvfs_clk->set_volt = clk_fv.index;\r
//DVFS_DBG("%s,%s,freq%u(ref vol %u)\n",__func__,dvfs_clk->name,\r
- // dvfs_clk->set_freq,dvfs_clk->set_volt);\r
+ // dvfs_clk->set_freq,dvfs_clk->set_volt);\r
#if 0\r
- if(dvfs_clk->dvfs_nb) {\r
- // must unregister when clk disable\r
- rk30_clk_notifier_register(clk, dvfs_clk->dvfs_nb);\r
- }\r
+ if (dvfs_clk->dvfs_nb) {\r
+ // must unregister when clk disable\r
+ rk30_clk_notifier_register(clk, dvfs_clk->dvfs_nb);\r
+ }\r
#endif\r
- dvfs_vd_get_newvolt_for_clk(dvfs_clk);\r
- dvfs_clk->enable_dvfs++; \r
- } else {\r
- DVFS_ERR("dvfs already enable clk enable = %d!\n", dvfs_clk->enable_dvfs);\r
- dvfs_clk->enable_dvfs++;\r
- }\r
- return 0;\r
+ dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
+ dvfs_clk->enable_dvfs++;\r
+ } else {\r
+ DVFS_ERR("dvfs already enable clk enable = %d!\n", dvfs_clk->enable_dvfs);\r
+ dvfs_clk->enable_dvfs++;\r
+ }\r
+ return 0;\r
}\r
\r
int clk_disable_dvfs(struct clk *clk)\r
{\r
- struct clk_node *dvfs_clk;\r
- dvfs_clk = clk->dvfs_info;\r
- if(!dvfs_clk->enable_dvfs) {\r
- DVFS_DBG("clk is already closed!\n");\r
- return -1;\r
- } else {\r
- dvfs_clk->enable_dvfs--;\r
- if(0 == dvfs_clk->enable_dvfs) {\r
- DVFS_ERR("clk closed!\n");\r
- rk30_clk_notifier_unregister(clk, dvfs_clk->dvfs_nb);\r
- DVFS_DBG("clk unregister nb!\n");\r
- }\r
- }\r
- return 0;\r
+ struct clk_node *dvfs_clk;\r
+ dvfs_clk = clk->dvfs_info;\r
+ if (!dvfs_clk->enable_dvfs) {\r
+ DVFS_DBG("clk is already closed!\n");\r
+ return -1;\r
+ } else {\r
+ dvfs_clk->enable_dvfs--;\r
+ if (0 == dvfs_clk->enable_dvfs) {\r
+ DVFS_ERR("clk closed!\n");\r
+ rk30_clk_notifier_unregister(clk, dvfs_clk->dvfs_nb);\r
+ DVFS_DBG("clk unregister nb!\n");\r
+ }\r
+ }\r
+ return 0;\r
}\r
\r
static int rk_dvfs_clk_notifier_event(struct notifier_block *this,\r
- unsigned long event, void *ptr)\r
+ unsigned long event, void *ptr)\r
{\r
- struct clk_notifier_data *noti_info;\r
- struct clk *clk;\r
- struct clk_node *dvfs_clk;\r
- noti_info = (struct clk_notifier_data *)ptr;\r
- clk = noti_info->clk;\r
- dvfs_clk = clk->dvfs_info;\r
-\r
- switch (event) {\r
- case CLK_PRE_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_PRE_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_POST_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_POST_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_ABORT_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_ABORT_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_PRE_ENABLE:\r
- DVFS_DBG("%s CLK_PRE_ENABLE\n", __func__);\r
- break;\r
- case CLK_POST_ENABLE:\r
- DVFS_DBG("%s CLK_POST_ENABLE\n", __func__);\r
- break;\r
- case CLK_ABORT_ENABLE:\r
- DVFS_DBG("%s CLK_ABORT_ENABLE\n", __func__);\r
- break;\r
- case CLK_PRE_DISABLE:\r
- DVFS_DBG("%s CLK_PRE_DISABLE\n", __func__);\r
- break;\r
- case CLK_POST_DISABLE:\r
- DVFS_DBG("%s CLK_POST_DISABLE\n", __func__);\r
- dvfs_clk->set_freq = 0;\r
- break;\r
- case CLK_ABORT_DISABLE:\r
- DVFS_DBG("%s CLK_ABORT_DISABLE\n", __func__);\r
-\r
- break;\r
- default:\r
- break;\r
- }\r
- return 0;\r
+ struct clk_notifier_data *noti_info;\r
+ struct clk *clk;\r
+ struct clk_node *dvfs_clk;\r
+ noti_info = (struct clk_notifier_data *)ptr;\r
+ clk = noti_info->clk;\r
+ dvfs_clk = clk->dvfs_info;\r
+\r
+ switch (event) {\r
+ case CLK_PRE_RATE_CHANGE:\r
+ DVFS_DBG("%s CLK_PRE_RATE_CHANGE\n", __func__);\r
+ break;\r
+ case CLK_POST_RATE_CHANGE:\r
+ DVFS_DBG("%s CLK_POST_RATE_CHANGE\n", __func__);\r
+ break;\r
+ case CLK_ABORT_RATE_CHANGE:\r
+ DVFS_DBG("%s CLK_ABORT_RATE_CHANGE\n", __func__);\r
+ break;\r
+ case CLK_PRE_ENABLE:\r
+ DVFS_DBG("%s CLK_PRE_ENABLE\n", __func__);\r
+ break;\r
+ case CLK_POST_ENABLE:\r
+ DVFS_DBG("%s CLK_POST_ENABLE\n", __func__);\r
+ break;\r
+ case CLK_ABORT_ENABLE:\r
+ DVFS_DBG("%s CLK_ABORT_ENABLE\n", __func__);\r
+ break;\r
+ case CLK_PRE_DISABLE:\r
+ DVFS_DBG("%s CLK_PRE_DISABLE\n", __func__);\r
+ break;\r
+ case CLK_POST_DISABLE:\r
+ DVFS_DBG("%s CLK_POST_DISABLE\n", __func__);\r
+ dvfs_clk->set_freq = 0;\r
+ break;\r
+ case CLK_ABORT_DISABLE:\r
+ DVFS_DBG("%s CLK_ABORT_DISABLE\n", __func__);\r
+\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ return 0;\r
}\r
+\r
static struct notifier_block rk_dvfs_clk_notifier = {\r
- .notifier_call = rk_dvfs_clk_notifier_event,\r
+ .notifier_call = rk_dvfs_clk_notifier_event,\r
};\r
\r
static int rk_regist_vd(struct vd_node *vd)\r
{\r
- if(!vd)\r
- return -1;\r
- mutex_lock(&mutex);\r
- mutex_init(&vd->dvfs_mutex);\r
- list_add(&vd->node, &rk_dvfs_tree);\r
- INIT_LIST_HEAD(&vd->pd_list);\r
- \r
- mutex_unlock(&mutex);\r
- return 0;\r
+ if (!vd)\r
+ return -1;\r
+ mutex_lock(&mutex);\r
+ mutex_init(&vd->dvfs_mutex);\r
+ list_add(&vd->node, &rk_dvfs_tree);\r
+ INIT_LIST_HEAD(&vd->pd_list);\r
+\r
+ mutex_unlock(&mutex);\r
+ return 0;\r
}\r
+\r
static int rk_regist_pd(struct pd_node_lookup *pd_lookup)\r
{\r
- struct vd_node *vd;\r
- struct pd_node *pd;\r
-\r
- mutex_lock(&mutex);\r
- pd = pd_lookup->pd;\r
-\r
- list_for_each_entry(vd, &rk_dvfs_tree, node) {\r
- if (vd == pd->vd) {\r
- list_add(&pd->node, &vd->pd_list);\r
- INIT_LIST_HEAD(&pd->clk_list);\r
- break;\r
- }\r
- }\r
- mutex_unlock(&mutex);\r
- return 0;\r
+ struct vd_node *vd;\r
+ struct pd_node *pd;\r
+\r
+ mutex_lock(&mutex);\r
+ pd = pd_lookup->pd;\r
+\r
+ list_for_each_entry(vd, &rk_dvfs_tree, node) {\r
+ if (vd == pd->vd) {\r
+ list_add(&pd->node, &vd->pd_list);\r
+ INIT_LIST_HEAD(&pd->clk_list);\r
+ break;\r
+ }\r
+ }\r
+ mutex_unlock(&mutex);\r
+ return 0;\r
}\r
\r
static int rk_regist_clk(struct clk_node *dvfs_clk)\r
{\r
- struct pd_node *pd;\r
- struct clk_list *child;\r
- struct clk *clk;\r
- int i = 0;\r
-\r
- if(!dvfs_clk)\r
- return -1;\r
-\r
- if(!dvfs_clk->pds)\r
- return -1;\r
- mutex_lock(&mutex);\r
- dvfs_clk->enable_dvfs = 0;\r
- dvfs_clk->vd = dvfs_clk->pds[0].pd->vd;\r
- for (i = 0; dvfs_clk->pds[i].pd != NULL; i++) {\r
- child = &(dvfs_clk->pds[i].clk_list);\r
- child->dvfs_clk = dvfs_clk;\r
- pd = dvfs_clk->pds[i].pd;\r
- list_add(&child->node, &pd->clk_list);\r
- }\r
- clk = dvfs_clk_get(NULL, dvfs_clk->name);\r
- dvfs_clk->ck=clk;\r
- clk_register_dvfs(dvfs_clk, clk);\r
- mutex_unlock(&mutex);\r
- return 0;\r
+ struct pd_node *pd;\r
+ struct clk_list *child;\r
+ struct clk *clk;\r
+ int i = 0;\r
+\r
+ if (!dvfs_clk)\r
+ return -1;\r
+\r
+ if (!dvfs_clk->pds)\r
+ return -1;\r
+ mutex_lock(&mutex);\r
+ dvfs_clk->enable_dvfs = 0;\r
+ dvfs_clk->vd = dvfs_clk->pds[0].pd->vd;\r
+ for (i = 0; dvfs_clk->pds[i].pd != NULL; i++) {\r
+ child = &(dvfs_clk->pds[i].clk_list);\r
+ child->dvfs_clk = dvfs_clk;\r
+ pd = dvfs_clk->pds[i].pd;\r
+ list_add(&child->node, &pd->clk_list);\r
+ }\r
+ clk = dvfs_clk_get(NULL, dvfs_clk->name);\r
+ dvfs_clk->ck = clk;\r
+ clk_register_dvfs(dvfs_clk, clk);\r
+ mutex_unlock(&mutex);\r
+ return 0;\r
}\r
\r
+#define get_volt_up_delay(new_volt, old_volt) \\r
+ ((new_volt) > (old_volt) ? (((new_volt) - (old_volt)) >> 10) : 0)\r
+\r
+\r
+static int flag_core_set_volt_err = 0;\r
int dvfs_target_core(struct clk *clk, unsigned long rate_hz)\r
{\r
- struct clk_node *dvfs_clk;\r
- unsigned int volt_vd_new = 0,volt_vd_old = 0,volt_clk_old=0;\r
- struct cpufreq_frequency_table clk_fv = {0, 0};\r
- int ret = 0;\r
+ struct clk_node *dvfs_clk;\r
+ unsigned int volt_new = 0, volt_old = 0, volt_clk_old = 0;\r
+ struct cpufreq_frequency_table clk_fv = {0, 0};\r
+ int ret = 0;\r
+ int flag_set_volt_correct = 0;\r
unsigned long temp_hz;\r
\r
- if(!clk)\r
- {\r
- DVFS_ERR("%s is not clk\n",__func__);\r
+ if (!clk) {\r
+ DVFS_ERR("%s is not clk\n", __func__);\r
return -1;\r
}\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
+ dvfs_clk = clk_get_dvfs_info(clk);\r
+\r
+ if (!dvfs_clk || dvfs_clk->vd->regulator == NULL) {\r
+ DVFS_ERR("%s can't get dvfs regulater\n", clk->name);\r
+ return -1;\r
+ }\r
+\r
+ temp_hz = rate_hz;//clk_round_rate_nolock(clk, rate_hz);\r
\r
- if(!dvfs_clk||dvfs_clk->vd->regulator == NULL) {\r
- DVFS_ERR("%s can't get dvfs regulater\n", clk->name);\r
- return -1;\r
- }\r
- \r
- temp_hz = rate_hz;//clk_round_rate_nolock(clk, rate_hz);\r
- \r
//DVFS_DBG("dvfs(%s) round rate(%lu)(rount %lu)\n",dvfs_clk->name,rate_hz,temp_hz);\r
\r
- /* find the clk corresponding voltage */\r
- if (dvfs_clk_get_ref_volt(dvfs_clk, temp_hz/1000, &clk_fv)) {\r
- DVFS_ERR("%s--%s:rate%lu,Get corresponding voltage error!\n",__func__,dvfs_clk->name,temp_hz);\r
- return -1;\r
- }\r
- volt_vd_old = dvfs_clk->vd->cur_volt;\r
+ /* find the clk corresponding voltage */\r
+ if (dvfs_clk_get_ref_volt(dvfs_clk, temp_hz / 1000, &clk_fv)) {\r
+ DVFS_ERR("%s--%s:rate%lu,Get corresponding voltage error!\n", \r
+ __func__, dvfs_clk->name, temp_hz);\r
+ return -1;\r
+ }\r
+ volt_old = dvfs_clk->vd->cur_volt;\r
\r
- volt_clk_old=dvfs_clk->set_volt;\r
+ volt_clk_old = dvfs_clk->set_volt;\r
\r
- dvfs_clk->set_volt=clk_fv.index;\r
+ dvfs_clk->set_volt = clk_fv.index;\r
\r
- volt_vd_new = dvfs_vd_get_newvolt_for_clk(dvfs_clk);\r
+ volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
\r
DVFS_LOG("dvfs--(%s),volt=%d(was %dmV),rate=%lu(was %lu),vd%u=(was%u)\n",\r
- dvfs_clk->name,clk_fv.index,dvfs_clk->set_volt,temp_hz,clk_get_rate(clk)\r
- ,volt_vd_new,volt_vd_old);\r
- // if up the voltage\r
- #if 1\r
- if (volt_vd_old < volt_vd_new) {\r
- if(dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_vd_new, volt_vd_new) < 0) {\r
- DVFS_ERR("set voltage err\n");\r
- return -1;\r
- }\r
- dvfs_clk->vd->cur_volt=volt_vd_new;\r
- }\r
- #endif\r
- if(dvfs_clk->clk_dvfs_target) {\r
- ret = dvfs_clk->clk_dvfs_target(clk, temp_hz, clk_set_rate_locked);\r
- } else {\r
- ret = clk_set_rate_locked(clk, temp_hz);\r
- }\r
- if (ret < 0) {\r
- \r
- dvfs_clk->set_volt=volt_vd_old;\r
- dvfs_vd_get_newvolt_for_clk(dvfs_clk); \r
- DVFS_ERR("set rate err\n");\r
- return -1;\r
- }\r
- dvfs_clk->set_freq = temp_hz/1000;\r
- #if 1\r
- if (volt_vd_old > volt_vd_new){\r
- if(dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_vd_new, volt_vd_new) < 0) {\r
- DVFS_ERR("set voltage err\n");\r
+ dvfs_clk->name, clk_fv.index, dvfs_clk->set_volt, temp_hz, clk_get_rate(clk)\r
+ , volt_new, volt_old);\r
+\r
+ if (flag_core_set_volt_err) {\r
+ /* It means the last time set voltage error */ \r
+ flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);\r
+ if (flag_set_volt_correct <= 0) {\r
+ DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload core_volt error %d!!! stop scaling\n", \r
+ __func__, dvfs_clk->name, volt_new, volt_old, \r
+ temp_hz, clk_get_rate(clk), flag_set_volt_correct);\r
+ return -1;\r
+ }\r
+\r
+ flag_core_set_volt_err = 0;\r
+ DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload core_volt! core_volt_correct = %d\n", \r
+ __func__, dvfs_clk->name, volt_new, volt_old, \r
+ temp_hz, clk_get_rate(clk), flag_set_volt_correct);\r
+\r
+ /* Reset vd's voltage */\r
+ dvfs_clk->vd->cur_volt = flag_set_volt_correct;\r
+ volt_old = dvfs_clk->vd->cur_volt;\r
+ }\r
+\r
+ /* if up the voltage */\r
+ if (volt_old < volt_new) {\r
+ if (dvfs_clk->vd->regulator) {\r
+ ret = dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new);\r
+ if (ret < 0) {\r
+ flag_core_set_volt_err = 1;\r
+ DVFS_ERR("%s %s set voltage up err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n", \r
+ __func__, dvfs_clk->name, ret, \r
+ temp_hz, clk_get_rate(clk), volt_new, volt_old);\r
+ return -1;\r
+ }\r
+\r
+ } else {\r
+ DVFS_ERR("%s up volt dvfs_clk->vd->regulator == NULL\n", __func__);\r
return -1;\r
- }\r
- dvfs_clk->vd->cur_volt=volt_vd_new;\r
- }\r
- #endif\r
- return 0;\r
+ }\r
+\r
+ dvfs_clk->vd->cur_volt = volt_new;\r
+ udelay(get_volt_up_delay(volt_new, volt_old));\r
+ DVFS_LOG("%s %s set voltage OK up ret = %d, Vnew = %d(was %d), Rnew = %lu(was %lu)\n", \r
+ __func__, dvfs_clk->name, ret, volt_new, volt_old, temp_hz, clk_get_rate(clk));\r
+ }\r
+\r
+ if (dvfs_clk->clk_dvfs_target) {\r
+ ret = dvfs_clk->clk_dvfs_target(clk, temp_hz, clk_set_rate_locked);\r
+ } else {\r
+ ret = clk_set_rate_locked(clk, temp_hz);\r
+ }\r
+\r
+ if (ret < 0) {\r
+\r
+ dvfs_clk->set_volt = volt_old;\r
+ dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
+ DVFS_ERR("set rate err\n");\r
+ return -1;\r
+ }\r
+ dvfs_clk->set_freq = temp_hz / 1000;\r
+\r
+ /* if down the voltage */\r
+ if (volt_old > volt_new) {\r
+ if (dvfs_clk->vd->regulator) {\r
+ ret = dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new);\r
+ if (ret < 0) {\r
+ flag_core_set_volt_err = 1;\r
+ DVFS_ERR("%s %s set voltage down err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n", \r
+ __func__, dvfs_clk->name, ret, temp_hz, clk_get_rate(clk), \r
+ volt_new, volt_old);\r
+ return -1;\r
+ }\r
+\r
+ } else {\r
+ DVFS_ERR("%s down volt dvfs_clk->vd->regulator == NULL\n", __func__);\r
+ return -1;\r
+ }\r
+\r
+ dvfs_clk->vd->cur_volt = volt_new;\r
+ DVFS_LOG("dvfs %s set volt ok dn\n", dvfs_clk->name);\r
+\r
+ }\r
+\r
+ return 0;\r
}\r
-#define get_volt_up_delay(new_volt,old_volt) ((new_volt)>(old_volt)?\\r
- (((new_volt)-(old_volt))>>10):0)\r
\r
+static int flag_arm_set_volt_err = 0;\r
int dvfs_target_cpu(struct clk *clk, unsigned long rate_hz)\r
{\r
- struct clk_node *dvfs_clk;\r
- int volt_new = 0, volt_old = 0;\r
- struct cpufreq_frequency_table clk_fv;\r
- int ret = 0;\r
+ struct clk_node *dvfs_clk;\r
+ int volt_new = 0, volt_old = 0;\r
+ struct cpufreq_frequency_table clk_fv;\r
+ int ret = 0;\r
+ int flag_set_volt_correct = 0;\r
unsigned long temp_hz;\r
\r
- if(!clk)\r
- {\r
- DVFS_ERR("%s is not clk\n",__func__);\r
+ if (!clk) {\r
+ DVFS_ERR("%s is not clk\n", __func__);\r
+ return -1;\r
+ }\r
+ dvfs_clk = clk_get_dvfs_info(clk);\r
+\r
+ if (!dvfs_clk || dvfs_clk->vd->regulator == NULL) {\r
+ DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
+ return -1;\r
+ }\r
+\r
+ /* need round rate */\r
+ temp_hz = clk_round_rate_nolock(clk, rate_hz);\r
+ DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu)\n", dvfs_clk->name, rate_hz, temp_hz);\r
+\r
+ /* find the clk corresponding voltage */\r
+ if (0 != dvfs_clk_get_ref_volt(dvfs_clk, temp_hz / 1000, &clk_fv)) {\r
+ DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
return -1;\r
}\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- \r
- if(!dvfs_clk||dvfs_clk->vd->regulator == NULL) {\r
- DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
- return -1;\r
- }\r
- /* need round rate */\r
- temp_hz = clk_round_rate_nolock(clk, rate_hz);\r
- \r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu)\n",dvfs_clk->name,rate_hz,temp_hz);\r
-\r
- /* find the clk corresponding voltage */\r
- if (0 != dvfs_clk_get_ref_volt(dvfs_clk, temp_hz/1000, &clk_fv)) {\r
- DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n",dvfs_clk->name, rate_hz);\r
- return -1;\r
- }\r
- volt_old = dvfs_clk->vd->cur_volt;\r
- volt_new = clk_fv.index;\r
-\r
- DVFS_LOG("%s--(%s),volt=%d(was %dmV),rate=%lu(was %lu),vd=%u(was %u)\n",__func__,\r
- dvfs_clk->name,volt_new,volt_old,temp_hz,clk_get_rate(clk)\r
- ,volt_new,volt_old);\r
- /* if up the voltage*/\r
- if (volt_old < volt_new) {\r
- if(dvfs_clk->vd->regulator&&dvfs_regulator_set_voltage(dvfs_clk->vd->regulator,volt_new, volt_new) < 0) {\r
- DVFS_ERR("set voltage err up\n");\r
- return -1;\r
- }\r
- dvfs_clk->vd->cur_volt = volt_new;\r
- DVFS_LOG("%s set volt ok up\n",dvfs_clk->name); \r
- udelay(get_volt_up_delay(volt_new,volt_old));\r
- //DVFS_DBG("get_volt_up_delay%u",get_volt_up_delay(volt_new,volt_old));\r
- }\r
- \r
- if(dvfs_clk->clk_dvfs_target) {\r
- ret = dvfs_clk->clk_dvfs_target(clk, temp_hz, clk_set_rate_locked);\r
- } else {\r
- ret = clk_set_rate_locked(clk, temp_hz);\r
- }\r
- if (ret < 0) {\r
- DVFS_ERR("set rate err\n");\r
- return -1;\r
- } \r
- dvfs_clk->set_freq = temp_hz/1000;\r
- \r
- DVFS_LOG("dvfs %s set rate%lu ok\n",dvfs_clk->name,clk_get_rate(clk));\r
- \r
- /* if down the voltage */\r
- if (volt_old > volt_new) {\r
- if(dvfs_clk->vd->regulator&&dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new) < 0) {\r
- DVFS_ERR("set voltage err dn\n");\r
- return -1;\r
- }\r
- dvfs_clk->vd->cur_volt = volt_new;\r
- DVFS_LOG("dvfs %s set volt ok dn\n",dvfs_clk->name);\r
- \r
- }\r
- return ret;\r
+\r
+ volt_old = dvfs_clk->vd->cur_volt;\r
+ volt_new = clk_fv.index;\r
+ if (flag_arm_set_volt_err) {\r
+ /* It means the last time set voltage error */\r
+ flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);\r
+ if (flag_set_volt_correct <= 0) {\r
+ DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload arm_volt error %d!!! stop scaling\n", \r
+ __func__, dvfs_clk->name, volt_new, volt_old, \r
+ temp_hz, clk_get_rate(clk), flag_set_volt_correct);\r
+ return -1;\r
+ }\r
+\r
+ flag_arm_set_volt_err = 0;\r
+ DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload arm_volt! arm_volt_correct = %d\n", \r
+ __func__, dvfs_clk->name, volt_new, volt_old, \r
+ temp_hz, clk_get_rate(clk), flag_set_volt_correct);\r
+\r
+ /* Reset vd's voltage */\r
+ dvfs_clk->vd->cur_volt = flag_set_volt_correct;\r
+ volt_old = dvfs_clk->vd->cur_volt;\r
+ }\r
+\r
+ /* if up the voltage */\r
+ if (volt_old < volt_new) {\r
+ if (dvfs_clk->vd->regulator) {\r
+ ret = dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new);\r
+ if (ret < 0) {\r
+ flag_arm_set_volt_err = 1;\r
+ DVFS_ERR("%s %s set voltage up err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n", \r
+ __func__, dvfs_clk->name, ret, temp_hz, clk_get_rate(clk), \r
+ volt_new, volt_old);\r
+ return -1;\r
+ }\r
+\r
+ } else {\r
+ DVFS_ERR("%s up volt dvfs_clk->vd->regulator == NULL\n", __func__);\r
+ return -1;\r
+ }\r
+\r
+ dvfs_clk->vd->cur_volt = volt_new;\r
+ udelay(get_volt_up_delay(volt_new, volt_old));\r
+ DVFS_LOG("%s %s set voltage OK up ret = %d, Vnew = %d(was %d), Rnew = %lu(was %lu)\n", \r
+ __func__, dvfs_clk->name, ret, volt_new, volt_old, temp_hz, clk_get_rate(clk));\r
+ }\r
+\r
+ if (dvfs_clk->clk_dvfs_target) {\r
+ ret = dvfs_clk->clk_dvfs_target(clk, temp_hz, clk_set_rate_locked);\r
+ } else {\r
+ ret = clk_set_rate_locked(clk, temp_hz);\r
+ }\r
+\r
+ if (ret < 0) {\r
+ DVFS_ERR("set rate err\n");\r
+ return -1;\r
+ }\r
+ dvfs_clk->set_freq = temp_hz / 1000;\r
+\r
+ DVFS_LOG("dvfs %s set rate%lu ok\n", dvfs_clk->name, clk_get_rate(clk));\r
+\r
+ /* if down the voltage */\r
+ if (volt_old > volt_new) {\r
+ if (dvfs_clk->vd->regulator) {\r
+ ret = dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new);\r
+ if (ret < 0) {\r
+ flag_arm_set_volt_err = 1;\r
+ DVFS_ERR("%s %s set voltage down err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n", \r
+ __func__, dvfs_clk->name, ret, temp_hz, clk_get_rate(clk), \r
+ volt_new, volt_old);\r
+ return -1;\r
+ }\r
+\r
+ } else {\r
+ DVFS_ERR("%s down volt dvfs_clk->vd->regulator == NULL\n", __func__);\r
+ return -1;\r
+ }\r
+\r
+ dvfs_clk->vd->cur_volt = volt_new;\r
+ DVFS_LOG("dvfs %s set volt ok dn\n", dvfs_clk->name);\r
+\r
+ }\r
+ return ret;\r
}\r
\r
\r
\r
/*****************************init**************************/\r
/**\r
-* rate must be raising sequence\r
-*/\r
+ * rate must be raising sequence\r
+ */\r
static struct cpufreq_frequency_table cpu_dvfs_table[] = {\r
- //{.frequency = 48*DVFS_KHZ, .index = 920*DVFS_MV},\r
- //{.frequency = 126*DVFS_KHZ, .index = 970*DVFS_MV},\r
- // {.frequency = 252*DVFS_KHZ, .index = 1040*DVFS_MV},\r
- // {.frequency = 504*DVFS_KHZ, .index = 1060*DVFS_MV},\r
- {.frequency = 816*DVFS_KHZ, .index = 1080*DVFS_MV},\r
- // {.frequency = 1008*DVFS_KHZ, .index = 1100*DVFS_MV},\r
+ //{.frequency = 48 * DVFS_KHZ, .index = 920*DVFS_MV},\r
+ //{.frequency = 126 * DVFS_KHZ, .index = 970 * DVFS_MV},\r
+ // {.frequency = 252 * DVFS_KHZ, .index = 1040 * DVFS_MV},\r
+ // {.frequency = 504 * DVFS_KHZ, .index = 1060 * DVFS_MV},\r
+ {.frequency = 816 * DVFS_KHZ, .index = 1080 * DVFS_MV},\r
+ // {.frequency = 1008 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
{.frequency = CPUFREQ_TABLE_END},\r
};\r
+\r
static struct cpufreq_frequency_table ddr_dvfs_table[] = {\r
- //{.frequency = 100*DVFS_KHZ, .index = 1100*DVFS_MV},\r
- {.frequency = 200*DVFS_KHZ, .index = 1000*DVFS_MV},\r
- {.frequency = 300*DVFS_KHZ, .index = 1050*DVFS_MV},\r
- {.frequency = 400*DVFS_KHZ, .index = 1100*DVFS_MV},\r
- {.frequency = 500*DVFS_KHZ, .index = 1150*DVFS_MV},\r
- {.frequency = 600*DVFS_KHZ, .index = 1200*DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END}, \r
+ //{.frequency = 100 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
+ {.frequency = 200 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
+ {.frequency = 300 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
+ {.frequency = 400 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
+ {.frequency = 500 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
+ {.frequency = 600 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
+ {.frequency = CPUFREQ_TABLE_END},\r
};\r
+\r
static struct cpufreq_frequency_table gpu_dvfs_table[] = {\r
- {.frequency = 100*DVFS_KHZ, .index = 1000*DVFS_MV},\r
- {.frequency = 200*DVFS_KHZ, .index = 1050*DVFS_MV},\r
- {.frequency = 300*DVFS_KHZ, .index = 1100*DVFS_MV},\r
- {.frequency = 400*DVFS_KHZ, .index = 1150*DVFS_MV},\r
- {.frequency = 500*DVFS_KHZ, .index = 1200*DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END}, \r
+ {.frequency = 100 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
+ {.frequency = 200 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
+ {.frequency = 300 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
+ {.frequency = 400 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
+ {.frequency = 500 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
+ {.frequency = CPUFREQ_TABLE_END},\r
};\r
\r
static struct cpufreq_frequency_table peri_aclk_dvfs_table[] = {\r
- {.frequency = 100*DVFS_KHZ, .index = 1000*DVFS_MV},\r
- {.frequency = 200*DVFS_KHZ, .index = 1050*DVFS_MV},\r
- {.frequency = 300*DVFS_KHZ, .index = 1070*DVFS_MV},\r
- {.frequency = 500*DVFS_KHZ, .index = 1100*DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END}, \r
+ {.frequency = 100 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
+ {.frequency = 200 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
+ {.frequency = 300 * DVFS_KHZ, .index = 1070 * DVFS_MV},\r
+ {.frequency = 500 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
+ {.frequency = CPUFREQ_TABLE_END},\r
};\r
\r
static struct vd_node vd_cpu = {\r
- .name = "vd_cpu",\r
+ .name = "vd_cpu",\r
.regulator_name = "vdd_cpu",\r
- .vd_dvfs_target = dvfs_target_cpu,\r
+ .vd_dvfs_target = dvfs_target_cpu,\r
};\r
\r
static struct vd_node vd_core = {\r
- .name = "vd_core",\r
+ .name = "vd_core",\r
.regulator_name = "vdd_core",\r
- .vd_dvfs_target = dvfs_target_core,\r
+ .vd_dvfs_target = dvfs_target_core,\r
};\r
\r
static struct vd_node vd_rtc = {\r
- .name = "vd_rtc",\r
+ .name = "vd_rtc",\r
.regulator_name = "vdd_rtc",\r
- .vd_dvfs_target = NULL,\r
+ .vd_dvfs_target = NULL,\r
};\r
\r
-static struct vd_node *rk30_vds[] = {&vd_cpu,&vd_core,&vd_rtc};\r
+static struct vd_node *rk30_vds[] = {&vd_cpu, &vd_core, &vd_rtc};\r
\r
static struct pd_node pd_a9_0 = {\r
- .name = "pd_a9_0",\r
- .vd = &vd_cpu,\r
+ .name = "pd_a9_0",\r
+ .vd = &vd_cpu,\r
};\r
static struct pd_node pd_a9_1 = {\r
- .name = "pd_a9_1",\r
- .vd = &vd_cpu,\r
+ .name = "pd_a9_1",\r
+ .vd = &vd_cpu,\r
};\r
static struct pd_node pd_debug = {\r
- .name = "pd_debug",\r
- .vd = &vd_cpu,\r
+ .name = "pd_debug",\r
+ .vd = &vd_cpu,\r
};\r
static struct pd_node pd_scu = {\r
- .name = "pd_scu",\r
- .vd = &vd_cpu,\r
+ .name = "pd_scu",\r
+ .vd = &vd_cpu,\r
};\r
static struct pd_node pd_video = {\r
- .name = "pd_video",\r
- .vd = &vd_core,\r
+ .name = "pd_video",\r
+ .vd = &vd_core,\r
};\r
static struct pd_node pd_vio = {\r
- .name = "pd_vio",\r
- .vd = &vd_core,\r
+ .name = "pd_vio",\r
+ .vd = &vd_core,\r
};\r
static struct pd_node pd_gpu = {\r
- .name = "pd_gpu",\r
- .vd = &vd_core,\r
+ .name = "pd_gpu",\r
+ .vd = &vd_core,\r
};\r
static struct pd_node pd_peri = {\r
- .name = "pd_peri",\r
- .vd = &vd_core,\r
+ .name = "pd_peri",\r
+ .vd = &vd_core,\r
};\r
static struct pd_node pd_cpu = {\r
- .name = "pd_cpu",\r
- .vd = &vd_core,\r
+ .name = "pd_cpu",\r
+ .vd = &vd_core,\r
};\r
static struct pd_node pd_alive = {\r
- .name = "pd_alive",\r
- .vd = &vd_core,\r
+ .name = "pd_alive",\r
+ .vd = &vd_core,\r
};\r
static struct pd_node pd_rtc = {\r
- .name = "pd_rtc",\r
- .vd = &vd_rtc,\r
+ .name = "pd_rtc",\r
+ .vd = &vd_rtc,\r
};\r
#define LOOKUP_PD(_ppd) \\r
{ \\r
.pd = _ppd, \\r
}\r
static struct pd_node_lookup rk30_pds[] = {\r
- LOOKUP_PD(&pd_a9_0),\r
- LOOKUP_PD(&pd_a9_1),\r
- LOOKUP_PD(&pd_debug),\r
- LOOKUP_PD(&pd_scu),\r
- LOOKUP_PD(&pd_video),\r
- LOOKUP_PD(&pd_vio),\r
- LOOKUP_PD(&pd_gpu),\r
- LOOKUP_PD(&pd_peri),\r
- LOOKUP_PD(&pd_cpu),\r
- LOOKUP_PD(&pd_alive),\r
- LOOKUP_PD(&pd_rtc),\r
+ LOOKUP_PD(&pd_a9_0),\r
+ LOOKUP_PD(&pd_a9_1),\r
+ LOOKUP_PD(&pd_debug),\r
+ LOOKUP_PD(&pd_scu),\r
+ LOOKUP_PD(&pd_video),\r
+ LOOKUP_PD(&pd_vio),\r
+ LOOKUP_PD(&pd_gpu),\r
+ LOOKUP_PD(&pd_peri),\r
+ LOOKUP_PD(&pd_cpu),\r
+ LOOKUP_PD(&pd_alive),\r
+ LOOKUP_PD(&pd_rtc),\r
};\r
\r
#define CLK_PDS(_ppd) \\r
}\r
\r
static struct pds_list cpu_pds[] = {\r
- CLK_PDS(&pd_a9_0),\r
- CLK_PDS(&pd_a9_1),\r
- CLK_PDS(NULL),\r
+ CLK_PDS(&pd_a9_0),\r
+ CLK_PDS(&pd_a9_1),\r
+ CLK_PDS(NULL),\r
};\r
+\r
static struct pds_list ddr_pds[] = {\r
- CLK_PDS(&pd_cpu),\r
- CLK_PDS(NULL),\r
+ CLK_PDS(&pd_cpu),\r
+ CLK_PDS(NULL),\r
};\r
+\r
static struct pds_list gpu_pds[] = {\r
- CLK_PDS(&pd_gpu),\r
- CLK_PDS(NULL),\r
+ CLK_PDS(&pd_gpu),\r
+ CLK_PDS(NULL),\r
};\r
\r
#define RK_CLKS(_clk_name, _ppds, _dvfs_table, _dvfs_nb) \\r
- { \\r
+{ \\r
.name = _clk_name, \\r
.pds = _ppds,\\r
.dvfs_table = _dvfs_table, \\r
.dvfs_nb = _dvfs_nb, \\r
- }\r
+}\r
\r
static struct pds_list aclk_periph_pds[] = {\r
- CLK_PDS(&pd_peri),\r
- CLK_PDS(NULL),\r
+ CLK_PDS(&pd_peri),\r
+ CLK_PDS(NULL),\r
};\r
\r
\r
static struct clk_node rk30_clks[] = {\r
- RK_CLKS("cpu", cpu_pds, cpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("ddr", ddr_pds, ddr_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("gpu", gpu_pds, gpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("aclk_periph", aclk_periph_pds, peri_aclk_dvfs_table,&rk_dvfs_clk_notifier),\r
+ RK_CLKS("cpu", cpu_pds, cpu_dvfs_table, &rk_dvfs_clk_notifier),\r
+ RK_CLKS("ddr", ddr_pds, ddr_dvfs_table, &rk_dvfs_clk_notifier),\r
+ RK_CLKS("gpu", gpu_pds, gpu_dvfs_table, &rk_dvfs_clk_notifier),\r
+ RK_CLKS("aclk_periph", aclk_periph_pds, peri_aclk_dvfs_table, &rk_dvfs_clk_notifier),\r
};\r
\r
int rk30_dvfs_init(void)\r
{\r
- int i = 0;\r
- for (i = 0; i < ARRAY_SIZE(rk30_vds); i++) {\r
- rk_regist_vd(rk30_vds[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_pds); i++) {\r
- rk_regist_pd(&rk30_pds[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_clks); i++) {\r
- rk_regist_clk(&rk30_clks[i]);\r
- }\r
- \r
- return 0;\r
+ int i = 0;\r
+ for (i = 0; i < ARRAY_SIZE(rk30_vds); i++) {\r
+ rk_regist_vd(rk30_vds[i]);\r
+ }\r
+ for (i = 0; i < ARRAY_SIZE(rk30_pds); i++) {\r
+ rk_regist_pd(&rk30_pds[i]);\r
+ }\r
+ for (i = 0; i < ARRAY_SIZE(rk30_clks); i++) {\r
+ rk_regist_clk(&rk30_clks[i]);\r
+ }\r
+\r
+ return 0;\r
}\r
\r
-#if 1\r
+//#define DVFS_DUMP_DBG\r
+#ifdef DVFS_DUMP_DBG\r
/**\r
* dump_dbg_map() : Draw all informations of dvfs while debug\r
*/\r
static void dump_dbg_map(void)\r
{\r
- int i;\r
- struct vd_node *vd;\r
- struct pd_node *pd, *clkparent;\r
- struct clk_list *child;\r
- struct clk_node *dvfs_clk;\r
-\r
- DVFS_DBG("-------------DVFS DEBUG-----------\n\n\n");\r
- DVFS_DBG("RK30 DVFS TREE:\n");\r
- list_for_each_entry(vd, &rk_dvfs_tree, node) {\r
- DVFS_DBG("|\n|- voltage domain:%s\n", vd->name);\r
- DVFS_DBG("|- current voltage:%d\n", vd->cur_volt);\r
-\r
- list_for_each_entry(pd, &vd->pd_list, node) {\r
- DVFS_DBG("| |\n| |- power domain:%s, status = %s, current volt = %d\n",\r
- pd->name, (pd->pd_status == PD_ON) ? "ON" : "OFF", pd->cur_volt);\r
-\r
- list_for_each_entry(child, &pd->clk_list, node) {\r
- dvfs_clk = child->dvfs_clk;\r
- DVFS_DBG("| | |\n| | |- clock: %s current: rate %d, volt = %d, enable_dvfs = %s\n",\r
- dvfs_clk->name, dvfs_clk->set_freq, dvfs_clk->set_volt, dvfs_clk->enable_dvfs == 0 ? "DISABLE" : "ENABLE");\r
- for (i = 0; dvfs_clk->pds[i].pd != NULL; i++) {\r
- clkparent = dvfs_clk->pds[i].pd;\r
- DVFS_DBG("| | | |- clock parents: %s, vd_parent = %s\n", clkparent->name, clkparent->vd->name);\r
- }\r
-\r
- for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
- DVFS_DBG("| | | |- freq = %d, volt = %d\n", dvfs_clk->dvfs_table[i].frequency, dvfs_clk->dvfs_table[i].index);\r
-\r
- }\r
- }\r
- }\r
- }\r
- DVFS_DBG("-------------DVFS DEBUG END------------\n");\r
+ int i;\r
+ struct vd_node *vd;\r
+ struct pd_node *pd, *clkparent;\r
+ struct clk_list *child;\r
+ struct clk_node *dvfs_clk;\r
+\r
+ DVFS_DBG("-------------DVFS DEBUG-----------\n\n\n");\r
+ DVFS_DBG("RK30 DVFS TREE:\n");\r
+ list_for_each_entry(vd, &rk_dvfs_tree, node) {\r
+ DVFS_DBG("|\n|- voltage domain:%s\n", vd->name);\r
+ DVFS_DBG("|- current voltage:%d\n", vd->cur_volt);\r
+\r
+ list_for_each_entry(pd, &vd->pd_list, node) {\r
+ DVFS_DBG("| |\n| |- power domain:%s, status = %s, current volt = %d\n",\r
+ pd->name, (pd->pd_status == PD_ON) ? "ON" : "OFF", pd->cur_volt);\r
+\r
+ list_for_each_entry(child, &pd->clk_list, node) {\r
+ dvfs_clk = child->dvfs_clk;\r
+ DVFS_DBG("| | |\n| | |- clock: %s current: rate %d, volt = %d, enable_dvfs = %s\n",\r
+ dvfs_clk->name, dvfs_clk->set_freq, dvfs_clk->set_volt, \r
+ dvfs_clk->enable_dvfs == 0 ? "DISABLE" : "ENABLE");\r
+ for (i = 0; dvfs_clk->pds[i].pd != NULL; i++) {\r
+ clkparent = dvfs_clk->pds[i].pd;\r
+ DVFS_DBG("| | | |- clock parents: %s, vd_parent = %s\n", \r
+ clkparent->name, clkparent->vd->name);\r
+ }\r
+\r
+ for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
+ DVFS_DBG("| | | |- freq = %d, volt = %d\n", \r
+ dvfs_clk->dvfs_table[i].frequency, \r
+ dvfs_clk->dvfs_table[i].index);\r
+\r
+ }\r
+ }\r
+ }\r
+ }\r
+ DVFS_DBG("-------------DVFS DEBUG END------------\n");\r
}\r
#endif\r
\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff